STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Prod
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STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Products
STD90/MDL90 0.35µm 3.3V CMOS Standard Cell Library Pure Logic/MDL Products Data Book 2000 Samsung Electronics Co., Ltd. rights reserved. part this document reproduced, form means, without prior written consent publisher. Samsung assumes responsibility errors resulting from information contained herein, does convey license under patent rights Samsung others. Samsung reserves right make changes products product specification improve function design time, without notice. STD90/MDL90 trademarks Samsung Electronics Co., Ltd. Verilog registered trademark Cadence Design Systems, Inc. Viewlogic registered trademark Viewlogic Systems, Inc. Mentor registered trademark Mentor Graphics Synopsys registered trademark Synopsys, Inc.
Head Office Samsung Electronics Co., System Business, ASIC Division, Design Technology #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-2-760-6500, 6501(Hot Line) 82-331-209-4920 http://www.intl.samsungsemi.com Printed Republic Korea
Marketing Team Samsung Electronics Co., System Business, ASIC Division, ASIC Marketing Team #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea 82-22-331-209-1930 82-2-331-209-1919
Introduction
This databook contains information about STD90/MDL90 0.35µm 3.3V TLM/QLM standard cell library pure logic products developed (Samsung Electronics Corporation). "library" basically contains various kinds internal cells soft-macros which used developing ASIC (Application Specific Integrated Circuit). also includes design helping designers work workstation platform, sorts design environments needed automatic chip design. There seven chapters this databook: Chapter Chapter Chapter Chapter Chapter Chapter Introduction Electrical Characteristics Internal Macrocells Input/Output Cells Compiled Macrocells
this databook each cell followed electrical characteristics, these characteristic values almost equal when corresponding cell operated real chip. purpose this databook prevent misuse misapplication STD90/MDL90 cell library providing precise information about cell list, electrical data, directions use, matters demanding special attention.
Samsung ASIC
STD90/MDL90
Contents
Introduction
Library Description .1-1 Features .1-2 Support .1-3 Product Family .1-3 1.4.1 Internal Macrocells .1-3 1.4.2 Compiled Macrocells .1-3 1.4.3 Input/Output Cells.1-4 Propagation Delays .1-6 Delay Model .1-12 Testability Design Methodology.1-15 Maximum Fanouts .1-18 Product Line-Up .1-24 1.10 Packages Capability Lead Count .1-25 1.11 Power Dissipation.1-27 1.12 VDD/VSS Rules Guidelines.1-30 1.13 Crystal Oscillator Considerations .1-35
Electrical Characteristics
Electrical Characteristics.2-1 Input Buffer Curves .2-5 Output Drive Capabilities.2-7
Internal Macrocells
Overview .3-1 Summary Tables .3-2 Logic Cells AD2DH/AD2/AD2D2/AD2D4 .3-15 AD3DH/AD3/AD3D2/AD3D4 .3-17 AD4DH/AD4/AD4D2/AD4D4 .3-19 AD5/AD5D2/AD5D4 .3-22 ND2DH/ND2/ND2D2/ND2D4 .3-25 ND3DH/ND3/ND3D2/ND3D4 .3-27 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .3-30
Samsung ASIC
STD90/MDL90
Contents ND5/ND5D2/ND5D4.3-33 ND6/ND6D2/ND6D4.3-36 ND8/ND8D2/ND8D4.3-40 NR2DH/NR2/NR2D2/NR2D2B/NR2D4 .3-44 NR3DH/NR3/NR3D2/NR3D2B/NR3D4 .3-46 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 .3-49 NR5/NR5D2/NR5D4.3-52 NR6/NR6D2/NR6D4.3-56 NR8/NR8D2/NR8D4.3-60 OR2DH/OR2/OR2D2/OR2D4 .3-64 OR3DH/OR3/OR3D3/OR3D4 .3-66 OR4DH/OR4/OR4D2/OR4D4 .3-69 OR5/OR5D2/OR5D4 .3-72 XN2/XN2D2/XN2D4 .3-76 XN3/XN3D2/XN3D4 .3-78 XO2/XO2D2/XO2D4 .3-80 XO3/XO3D2/XO3D4 .3-82 AO21/AO21D2/AO21D2B/AO21D4.3-84 AO2111/AO2111D2.3-90 AO22/AO22D2/AO22D2B/AO22D4.3-93 AO22A/AO22D2A/AO22D4A.3-96 AO221/AO221D2/AO221D4.3-98 AO222A/AO222D2A/AO222D4A.3-107 AO2222/AO2222D2/AO2222D4.3-109 AO31/AO31D2/AO31D4.3-113 AO311/AO311D2/AO311D4.3-115 AO3111/AO3111D2.3-119 AO32/AO32D2/AO32D4.3-122 AO321/AO321D2/AO321D4.3-126 AO322/AO322D2/AO322D4.3-130 AO33/AO33D2/AO33D4.3-134 AO331/AO331D2/AO331D4.3-138 AO332/AO332D2/AO332D4.3-142 AO4111/AO4111D2.3-146 OA2111/OA2111D2 .3-155 OA22A/OA22D2A/OA22D4A.3-161 OA221/OA221D2/OA221D4.3-163
Samsung ASIC
STD90/MDL90
Contents OA2222/OA2222D2/OA2222D4.3-172 OA31/OA31D2/OA31D4.3-176 OA311/OA311D2/OA311D4.3-178 OA3111/OA3111D2 .3-182 OA32/OA32D2/OA32D4.3-185 OA321/OA321D2/OA321D.3-189 OA322/OA322D2/OA322D4.3-193 OA33/OA33D2/OA33D4.3-197 OA331/OA331D2/OA331D4.3-201 OA332/OA332D2/OA332D4.3-205 OA4111/OA4111D2 .3-209 SCG1 .3-212 SCG2 .3-214 SCG3 .3-215 SCG4 .3-216 SCG5 .3-218 SCG6 .3-219 SCG7 .3-220 SCG8 .3-221 SCG9 .3-222 SCG10 .3-223 SCG11 .3-224 SCG12 .3-225 SCG13 .3-226 SCG14 .3-227 SCG15 .3-228 SCG16 .3-229 SCG17 .3-230 SCG18 .3-231 SCG19 .3-232 SCG20 .3-233 SCG21 .3-234 SCG22 .3-235 DL1D2/DL1D4 .3-236 DL2D2/DL2D4 .3-237 DL3D2/DL3D4 .3-238 DL4D2/DL4D4 .3-239 DL5D2/DL5D4 .3-240 DL10D2/DL10D4 .3-241 .3-242 IVT/IVTD2/IVTD4/IVTD8/IVTD16 .3-247 .3-249
STD90/MDL90
Samsung ASIC
Contents .3-251 NIT/NITD2/NITD4/NITD8/NITD16 .3-254 .3-257 Flip-Flops FD1/FD1D2 .3-263 FD1CS/FD1CSD2 .3-265 FD1S/FD1SD2 .3-268 FD1SQ/FD1SQD2.3-270 FD1Q/FD1QD2.3-272 FD2/FD2D2 .3-274 FD2CS/FD2CSD2 .3-276 FD2S/FD2SD2 .3-280 FD2SQ/FD2SQD2.3-283 FD2Q/FD2QD2.3-286 FD3/FD3D2 .3-288 FD3CS/FD3CSD2 .3-290 FD3S/FD3SD2 .3-293 FD3SQ/FD3SQD2.3-296 FD3Q/FD3QD2.3-299 FD4/FD4D2 .3-301 FD4CS/FD4CSD2 .3-305 FD4S/FD4SD2 .3-309 FD4SQ/FD4SQD2.3-313 FD4Q/FD4QD2.3-316 FD5/FD5D2 .3-318 FD5S/FD5SD2 .3-320 FD6/FD6D2 .3-322 FD6S/FD6SD2 .3-324 FD7/FD7D2 .3-327 FD7S/FD7SD2 .3-329 FD8/FD8D2 .3-332 FD8S/FD8SD2 .3-336 FDS2/FDS2D2 .3-340 FDS2CS/FDS2CSD2 .3-342 FDS2S/FDS2SD2.3-345 FDS3/FDS3D2 .3-347 FDS3CS/FDS3CSD2 .3-349 FDS3S/FDS3SD2.3-352 FJ1/FJ1D2.3-355 FJ1S/FJ1SD2 .3-357 FJ2/FJ2D2.3-359 FJ2S/FJ2SD2 .3-361
Samsung ASIC
STD90/MDL90
Contents FJ4/FJ4D2.3-364 FJ4S/FJ4SD2 .3-367 FT2/FT2D2 .3-370 Latches LD1/LD1D2 .3-373 LD1A/LD1D2A.3-375 LD1Q/LD1QD2 .3-377 LD2/LD2D2 .3-379 LD2Q/LD2QD2 .3-382 LD3/LD3D2 .3-384 LD4/LD4D2 .3-387 LD5/LD5D2 .3-390 LD5Q/LD5QD2 .3-392 LD5S/LD5SD2.3-394 LD6/LD6D2 .3-397 LD6Q/LD6QD2 .3-400 LD7/LD7D2 .3-402 LD8/LD8D2 .3-405 LS0/LS0D2 .3-408 LS1/LS1D2 .3-410 Holder BUSHOLDER .3-414 Internal Clock Drivers CK2/CK4/CK6/CK8/CK12/CK16/CK20 .3-416 Decoders .3-419 DC4I .3-421 DC8I .3-423 Adders FADH/FA/FAD2.3-427 HADH/HA/HAD2 .3-431 SCG23 .3-434 Multiplexers MX2DH/MX2/MX2D2/MX2D4 .3-436 MX2X4 .3-439 MX2IDH/MX2I/MX2ID2/MX2ID4 .3-441 MX2IX4 .3-447 MX3I/MX3ID2/MX3ID4 .3-449
STD90/MDL90
viii
Samsung ASIC
Contents MX4/MX4D2/MX4D4 .3-453 MX8/MX8D2/MX8D4 .3-457
Input/Output Cells
Overview .4-1 Summary Tables .4-2 Input Buffers PvIC/PvICD/PvICU.4-8 PvIS/PvISD/PvISU .4-11 Output Buffers PvOByz .4-15 PvODyz .4-21 PvOTyz .4-30 Bi-Directional Buffers PvBaDyz/PvBaUDyz .4-44 PvBaTyz/PvBaDTyz/PvBaUTyz .4-44 Input Clock Drivers PSCKDCaby.4-46 PSCKDSaby.4-51 Oscillators PSOSCK(1/2) .4-57 PSOSCK(17/27) .4-60 PSOSCM(1/2/3) .4-63 PSOSCM(16/26/36) .4-67 Buffers PIPCI .4-73 POPCI .4-74 PBPCI .4-75 PTIPCI.4-76 PTOPCI .4-77 PTBPCI .4-78 Buffers PBUSB/PBUSB1 .4-81 Power Pads VDD3(I/P/O/IP/OP/T) .4-88 VSS(I/P/O/IP/OP/T).4-88
Samsung ASIC
STD90/MDL90
Contents Analog Interface VDDA/VDDD .4-89 VSSD/VSSA/VBBA .4-89 .4-89 .4-89
Compiled Macrocells
Overview Compiled Macrocells .5-1 Characteristics Timing Power.5-2 Built-In Self Test Compiled Memory .5-3 Selection Guide Compiled Memory.5-4 SPSRAM_HD .5-5 SPSRAMBW_HD .5-15 DPSRAM_HD.5-25 SPARAM_HD .5-35 DROM_HD .5-45 MROM_HD.5-53 Compiled Datapath Macrocells .5-59 Datapath Module Design Flow .5-59 Selection Guide Compiled Datapath Macrocells.5-60 ADDER.5-61 .5-66 .5-70 CSADDER.5-75 BMPY .5-79 REGF .5-86
AL2007LX .6-1 AL2007LA .6-9
STD90/MDL90
Samsung ASIC
Introduction
Table Contents
Library Description. Features. Support. Product Family 1.4.1 Internal Macrocells. 1.4.2 Compiled Macrocells. 1.4.3 Input/output Cells Propagation Delays Delay Model. 1-12 Testability Design Methodology 1-15 Maximum Fanouts 1-18 Product Line-up 1-24 1.10 Packages Capability Lead Count 1-25 1.11 Power Dissipation 1-27 1.12 VDD/VSS Rules Guidelines 1-30 1.13 Crystal Oscillator Considerations 1-35
Introduction
Library Description
Library Description
Samsung ASIC offers STD90/MDL90 0.35µm CMOS standard cell libraries based completely blended process. Samsung's world-leading DRAM process merged with sophisticated 0.35µm cell-based logic process providing layers interconnect metal with various pad-pitch options. STD90/MDL90 support three million gate count logic providing usable gates with four layer metal. STD90/MDL90 faster than 0.5µm second generation library STD85. Logic density times greater than that STD85. fully configurable memory compiler available datapath elements with width supported. support mixed voltage environments, 3.3V 5V-tolerant cells available. LVTTL, LVCMOS, Schmitt trigger, buffers supported. better support system-on-a-chip design style, various core cells available including processor cores like ARM7TDMI, 80C51 Oak. list analog core cells includes ADC, DAC, CODEC PLL. STD90/MDL90 design supports Synopsys Design Compiler, VSS, Verilog-XL, Powerview, Mentor, Motive, Sunrise IKOS. Samsung design methodology offers comprehensive timing solution including static timing analysis, floorplanning, extraction delay calculation with very deepsubmicron solutions from leading vendors. latest status details, please refer design release notes.
Samsung ASIC
STD90/MDL90
Features
Introduction
Features
3.3V standard cell library including process cores, analog cores DRAMs. 0.35µm quad layer metal HCMOS technology Unified process DRAM, logic analog High basic cell usages million gates Maximum usage: quad layer metal High speed Typical 2-input NAND gate delay(ND2D4): 91ps (F/O=2 WL(0.03pF) Fully configurable Static RAMs ROMs 512K-bit Diffusion/Metal-2 available 128K-bit Single-Port Static available 64K-bit Dual-Port Static Configurable datapath elements available 4-64 width adder, ALU, barrel shifter, carry-select adder, multiplier, multi-port register file Operating Temperature (TA) Commercial range: +70°C Industrial range: -40°C +85°C Selectable output current drive capability 1/2/4/8/12/16/20/24mA available 3.3V 1/2/4/6mA available 5V-tolerant output buffers
3.3V 5V-tolerant interface including LVTTL, LVCMOS, PCI, buffer. Processor core integration capability including ARM7TDMI, 80C51, others Analog core integration capability including ADC, DAC, CODEC, others Various package options Fully integrated software support Logic synthesis: Synopsys Design Compiler Logic simulation: Cadence Verilog-XL, Cadence NC-Verilog, Viewlogic ViewSim, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VSS, Synopsys Scan insertion ATPG: Synopsys TestGen, Synopsys Test Compiler, Mentor Fastscan Static timing analysis: Synopsys PrimeTime, Synopsys MOTIVE analysis: Avant! Star-RC Power analysis: Synopsys DesignPower, CubicPower (ln-House Tool) Formal verification: Synopsys Formality, Chrysalis Design VERIFYer, Verplex Tuxedo-LEC Fault simulation: Cadence Verifault, SuperTest (In-House Tool) Delay calculator: CubicDelay (In-House Tool) Cell optimized synthesis
STD90/MDL90
Samsung ASIC
Introduction
Support
Support
STD90/MDL90 supports rich collection industry-standard tools from Cadence, Synopsys, Mentor graphics, Avant! multiple design platforms such Solaris Customers allowed choose among industryleading tools from design capture, synthesis, simulation, layout. Several powerful proprietary software tools seamlessly integrated design kits improve your product quality. high simulation accuracy, STD90/MDL90 uses proprietary delay calculator. Cell delay calculated based matrix delay parameters each macrocell, signal interconnect delay calculated based tree analysis.
Product Family
STD90/MDL90 library include following design elements: Internal Macrocells Compiled Macrocells Input/Output Cells JTAG Boundary Scans.
1.4.1 INTERNAL MACROCELLS Macrocells lowest level logic functions such NAND, flipflop used logic designs. There about different types internal macrocells. They usually come three levels drive strength (1X, 4X). These macrocells have many levels representations-logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, physical layout, placement routing model. 1.4.2 COMPILED MACROCELLS Compiled macrocells STD90/MDL90 consist compiled memory compiled datapath macrocells. Compiled memory macrocells include types single-port RAMs (synchronous asynchronous), dual-port (synchronous) types ROMs (synchronous diffusion metal-2 programmable). Synchronous memories have fully synchronous operation clock. Asynchronous memories have synchronous operation Write Enable write mode have asynchronous operation address read mode. Those compiled memories have automatic power-down mode that significantly reduces power consumption read write operations. This power-down mode ensures that memory consumes power minimum amount time needed read write operation. memories, flexible memory aspect ratio provided. case single-port synchronous SRAM, bit-write capability available. Now, softmacro based memory BIST (Built-In Self Test) capability available. Several memory macrocells same type different type circuit tested single BIST circuit. Compiled datapath macrocells include adder, ALU, barrel shifter, carry select adder, multiplier multi-port register file. Adder supports both addition subtraction adopts group-bypass carry propagation scheme improve performance. supports arithmetic operations logical operations. Carry select adder much faster than adder adopts double-carry propagation scheme improve performance. Multiplier supports pipe-lined
Samsung ASIC
STD90/MDL90
Product Family
Introduction
scheme improve performance also accumulation scheme. Multi-port register file allows 1-to-2 write 1-to-4 read ports each port fully independent. write mode, this register file operates synchronously clock. read mode, operates asynchronously address. provide kinds engineering design services. support additional compiled datapath macrocells such Comparators, Detectors, Incrementers Decrementers, Multiplexers, other support hardwired datapath module design. 1.4.3 INPUT/OUTPUT CELLS There about four hundred different buffers. Each cell implemented solely basic cell architecture which forms periphery chip. test logic provided enable efficient parametric (threshold voltage) testing input buffers including LVCMOS, CMOS level converters, Schmitt trigger input buffers, clock drivers oscillator buffers. Pull-up pulldown resistors optional features. Three basic types output buffers (non-inverting, tri-state open drain) available range driving capabilities from 24mA 3.3V drive 5V-tolerant drive. levels slew rate controls provided each buffer type (except buffers) reduce output power/ground noise signal ringing, especially simultaneous switching outputs. Bi-directional buffers combinations input buffers output buffers (tristate open drain) single unit. structure been fully characterized protection latch-up resistance. user's convenience, STD90/MDL90 library provides 100K pull-down pull-up resistances respectively. 1.4.3.1 Cell Drives Options provide designers with greater flexibility, each buffer selected among various current levels (e.g., 1mA, 2mA,., 24mA). choice currentlevel buffers affects their propagation delay current noise. slew rate control helps decrease system noise output signal overshoot/undershoot caused switching output buffers. output edge rate slowed down selecting high slew rate control cells. STD90/MDL90 provides three different sets output slew rate controls. Only slot required slew rate control options. 1.4.3.2 Tolerant Buffers STD90/MDL90 library process which most optimum performance 3.3V. this process, voltages more than 3.6V allowed gate oxide because reliability problem. special circuit adopted order make voltage tolerable 5.25V offer interface driving 6mA. Obviously, this circuit constructed permit more than 3.6V gate oxide. external circuit diagram follows. maximum external tolerance voltage this buffer 5.5V. leakage current tri-state input output less than 100nA used 3.3V normal buffer.
STD90/MDL90
Samsung ASIC
Introduction
Product Family
3.3V Output voltage 3.3V Open drain output tolerant input Tri-state output Bi-directional 0.35µm 3.3V process
3.3V
5.0V
Input Input Normal process
1.4.3.3 Buffers addition input, output, bi-directional, slew rate controlled Schmitt trigger buffers, Samsung ASIC offers (Peripheral Component Interconnect) compliant buffers. 3.3V 33MHz 5V-tolerant 33MHz buffers included library. 1.4.3.4 (Universal Serial Bus) Buffers Various kinds peripheral equipments such mouse, stick, keyboard, modem, scanner printer improve power computer. However, easy connect them properly computer. specification established late 1995 good solution this problem, providing facile method expansion. Samsung ASIC offers full speed speed buffers.
Samsung ASIC
STD90/MDL90
Propagation Delays
Introduction
Propagation Delays
Interconnection wire length, temperature supply voltage chief factors affecting propagation delays. 1.5.1 WIRE LENGTH LOAD Table 1-1. shows equivalent standard load matrix 3-layer 4-layer metal interconnect. equivalent standard load values function gatecount fanout. These values based capacitive loading used wire length estimates which affect propagation delay.
Table 1-1.
Gates Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000
Equivalent Standard loads 3-layer 4-layer Metal Interconnect
Fanouts
0.633 0.837 2.292 2.514 12.647 13.313 14.644 15.976 17.823 19.080 21.984 24.696 32.133 39.100
1.227 1.605 4.511 5.103 16.863 17.751 19.526 21.301 23.764 25.440 29.312 32.928 42.843 52.133
2.091 3.042 6.804 7.618 21.079 22.189 24.408 26.442 29.706 31.980 37.162 42.005 55.191 67.548
2.797 4.213 9.023 10.133 22.337 23.520 26.183 28.254 31.686 34.065 39.500 44.580 58.434 71.417
3.434 5.162 11.316 12.721 24.463 25.758 28.605 30.935 34.656 37.227 43.113 48.612 63.625 77.695
4.043 6.047 13.535 15.236 25.184 26.516 29.400 31.841 35.647 38.269 44.281 49.900 65.247 79.629
5.526 6.974 15.828 17.751 26.951 28.374 31.426 34.070 38.122 40.910 47.309 53.288 69.629 84.941
7.415 10.304 18.121 20.340 30.815 32.442 35.900 38.849 43.568 46.838 54.314 61.298 80.347 98.198
29.289 30.547 36.316 40.754 56.028 58.894 65.088 70.358 74.889 77.036 83.250 89.022 106.405 122.664
58.284 60.946 72.633 81.508 89.571 94.156 103.920 112.130 119.378 122.828 132.784 142.031 169.855 195.883
116.494 121.893 145.266 163.017 179.142 188.239 207.618 223.964 238.387 245.226 265.011 283.387 338.729 390.495
0.570 0.753 2.063 2.263 11.383 11.982 13.180 14.378 16.041 17.172 19.786 22.227 28.920 35.190 41.058 46.543
1.104 1.444 4.060 4.593 15.177 15.976 17.573 19.171 21.388 22.896 26.381 29.636 38.559 46.920 54.744 62.058
1.882 2.738 6.124 6.856 18.971 19.970 21.967 23.798 26.735 28.782 33.446 37.804 49.672 60.793 71.204 80.934
2.517 3.792 8.121 9.119 20.103 21.168 23.565 25.428 28.517 30.658 35.551 40.122 52.591 64.275 75.211 85.433
3.091 4.646 10.184 11.449 22.017 23.182 25.744 27.842 31.191 33.504 38.801 43.751 57.263 69.926 81.776 92.853
3.639 5.442 12.181 13.713 22.666 23.864 26.460 28.657 32.082 34.442 39.853 44.909 58.723 71.666 83.781 95.104
4.073 6.277 14.245 15.976 24.255 25.536 28.283 30.663 34.310 36.819 42.579 47.959 62.666 76.447 89.345 101.400
6.673 9.274 16.309 18.306 27.734 29.198 32.310 34.965 39.211 42.154 48.883 55.167 72.312 88.378 103.415 117.470
26.360 27.492 32.684 36.678 50.425 53.005 58.579 63.323 67.400 69.333 74.926 80.120 95.764 110.398 124.067 136.818
52.455 54.852 65.369 73.357 80.613 84.741 93.528 100.917 107.440 110.545 119.505 127.827 152.870 176.295 198.176 218.585
104.844 109.704 130.739 146.715 161.227 169.415 186.856 201.568 214.548 220.703 238.509 255.048 304.856 351.446 394.965 435.558
STD90/MDL90
Samsung ASIC
Introduction
Propagation Delays
1.5.2
TEMPERATURE SUPPLY VOLTAGE
next figure describes propagation delay derating factors (KT, function on-chip junction temperature (TJ) supply voltage (VDD). result power dissipation, junction temperature generally higher than ambient temperature. temperature inside package (junction temperature, calculated using chip power dissipation thermal resistance ambient temperature (JA) package. Information package thermal performance obtained from Samsung application engineers. Figure 1-1. Effect Temperature Supply Voltage Propagation Delay
Temperature (TJ)
1.158 1.098 1.074
1.000 0.957 0.889
(°C)
Supply Voltage (VDD)
1.183
1.076
1.000
0.944 (Volt)
Samsung ASIC
STD90/MDL90
Propagation Delays
Introduction
1.5.3 BEST WORST CASE CONDITIONS circuit should designed operate properly within given specification level, either commercial industrial. recommended that circuits simulated best case, normal case, worst case conditions each specification level. following expressions also allow effect process variation circuit performance. Best case (Worst case): (TWC) TNOM Worst case: KPWC TNOM where Best case propagation delay Worst case propagation delay TNOM Normal propagation delay 3.3V typical process) Refer toTable 1-2., Table 1-3., Table 1-4. 1.5.4 DERATING FACTORS STD90/MDL90 multipliers applied nominal delay data order estimate effects supply voltage, temperature process. Nominal data provided conditions 3.3V, 25°C typical process. derating factors STD90/MDL90 follows. Table 1-2. STD90/MDL90 Process Derating Factor (KP) Slow Table 1-3. Temp. Table 1-4. Voltage (oC) Fast
Process Factor (KP)
STD90/MDL90 Temperature Derating Factor (KT) 1.158 1.098 1.074 1.000 0.957 0.889
STD90/MDL90 Voltage Derating Factor (KV) 0.944 1.000 1.076 1.183
STD90/MDL90
Samsung ASIC
Introduction
Propagation Delays
1.5.5 TIMING PARAMETERS This section discusses issues involving timing parameters primitive cells. 1.5.5.1 Rise Fall Times definition rise time (tR) fall time (tF) shown following figure. Figure 1-2. Rise Fall Times
1.5.5.2 Setup Hold Times Setup time (tSU) minimum period which input data flip-flop latch must stable before active edge clock occurs. Hold time (tHD) minimum period which input data flip-flop latch must remain stable after active edge clock occurred. next figure shows relationship between setup hold times standard flip-flop triggered rising edge clock. Figure 1-3. Setup Hold Times
1.5.5.3 Minimum Pulse Widths Minimum clock pulse widths (tPWH, tPWL) time intervals during clock signal high low, that ensures proper operation flip-flop latch.
Samsung ASIC
STD90/MDL90
Propagation Delays
Introduction
Figure 1-4.
Minimum Pulse Width
tPWH
1.5.5.4 Recovery Times Recovery time (tRC) minimum time after asynchronous disabled that active clock edge will propagate data from input output. active edge clock occurs before specified recovery time, input data will propagate. Figure 1-5. Recovery Time
1.5.5.5
Removal Times
Removal time (tRM) minimum time which asynchronous reset latch must remain enabled after active edge clock occurred. reset disabled before specified removal time, input data propagate incorrectly. Figure 1-6. Removal Time
STD90/MDL90
1-10
Samsung ASIC
Introduction
Propagation Delays
1.5.5.6 Propagation Delays delay macrocell considered rising delay (tPLH) signal output rising. rising input rising output, rising delay interval between times input becomes supply voltage (VDD) output becomes VDD. input falling output rising, rising delay interval between times input falls output rises VDD. converse true falling delay (tPHL). Figure 1-7. Propagation Delay
tPLH
tPHL
tPLH
tPHL
1.5.6 PROPER BUFFERS Figure 1-8. shows average propagation delays internal inverter (IV), inverter (IVD8), normal clock driver (CK2), high clock driver (CK12) STD90/MDL90. Note that transistors used buffers over larger have lower channel resistance than those channel transistors primitive cells. used clock driver core limited design clock driver over used high fanout signals.
Samsung ASIC
1-11
STD90/MDL90
Delay Model
Introduction
Figure 1-8.
Average Gate Delay STD90/MDL90 Average Delay [ns]
IVD8 CK12
Fanout [number]
caution, emphasized Figure 1-9. shows that route buffer that uses slot from internal element back into internal logic, additional wiring needed could increase propagation delays materially. Higher drive strength internal cells more appropriate than slot buffers. Realize also that using slot cells internal buffering removes those locations external I/Os uses wiring channels, thereby increasing routability congestion master slice products. Figure 1-9. Slot Internal Buffer
High Fanout Clock Driver Using Slot
Long Wire
Delay Model
ASIC timing characteristics consist following components: Cell propagation delay from input output transitions based input waveform slope, fanout loads distributed interconnection wire resistance capacitance. Interconnection wire delay across metal lines. Timing requirement parameters such setup time, hold time, recovery time, skew time, minimum pulse width, etc. Derating factors junction temperature, power supply voltage, process variations.
STD90/MDL90
1-12
Samsung ASIC
Introduction
Delay Model
Timing model STD90/MDL90 focuses characterize cell propagation delay time accurately. accomplish this goal, 2-dimensional table look-up delay model been adopted. index variables this table input waveform slope output load capacitance. figure below. Samsung ASIC design automation system supports n-dimensional table model even though adopted 2-dimensional model 0.35µm cell-based products. Figure 1-10. 2-Dimensional Table Delay Model
Propagation Delay [ns] Input Waveform Slope [ns] Load [pF]
Table 1-5. shows example this model 2-input NAND cell. data this table high-to-low transition delay times from input pins output pin. number points values index variables differ each cell. Table 1-5.
SLOPE
Table Delay Model Example 0.011 0.06060 0.08601 0.11397 0.09984 0.043 0.12196 0.15686 0.24258 0.26318 0.504 0.78281 0.81447 1.03300 1.21660 0.964 1.44330 1.47460 1.67820 1.90920
0.024 0.255 1.627 3.000
Notice that 4-by-4 table used. Delay values between grid points beyond this table determined linear interpolation extrapolation methods. This general table delay model provides great flexibility well high accuracy since extensive software revisions required when cell library updated. other timing components such interconnection wire delay, timing requirement parameters derating factors characterized commonly-accepted industry. delay time interconnection wire separated into components. signal propagation delay time across metal lines. This delay time component computed through conventional analysis based -model. other additional delay driving cell wire load. traditional compute this based lumped capacitance model, ignoring wire resistance.
Samsung ASIC
1-13
STD90/MDL90
Delay Model
Introduction
sub-micron technology, this approximation cannot accepted more. wire resistance shielding effect driving cell from load capacitances. effective capacitance CEFF, single capacitance approximating distributed interconnection wire resistance capacitance, derived, illustrated following figure. compensation factor extracted each cell, function length interconnection wires layout topology. these effects merged determine effective capacitance this value used index table delay model. Figure 1-11. Concept Effective Capacitance
CEFF Cload)
figure below summarizes features Samsung ASIC's delay model. 2-dimensional table delay model output loading input waveform slope effects used.The slopes (tR, delay times (tPLH, tPHL) cell instances calculated recursively. input waveform slope each primary input loading capacitance each primary output assigned individually default. delays cells interconnection wires supported. effect distributed interconnection wire resistance capacitance cell delay analysed using effective capacitance concept.
Figure 1-12. Features Delay Model
STD90/MDL90
1-14
Samsung ASIC
Introduction
Testability Design Methodology
Testability Design Methodology
1.7.1 SCAN DESIGN Multiplexed scan flip-flop that minimizes area delay overhead needed implement scan design. Automated design rules checking, scan insertion, test pattern generation High fault coverage synchronous designs
1.7.2 BOUNDARY-SCAN IEEE 1149.1 JTAG boundary-scan registers with primitive cells Boundary-Scan Description Language (BSDL) description board testing Combination with internal scan design core testing
Boundary Scan Architecture boundary scan architecture contains (Test Access Port), controller, instruction register group test data registers. instruction test data registers separate shift-register-based paths connected parallel with common serial data input common serial data output which connected TAP, signals. controller selects alternative instruction test data register paths between TDO. schematic view level design test logic architecture shown Figure 113. Figure 1-13. JTAG Test Access Port (TAP) Block Diagram
Scannable Register Device Identity Register Instruction Register Controller Bypass Register TEST ACCESS PORT (TAP)
SYSTEM LOGIC
Multiplexer
Boundary Scan Path
Samsung ASIC
1-15
STD90/MDL90
Testability Design Methodology
Introduction
Boundary Scan Functional Block Descriptions (Test Access Port) general-purpose port that provide with access many test support functions built into component, including test logic. includes three inputs (TCK; Test Clock Signal, TMS; Test Mode Signal TDI; Test Data Input) output (TDO; Test Data Output) required test logic. optional fourth input (TRSTN; Test Reset) provided asynchronous initialization test logic. values applied pins sampled rising edge TCK, value placed changes falling edge TCK. Controller controller receives TCK, interprets signals TMS, generates clock control signals both instruction test data registers other parts test circuitries required. Instruction Register/Instruction Decoder Test instructions shifted into held instruction register. Test instructions include selection tests performed test data register accessed. basic 3-bit instruction register instruction decoder provided macrofunctions library. Test Data Registers Data registers include bypass register, boundary scan register, device identification register other design specific registers. Only bypass- boundary scan registers mandatory; rest optional. Bypass register: bypass register provides single-bit serial connection through circuit when none other test data registers selected. used allow test data flow through given device other components product without affecting normal operation. Boundary scan register: boundary scan register detects typical production defects board interconnects, such opens, shorts, etc. also allows access component inputs outputs when test their logic sample flow-through signals. Special boundary scan register macrocells provided this purpose. These special registers discussed next section next pages. Design-specific test data register: These optional registers provided allow access design-specific test support features integrated circuit, such self-test, scan test. Device identification register: This optional test data register that allows manufacturer part number variant components identified. 32-bit identification register partitioned into four fields: Device version identifier1st field Device part number Manufacturer's JEDEC number first four bits beginning from field bits field bits field -tied High
STD90/MDL90
1-16
Samsung ASIC
Introduction
Testability Design Methodology
ASIC designer free fill version part number manner long total twenty bits used. Samsung's JEDEC code: decimal 1001110 Continuation field bits) 0000 Contents device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 Users define these fields.
Boundary Scan Register (connection boundary scan cells)
Boundary Scan Path
Instruction Register
Test Access Port (TAP)
Test Data Register
Controller
Circuit Prior Boundary Scan (Core Logic)
Bypass Register
1.7.3 BIST (BUILT-IN SELF-TEST) Efficient test solution compiled memory macrocells speed parallel testing multiple memories Less routing overhead test requirements
Samsung ASIC
1-17
STD90/MDL90
Maximum Fanouts
Introduction
Maximum Fanouts
1.8.1 INTERNAL MACROCELLS maximum fanouts STD90/ MDL90 primitive cells follows. Note that these fanout limitation values calculated when rise fall times input signal 0.255ns. Depending rise fall times, maximum fanout limitations varied case case. following table maximum fanout values pins STD90/ MDL90 internal macrocells listed. Table 1-6. Maximum Fanouts Internal Macrocells (tR/tF 0.255ns, fanout (SL) 0.01352pF)
Cell Name Maximum Fanout
Cell Name NR4DH NR4D2 NR4D2B NR4D4 NR5D2 NR5D4 NR6D2 NR6D4 NR8D2 NR8D4 OR2DH OR2D2 OR2D4 OR3DH OR3D2 OR3D4 OR4DH OR4D2 OR4D4 OR5D2 OR5D4 XN2D2 XN2D4 XN3D2 XN3D4 XO2D2 XO2D4 XO3D2 XO3D4 AO21 AO21D2 AO21D2B AO21D4 AO211 AO211D2 AO211D2B AO211D4 AO2111 AO2111D2 AO22 AO22D2 AO22D2B AO22D4 AO22A AO22D2A AO22D4A AO221 AO221D2 AO221D4 AO222 AO222D2 AO222D2B AO222D4 AO222A AO222D2A AO222D4A AO2222 AO2222D2 AO2222D4 AO31 AO31D2
Logic Cells
AD2D2 AD2D4 AD3DH AD3D2 AD3D4 AD4DH AD4D2 AD4D4 AD5D2 AD5D4 ND2DH ND2D2 ND2D4 ND3DH ND3D2 ND3D4 ND4DH ND4D2 ND4D2B ND4D4 ND5D2 ND5D4 ND6D2 ND6D4 ND8D2 ND8D4 NR2DH NR2D2 NR2D2B NR2D4 NR3DH NR3D2 NR3D2B NR3D4
Maximum Fanout
STD90/MDL90
1-18
Samsung ASIC
Introduction
Maximum Fanouts
Cell Name AO31D4 AO311 AO311D2 AO311D4 AO3111 AO3111D2 AO32 AO32D2 AO32D4 AO321 AO321D2 AO321D4 AO322 AO322D2 AO322D4 AO33 AO33D2 AO33D4 AO331 AO331D2 AO331D4 AO332 AO332D2 AO332D4 AO4111 AO4111D2 OA21 OA21D2 OA21D2B OA21D4 OA211 OA211D2 OA211D2B OA211D4 OA2111 OA2111D2 OA22 OA22D2 OA22D2B OA22D4 OA22A OA22D2A OA22D4A OA221 OA221D2 OA221D4 OA222 OA222D2 OA222D2B OA222D4 OA2222 OA2222D2 OA2222D4 OA31 OA31D2 OA31D4 OA311 OA311D2 OA311D4 OA3111 OA3111D2 OA32 OA32D2 OA32D4 OA321 OA321D2 OA321D4 OA322 OA322D2 OA322D4 OA33 OA33D2 OA33D4
Maximum Fanout
Cell Name OA331 OA331D2 OA331D4 OA332 OA332D2 OA332D4 OA4111 OA4111D2 SCG1 SCG2 SCG3 SCG4 SCG5 SCG6 SCG7 SCG8 SCG9 SCG10 SCG11 SCG12 SCG13 SCG14 SCG15 SCG16 SCG17 SCG18 SCG19 SCG20 SCG21 SCG22 SCG23 DL1D2 DL1D4 DL2D2 DL2D4 DL3D2 DL3D4 DL4D2 DL4D4 DL5D2 DL5D4 DL10D2 DL10D4 IVDH IVD2 IVD3 IVD4 IVD6 IVD8 IVD16 IVCD11 IVCD13 IVCD22 IVCD26 IVCD44 IVTD2 IVTD4 IVTD8 IVTD16 IVTN IVTND2 IVTND4 IVTND8 IVTND16 NIDH
Maximum Fanout 1221 1093 1094
Samsung ASIC
1-19
STD90/MDL90
Maximum Fanouts
Introduction
Cell Name NID2 NID3 NID4 NID6 NID8 NID16 NITD2 NITD4 NITD8 NITD16 NITN NITND2 NITND4 NITND8 NITND16
Maximum Fanout 1218 1092 1092
Cell Name FD4CSD2 FD4S FD4SD2 FD4SQ FD4SQD2 FD4Q FD4QD2 FD5D2 FD5S FD5SD2 FD6D2 FD6S FD6SD2 FD7D2 FD7S FD7SD2 FD8D2 FD8S FD8SD2 FDS2 FDS2D2 FDS2CS FDS2CSD2 FDS2S FDS2SD2 FDS3 FDS3D2 FDS3CS FDS3CSD2 FDS3S FDS3SD2 FJ1D2 FJ1S
Flip-Flops
FD1D2 FD1CS FD1CSD2 FD1S FD1SD2 FD1SQ FD1SQD2 FD1Q FD1QD2 FD2D2 FD2CS FD2CSD2 FD2S FD2SD2 FD2SQ FD2SQD2 FD2Q FD2QD2 FD3D2 FD3CS FD3CSD2 FD3S FD3SD2 FD3SQ FD3SQD2 FD3Q FD3QD2 FD4D2 FD4CS
Maximum Fanout
STD90/MDL90
1-20
Samsung ASIC
Introduction
Maximum Fanouts
Cell Name FJ1SD2 FJ2D2 FJ2S FJ2SD2 FJ4D2 FJ4S FJ4SD2 FT2D2
Maximum Fanout
Cell Name LS1D2
Maximum Fanout 10000
Busholder Holder
busholder
Decoders
DC4I
DC8I
Latches
LD1D2 LD1A LD1D2A LD1Q LD1QD2 LD2D2 LD2Q LD2QD2 LD3D2 LD4D2 LD5D2 LD5S LD5SD2 LD5Q LD5QD2 LD6D2 LD6Q LD6QD2 LD7D2 LD8D2 LS0D2
Adders
FADH FAD2 HADH HAD2
Multiplexers
MX2DH MX2D2 MX2D4
MX2X4 MX2IDH MX2I MX2ID2 MX2ID4 MX2IDHA MX2IA MX2ID2A MX2ID4A
MX2IX4 MX3I MX3ID2 MX3ID4 MX4D2 MX4D4 MX8D2 MX8D4
Samsung ASIC
1-21
STD90/MDL90
Maximum Fanouts
Introduction
1.8.2 Cells maximum fanouts cells follows. Table 1-7. Maximum Fanouts Cells (tR/tF 0.255ns, fanout (SL) 0.01352pF) Cell Output Maximum Name Fanouts
pic_abb picc_abb picd picu pipci pisd pisu psosck1 psosck17 psosck2 psosck27 psoscm1 psoscm16 psoscm2 psoscm26 psoscm3 psoscm36 ptic pticd pticu ptipci3 ptipci5 ptis ptisd ptisu 1575
STD90/MDL90
1-22
Samsung ASIC
Introduction
Maximum Fanouts
1.8.2 CELL FANOUT STD90/MDL90 fanout cells <Condition> 3.3V Fanout 0.00945pF input FD1) Standard Load (SL) 0.01352pF Input slope 0.255ns output transition time (mott) 3.0ns Maximum frequency 150MHz length (µm/fanout): branch length each fanout except trunk Table 1-8. Maximum Fanout Clock Cells
5000 1125 1478 2106 2643 3082 10000 1201 1596 1865 2039 5000 1041 10000 case that interconnection considered 1112 1651 2204 3287 4359 5146
Trunk width (µm) length (µm/fanout) Trunk length (µm) ck12 ck16 ck20
1.8.3 CELLS maximum fanouts cells follows. Table 1-9. Maximum Fanout Cells
5000 10000 5000 10000 case that interconnection considered 1218
Trunk width (µm) length (µm/fanout) Trunk length (µm) nid2 nid3 nid4 nid6 nid8 nid16
high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis.
Samsung ASIC
1-23
STD90/MDL90
Product Line-Up
Introduction
Product Line-Up
Table 1-9. Optimum Gates Numbers STD90/MDL90 Ref.
NOTE:
Estimated Gates 30,000 50,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 500,000 600,000 700,000 800,000 900,000 1,000,000 1,200,000 1,400,000 1,600,000 1,800,000 2,000,000 2,500,000 3,000,000
Total Pads
Chip size changed depending circuit design.
STD90/MDL90
1-24
Samsung ASIC
Introduction
1.10 Package Capability Lead Count
1.10
Package Capability Lead Count
Lead Count
Package Lead Inductance SOP/SSOP (Small Outline Package) 8.7mm 5.1mm 10.2 15.6 14.1 18.4 12.6 29.0mm 12.7 29.0 TSOP/TSSOP (Thin SOP) 3.0mm x9.7mm 14.0 10.2 18.9 10.2 21.4 10.2 22.6 12.0 20.0mm 12.4 16.4 PSOP/PSSOP (Power SOP) 7.64 12.8 11.0 15.9 20nH 16nH
Samsung ASIC
1-25
STD90/MDL90
1.10 Package Capability Lead Count
Introduction
Package Lead Inductance (Quad Flat Package) 12nH 11nH 17nH 15nH TQFP (Thin Quad Flat Package) 10nH 11nH 13nH PLCC (Plastic Leaded Chip Carrier) 16.6 16.5mm <5nH 29.3 29.3 13nH
Lead Count
Package SBGA (Super BGA) 42.5 42.5 PBGA (Plastic BGA) PBGA (Plastic BGA)
Lead Inductance Lp/g Lp/g Lp/g Lsig Lsig <9nH 13nH 18nH 21nH 13nH 14nH Lsig <10nH 13nH 18nH 21nH 13nH 14nH
Lead Count
STD90/MDL90
1-26
Samsung ASIC
Introduction
1.11
Power Dissipation
1.11 Power Dissipation
1.11.1 ESTIMATION POWER DISSIPATION CMOS CIRCUIT CMOS circuits have been traditionally considered consume power since they draw very small amount current steady state. However, recent revolution CMOS technology that allows very high gate density changed power dissipation should understood. power dissipation CMOS circuit affected various factors such number gates, switching frequency, loading output gate, Power dissipation important when designers decide amount necessary power supply current device operate safety. Propagation delays reliability device also depend power dissipation that determines temperature which operates. obtain high speed reliability, designers must estimate power dissipation device accurately determine appropriate environments including package system cooling methods. This section describes concepts types power dissipation (static dynamic) CMOS circuit, method calculating those Samsung STD90/MDL90 library, finally their relationship with temperature. 1.11.2 STATIC (DC) POWER DISSIPATION There types static current contributing total static power dissipation CMOS circuits. leakage current gates resulted reverse bias between well substrate region. There current path from power ground CMOS because transistor pair always off, therefore, static current except leakage current flows through internal gates device. amount this leakage current however, range tens nano amperes, which negligible. other current that flows through input output buffers when circuit interfaced with other devices, especially TTL. current pull-up/ pull-down transistor input buffers about 35µA typically, which also negligible. Therefore, only current that output buffers source sink counted estimate total static power dissipation. power dissipation output bi-directional buffers determined following formula:
PDC_OUTPUT [mW] VOL(k) IOL(k) tL(k) VOH(k) tH(k)
PDC_BI [mW] VOL(k) IOL(k) tL(k) VOH(k) tH(k) Sout
where, Number output bidirectional buffers Total operation time output mode logic high state time logic state time (Supposed that output bidirectional buffers have just logic high state) Sout output mode ratio bidirectional buffers (typically 0.5)
Samsung ASIC
1-27
STD90/MDL90
1.11
Power Dissipation
Introduction
1.11.3 DYNAMIC (AC) POWER DISSIPATION When CMOS gate changes state, draws switching current result charging discharging load capacitance, energy associated with switching current node capacitance, VDD2 where power supply voltage. addition power dissipated load capacitance, CMOS circuits consume power short-circuit current flowing through temporary VDD-to-ground path during switching. dynamic power dissipation entire chip much more complicated estimate since depends degree switching activity circuit. Samsung found that degree switching activity average recommends this number used estimating total dynamic power dissipation. 1.11.4 POWER DISSIPATION STD90/MDL90 This section describes equations estimate power dissipation STD90/MDL90. explained previous section, total power dissipation (PTOTAL) consists static power dissipation (PDC) dynamic power dissipation (PAC). PTOTAL Since only output buffers contribute static power dissipation, PDC_OUTPUT where PDC_OUTPUT static power dissipated when output buffers source sink. dynamic power dissipation caused three components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bidirectional buffers (PAC_BI), internal cells (PAC_INTERNAL). PAC_ INPUT PAC_OUTPUT PAC_BI PAC_INTERNAL Each term mentioned above characterized following equations:
N_input
PAC_INPUT [mW] 10.89 PAC_OUTPUT [mW] 10.89
N_bi
0.001 Ci_inload
N_output
0.001 Ci_outload
PAC_BI [mW] 10.89 Sout 10.89
(0.001 Ci_inload)
N_bi
(0.001 Ci_outload) Sout
N_macro
PAC_INTERNAL [mW] 0.001 0.8433 0.0485
0.001
STD90/MDL90
1-28
Samsung ASIC
Introduction
1.11
Power Dissipation
where N_input number input buffers used, N_output number output buffers used, N_bi number bidirectional buffers used, N_macro number macro cells used, size design gate count, operating frequency MHz, estimated degree switching activity (typically 0.1), Sout output mode ratio bidirectional buffers (typically 0.5), load capacitance characterized power i-th hard macro block (µW/MHz) 1.11.5 TEMPERATURE POWER DISSIPATION total power dissipation, PTOTAL used find device temperature following equation:
PTOTAL
where
thermal impedance,
junction temperature device, ambient temperature.
Thermal impedances Samsung packages given following table. junction temperature, obtained multiplying PTOTAL appropriate adding determines derating factor propagation delays also indicates reliability measures. Hence, designers achieve desired derating factor reliability targets choosing appropriate packages system cooling methods. Table 1-10. Number Thermal Impedances Samsung Plastic Packages SOP/TSOP 41-44 46-56 44-71 39-59 34-56 27-33 34-46
JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W]
Number
51-62
43-56
43-74
27-61
33-47
43-51
29-51
22-43
28-47
29-42
TQFP/LQFP Number 68-70 37-70 35-62 PBGA Number 19-22 16-19 SBGA Number 14.1 13.1 11.7 10.2 (TEPBGA) (TEPBGA) 31-34 37-56 30-42
Samsung ASIC
1-29
STD90/MDL90
1.12
VDD/VSS Rules Guidelines
Introduction
1.12 VDD/VSS Rules Guidelines
There three STD90, providing power with internal area. Core logic VDD3I, VSSI Pre-drive (I/O area) VDD3P, VSSP Output-drive (I/O area) VDD3O, VSSO
number pads required specific design depends following factors: Number input output buffers Number simultaneous switching outputs Number used gates simultaneous switching gates Operating frequency.
1.12.1 BASIC PLACEMENT GUIDELINES purpose these guidelines minimize drop noise reliable device operations. Core logic pre-driver VDD/VSS pads should evenly distributed sides chip. have core block demanding high power (compiled memory, analog), extra power pads should placed that side. Power pads group should evenly distributed group. place quiet signal (analog, reference) analog power (VDDA/ VSSA) bi-directional buffer next group. opposite types power pads (VDD/VSS) should placed close possible. possible, place power pads (VDD/VSS) corner chip.
1.12.2 VDD3I/VSSI ALLOCATION GUIDELINES purpose these guidelines ensure that minimum number core logic power pairs meeting ElectroMigration current limit used. number VDD3I/VSSI pads required specific design determined function operating frequency chip. VDD3I width number pads equal those VSSI VDD3I/VSSI buses pads should distributed evenly core each side chip. total number core logic VDD3I pads equal that VSSI pads.
STD90/MDL90
1-30
Samsung ASIC
Introduction
1.12
VDD/VSS Rules Guidelines
number VDD3I/VSSI pairs required design calculated from following expression: number VDD3I/VSSI pairs 0.001 0.2555 0.0147
N_macro
round
where, core (excluding hard macro blocks) size gate counts switching ratio (typically 0.1) Operating frequency (MHz) Characterized current i-th hard macro block (mA/MHz) Operating frequency i-th hard macro block (MHz) Current limit VDD/VSS pairs based ElectroMigration rule (100mA) reliable device operation minimize voltage drop, minimum number VDD3I/VSSI power pairs Extra power needed demanding high power macro blocks (SRAM, analog block.). 1.13.3 VDD3P/VSSP ALLOCATION GUIDELINES. These guidelines ensure that adequate input threshold voltage margin maintained during switching. number VDD3P/VSSP pads required design calculated from following expressions: eq_p Number_ of_VDD3P/VSSP_pad-pairs round above expression, Ieq_p (Average current input/output buffers bidirection pre-drivers maximum operational frequency.) [mA] (Refer Table 1-11)
N_input
Ieq_p
N_bi
N_output Ij_eq_p_out eq_p_in
Sout Ik_eq_p_out Sout k_eq_p_in
where N_input number input buffers used, N_output number output buffers used, N_bi number bidirectional buffers used, operating frequency MHz, Sout output mode ratio bidirectional buffers (typically 0.5), Current limit VDD/VSS pairs based ElectroMigration rule. (100mA) Table 1-11(a). Ieq_p 100MHz) Each Type Input Buffer Input Buffer Type CMOS CMOS Schmitt Ieq_p_in (mA)
Samsung ASIC
1-31
STD90/MDL90
1.12
VDD/VSS Rules Guidelines
Introduction
Table 1-11(b). Ieq_p 100MHz) Each Type Output Buffer Output Buffer Type B1-8 B12-24 B4-24 (T4-24) (T12-24) Slew-Rate Ieq_p_out (mA)
NOTE: means output driver cells, means 24mA output driver cells.
reliable device operation minimizing voltage drop, minimum number VDD3P/VSSP power pairs 1.12.4 VDD3O/VSSO ALLOCATION GUIDE (Simultaneous Switching Output) current induced power ground inductance cause system failure because voltage fluctuations. calculation output driver power numbers, consider noise well current limit based ElectroMigration. define output considered simultaneous window such type buffers. number VDD3O/VSSO pads required device calculated from following expression. case heavy load, high frequency package inductance, number power pads block could determined electromigration rule rather than limit noise. number power pads block should determined worse power number under limit noise that under limit electromigration rule. Number power pads block under limit noise Calculating number power each group from following expressions: number_of_SSO NVDDO each_SSO -NBvdd SSO_mode number_of_SSO NVSSO each_SSO -NBvss SSO_mode above formula, NVDDOeach_sso Number VDD3O required each group NVSSOeach_sso Number VSSO required each group NBvdd=Number buffers VDD3O power with lead inductance (Refer Table 1-13.) NBvss Number buffers VSSO ground with lead inductance Package lead frame inductance (Refer 1.10 Package Capability Lead Count) Dsso_mode DL_mode DP_mode DV_mode DT_mode DC_mode (Refer Table 1-12.) DL_mode Lead inductance derating factor DP_mode Process derating factor DV_mode Voltage derating factor DT_mode Temperature derating factor DC_mode Cload derating factor (mode either vss.)
STD90/MDL90
1-32
Samsung ASIC
Introduction
1.12
VDD/VSS Rules Guidelines
Table 1-12. Item
Package Lead
Derating Equation Mode Equation
DL_vdd DL_vss 0.0052 0.9794 0.0052 1.0825 0.0094 1.0377 0.0377 0.5660 1.0000 1.1134 1.2887 1.0000 1.3208 1.5094 0.4467 voltage 2.5670 0.3093 voltage 2.1134 0.4403 voltage 2.5283 0.2516 voltage 1.9057 0.0008 temperature 1.0000 0.0006 temperature 1.0066 0.0045 temperature 1.0000 0.0034 temperature 1.0274 0.0155 Cload 0.5361 0.0180 Cload 0.4588 0.0255 Cload 0.2358 0.0142 Cload 0.5755
Range
15nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temperature temperature temperature temperature 10pF Cload 30pF 30pF Cload 50pF 10pF Cload 30pF 30pF Cload 50pF
Process DP_vdd
DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss
Table 1-13.
NBvdd/NBvss Parameter (Process best, Volt 3.6V Temp. 0°C, Llead 1nH)
Voltage Type Normal NBvdd NBvss Slew-Rate Medium (sm) NBvdd NBvss Slew-Rate High (sh) NBvdd NBvss
Buffer Type
pob1 (pot1) pob2 (pot2) pob4 (pot4) pob8 (pot8) pob12 (pot12) 3.3V Interface pob16 (pot16) pob20 (pot20) pob24 (pot24) ptot1 ptot2 Tolerant ptot4 ptot6
NOTE: pob1 means output driver cells, pob24 means 24mA output driver cells.
Calculating number required power total from following expression: NVDDO1sso NVDDOeach_sso NVSSO1sso NVSSOeach_sso When there blocks which switching simultaneously with others, only maximum value NVDDO_each_sso/NVSSO_each_sso among those block should accounted. above formula, NVDDOsso Number VDD3O total buffers NVSSOsso Number VSSO total buffers
Samsung ASIC
1-33
STD90/MDL90
1.12
VDD/VSS Rules Guidelines
Introduction
Number power pads block under limit electromigration rule Calculating following expression:
eq_o NVDDO2SSO NVSSO2SSO
N_SSO_output
eq_o
N_SSO_bi
0.001 i_outload
0.001 j_outload j_out
where N_SSO_output number simultaneous switching output buffers used, N_SSO_bi number simultaneous switching bidirectional buffers used, Coutload Output load capacitance [pF] Operating voltage Maximum operating frequency [MHz] Switching ratio (typically 0.5) Sout Output mode ratio bidirectional buffers, (typically 0.5). Current limit VDD/VSS paris based electromigration rule.(100mA)
Number power pads non-SSO block Calculating following expression:
eq_o NVDDOnon_SSO NVSSOnon_SSO
N_non_SSO_output
eq_o
N_non_SSO_bi
0.001 i_outload
0.001 j_outload j_out
where N_non_SSO_output number simultaneous switching output buffers used, N_non_SSO_bi number simultaneous switching bidirectional buffers used, Coutload Output load capacitance [pF] Operating voltage Maximum operating frequency [MHz] Switching ratio (typically 0.5) Sout Output mode ratio bidirectional buffers, (typically 0.5). Current limit VDD/VSS paris based electromigration rule.(100mA)
Total number power pads VDD3O/VSSO Calculating following expressions:
Number VDD3O NVDDO1 SSO, NVDDO2 NVDDO non_SSO round-up Number VSSO
NVSSO1 SSO, NVSSO2 NVSSO non_SSO round-up
When open drain type buffers used, consider using VSSO pads since they have current sink only.
STD90/MDL90
1-34
Samsung ASIC
Introduction
1.13
Crystal Oscillator Consideration
1.13 Crystal Oscillator Consideration
1.13.1 OVERVIEW STD90/MDL90 contains circuit commonly referred "on-chip oscillator." on-chip circuit itself oscillator amplifier which suitable being used amplifier part feedback oscillator. With proper selection off-chip components, this oscillator circuit performs better than other types clock oscillators. very important select suitable off-chip components work with onchip oscillator circuitry. should noted, however, that Samsung cannot assume responsibility writing specifications off-chip components complete oscillator circuit, guaranteeing performance finished design production, more than transistor manufacturer, whose data sheets show number suggested amplifier circuits, assume responsibility operation, production, them. often asked don't publish list required crystal ceramic resonator specifications, recommend values other off-chip components. This been done past, sometimes with consequences that were intended. Suppose suggest maximum crystal resistance 30ohms some given frequency. Then your crystal supplier tells 30ohm crystals going cost twice much 50ohm crystals. Fearing that Samsung will "guarantee operation" with 50ohm crystals, order expensive ones. fact, Samsung guarantees only what embodied within Samsung product. Besides, there reason 50ohm crystals couldn't used, other off-chip components suitably adjusted. Should recommend values other off-chip components? Should 50ohm crystals 30ohm crystals? With respect what should optimize their selection? Should minimize start-up time maximize frequency stability? many applications, neither start-up time frequency stability particularly critical, "recommendations" only restricting your system unnecessary tolerances. depends application. 1.13.2 OSCILLATOR DESIGN CONSIDERATIONS ASIC designers have number options clocking system. main decision whether "on-chip" oscillator external oscillator. choice on-chip oscillator, what kinds external components external oscillator, what type oscillator would decisions have based both economic technical requirements. this section will discuss some factors that should considered. 1.13.2.1 On-Chip Oscillator most cases, on-chip amplifier with appropriate external components provides most economical solution clocking problem. Exceptions arise server environments when frequency tolerances tighter than about 0.01%. external components that commonly used CMOS gate oscillator
Samsung ASIC
1-35
STD90/MDL90
1.13
Crystal Oscillator Consideration
Introduction
positive reactance (normal crystal oscillator), capacitors, resistor shown figure below. Figure 1-14. CMOS Oscillator Inside Chip PADA
PADY
Feedback Amplifier
1.13.2.2 Crystal Specifications Specifications appropriate crystal very critical, unless frequency fundamental-mode crystal medium better quality used. often asked what maximum crystal resistance should specified. best answer that question lower better, what available. crystal resistance will have some effect start-up time steady-state amplitude, much that can't compensated appropriate selection capacitances, Similar questions asked about specifications load capacitance shunt capacitance. best advice give understand what these parameters mean they affect operation circuit (that being purpose this application note), then decide yourself such specifications meaningful your frequency tolerances tighter than about 0.1%. Part problem that crystal manufacturers accustomed talking "ppm" tolerances with radio engineers simply won't take your order until you've filled their list frequency tolerance requirements, both yourself crystal manufacturer. Don't 0.003% crystals your actual frequency tolerance 1.13.2.3 Oscillation Frequency oscillation frequency determined 99.5% crystal about 0.5% circuit external crystal. on-chip amplifier little effect frequency, which should since amplifier parameterizes temperature process dependent. influence on-chip amplifier frequency means input output (pin-to-ground) capacitances, which parallel PADA-to-PADY (pin-to-pin) capacitance, which parallels crystal. input pin-to-pin capacitances about each.
STD90/MDL90
1-36
Samsung ASIC
Introduction
1.13
Crystal Oscillator Consideration
Internal phase deviations capacitance 30pF. These deviations from ideal have less effect positive reactance oscillator (with inverting amplifier) than comparable series resonant oscillator (with non-inverting amplifier) reasons: first, effect output capacitor; second, positive reactance oscillator less sensitive, frequency-wise, such phase errors. 1.13.2.4 Selection Optimal values capacitors depend whether quartz crystal ceramic resonator being used, also application-specific requirements start-up time frequency tolerance. Start-up time sometimes more critical microcontroller systems than frequency stability, because various reset initialization requirements. Less commonly, accuracy oscillator frequency also critical, example, when oscillator being used time base. general rule, fast start-up stable frequency tend pull oscillator design opposite directions. Considerations both start-up time frequency stability over temperature suggest that should about equal least 20pF. (But they don't have either.) Increasing value these capacitances above some 50pF improves frequency stability. also tends increase start-up time. These maximum value (several hundred depending value quartz ceramic resonator) above which oscillator won't start all. on-chip amplifier simple inverter, user select values between some 100pF, depending whether start-up time frequency stability more critical parameter specific application. 1.13.2.5 Selection CMOS inverter might work better this application since large (1megaohm) used hold inverter linear region. Logic gates tend have fairly output resistance, which testabilizes oscillator. that reason resistor (several k-ohm) often added feedback network, shown Figure 1-14. higher frequencies 30pF capacitor sometimes used position, compensate some internal propagation delay. 1.13.2.6 Capacitance Internal pin-to-ground pin-to-pin capacitances, PADA PADY have some effect oscillator. These capacitances normally taken range 10pF, they extremely difficult evaluate. measurement such capacitance necessarily include effects from others. advantage positive reactance oscillator that pin-to ground cap. paralleled external bulk capacitance, precise determination their value unnecessary.
Samsung ASIC
1-37
STD90/MDL90
1.13
Crystal Oscillator Consideration
Introduction
would suggest that there little justification more precision than assign them value (PADA-to-ground PADA-to-PADY). This value probably error more than 4pF. PADY-to-ground cap. entirely "pin capacitance", more like "equivalent output capacitance" some 30pF, having include effect internal phase delays. This value varies some extent with temperature, process, frequency. 1.13.2.7 Placement Components Noise glitches arising PADA PADY pins wrong time cause miscount internal clock-generating circuitry. These kinds glitches produced through capacitive coupling between oscillator components traces carrying digital signals with fast rise fall times. this reason, oscillator components should mounted close chip have short, direct traces PADA, PADY, pins. possible, dedicated only crystal feedback amplifier. 1.13.3 TROUBLESHOOTING OSCILLATOR PROBLEMS first thing consider case difficulty that there significant differences stray caps between test actual application, particularly actual application multi-layer board. Noise glitches, that present test application board, another possibility. Capacitive coupling between oscillator circuitry other signal already been mentioned source miscounts internal clocking circuitry. Inductive coupling also doubtful, there strong current nearby. These problems function layout. Surrounding oscillator components with "quit" traces (for example, ground) will alleviate capacitive coupling signals having fast transition time. minimize inductive coupling, layout should minimize areas loops formed oscillator components. loops demanding checked follows: PADA through resonator PADY; PADA through pin; PADY through pin. unusual find that ground ends eventually connect only after looping around farthest ends board. good. Finally, should overlooked that software problems sometimes imitate symptoms slow-starting oscillator incorrect frequency. Never underestimate perversity software problem.
STD90/MDL90
1-38
Samsung ASIC
Electrical Characteristics
Contents
Electrical Characteristics Input Buffer Curves. Output Drive Capabilities
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
0.3V, 70°C case normal I/O)
Symbol VTIIH Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type B24Note2 Type Type Type Type Type Type Type Type level output voltage Type B24Note2 Type Type Type Type Type Type Type Type Tri-state output leakage current Output short circuit current Quiescent supply current Input capacitanceNote4 12mA 16mA 20mA 24mA VOUT =VSS 3.6V, 3.6V, -170 100Note3 Input Bidirectional Buffers Output Buffer 0.05 -1µA -1mA -2mA -4mA -8mA -12mA -16mA -20mA -24mA 0.05 LVCMOS LVCMOS LVCMOS Condition Type Unit
COUT
Output capacitanceNote4
Samsung ASIC
STD90/MDL90
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
0.3V, VEXT 0.25V, 70°C case 5V-tolerant I/O)
Symbol VIHNote1 VILNote1 VTIIH Parameter High level input voltage LVCMOS interface level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type B16Note2 Type Type Type Type level output voltage Type B16Note2 Type Type Type Type Tri-state output leakage current Output short circuit current Quiescent supply current Input capacitanceNote4 VOUT =VSS VEXT 3.6V, 3.6V, 100Note3 input bidirectional buffers output buffer 0.05 -1µA -1mA -2mA -4mA -6mA 0.05 LVCMOS LVCMOS LVCMOS Condition Type Unit
COUT NOTES:
Output capacitanceNote4
5V-tolerant input have less than 0.2V hysteresis. Type means output driver cells, type B6/B24 means 6mA/24mA output driver cells. This value depends customer design. This value excludes package parasitics.
STD90/MDL90
Samsung ASIC
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
10%, 70°C
Symbol VTIIH Parameter High level input voltage CMOS interface level input voltage CMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold High level input current Input buffer Input buffer with pull-down level input current Input buffer Input buffer with pull-up High level output voltage Type B24Note1 Type Type Type Type Type Type Type Type level output voltage Type B24Note1 Type Type Type Type Type Type Type Type Tri-state output leakage current Output short circuit current Quiescent supply current Input capacitanceNote3 12mA 16mA 20mA 24mA VOUT =VSS VVDD 3.3V, 3.3V, -150 100Note2 input bidirectional buffers output buffer 0.05 -1µA -1mA -2mA -4mA -8mA -12mA -16mA -20mA -24mA 0.05 CMOS CMOS CMOS Condition Type Unit
COUT NOTES:
Output capacitanceNote3
Type means output driver cells, type B6/B24 means 6/24mA output driver cells. This value depends customer design. This value excludes package parasitics.
Samsung ASIC
STD90/MDL90
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol TSTG Parameter supply voltage input voltage input current Storage temperature 3.3V tolerant -0.3 +0.3 -0.3 Rating Unit
Recommended Operating Conditions
Symbol supply voltage Commercial temperature range Industrial temperature range Parameter 3.3V Rating Unit
NOTE: electrical characteristics applied digital cell library without analog core.
Samsung ASIC
STD90/MDL90
ELECTRICAL CHARACTERISTICS
INPUT BUFFER CURVES
INPUT BUFFER CURVES
Input Buffer Transfer Curves
[VDD 3.3V, 25°C, Typical Process]
Vout[V]
Vout[V]
Vin[V]
Vin[V]
CMOS
CMOS Schmitt Trigger
Input Clock Drivers Transfer Curves
[VDD 3.3V, 25°C, Typical Process]
Vout[V]
Vout[V]
Vin[V]
Vin[V]
CMOS
CMOS Schmitt Trigger
Input Buffer Pull-Down/Pull-Up Characteristics
Samsung ASIC
STD90/MDL90
INPUT BUFFER CURVES
ELECTRICAL CHARACTERISTICS
[VDD 3.3V, 25°C, Typical Process]
Ids[uA]
32.9 30.0
Ids[uA]
32.5 30.0
20.0
20.0
10.0
10.0
Vin[V]
Vin[V]
Pull-Down
Pull-Up
STD90/MDL90
Samsung ASIC
ELECTRICAL CHARACTERISTICS
OUTPUT DRIVE CAPABILITIES
OUTPUT DRIVE CAPABILITIES
Characteristics [VDD 3.3V, 25°C, Typical Process]
[mA]
148.6 125.0 100.0 75.0 50.0 25.0
pob24 pob20 pob16 pob12
IOL[mA]
119.9 100.0 75.0 50.0
pob24 pob20 pob16 pob12 pob8
pob8 pob4 pob2 pob1
25.0
pob4 pob2 pob1
Vout
Vout
P-TR Characteristics
N-TR Characteristics
Samsung ASIC
STD90/MDL90
Internal Macrocells
Contents
Overview Summary Tables. Logic Cells. Flip-Flops. 3-260 Latches. 3-372 Holder. 3-414 Internal Clock Drivers 3-415 Decoders 3-418 Adders 3-426 Multiplexers 3-435
INTERNAL MACROCELLS
OVERVIEW
OVERVIEW
third chapter contains data sheets logic cells, flip-flops, latches, holder, internal clock drivers, decoders, adders multiplexers. electrical characteristics each cell follow basic cell data. Summary tables following pages list whole STD90/MDL90 internal macrocells type show their reference page numbers your convenience. Moreover, find more detailed description tables leading pages each category.
Samsung ASIC
STD90/MDL90
SUMMARY TABLES
INTERNAL MACROCELLS
SUMMARY TABLES
Logic Cells
Cell Type Cell Cell Name AD2DH/AD2/AD2D2/AD2D4 AD3DH/AD3/AD3D2/AD3D4 AD4DH/AD4/AD4D2/AD4D4 AD5/AD5D2/AD5D4 NAND Cell ND2DH/ND2/ND2D2/ND2D4 ND3DH/ND3/ND3D2/ND3D4 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 ND5/ND5D2/ND5D4 ND6/ND6D2/ND6D4 ND8/ND8D2/ND8D4 Cell NR2DH/NR2/NR2D2/NR2D2B/NR2D4 NR3DH/NR3/NR3D2/NR3D2B/NR3D4 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 NR5/NR5D2/NR5D4 NR6/NR6D2/NR6D4 NR8/NR8D2/NR8D4 Cell OR2DH/OR2/OR2D2/OR2D4 OR3DH/OR3/OR3D3/OR3D4 OR4DH/OR4/OR4D2/OR4D4 OR5/OR5D2/OR5D4 Exclusive-NOR Cell Exclusive-OR Cell Combinational Cell XN2/XN2D2/XN2D4 XN3/XN3D2/XN3D4 XO2/XO2D2/XO2D4 XO3/XO3D2/XO3D4 AO21/AO21D2/AO21D2B/AO21D4 AO211/AO211D2/AO211D2B/AO211D4 AO2111/AO2111D2 AO22/AO22D2/AO22D2B/AO22D4 AO22A/AO22D2A/AO22D4A AO221/AO221D2/AO221D4 AO222/AO222D2/AO222D2B/AO222D4 AO222A/AO222D2A/AO222D4A AO2222/AO2222D2/AO2222D4 AO31/AO31D2/AO31D4 AO311/AO311D2/AO311D4 AO3111/AO3111D2 AO32/AO32D2/AO32D4 Page 3-15 3-17 3-19 3-22 3-25 3-27 3-30 3-33 3-36 3-40 3-44 3-46 3-49 3-52 3-56 3-60 3-64 3-66 3-69 3-72 3-76 3-78 3-80 3-82 3-84 3-87 3-90 3-93 3-96 3-98 3-102 3-107 3-109 3-113 3-115 3-119 3-122
STD90/MDL90
Samsung ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Cell Type
Cell Name AO321/AO321D2/AO321D4 AO322/AO322D2/AO322D4 AO33/AO33D2/AO33D4 AO331/AO331D2/AO331D4 AO332/AO332D2/AO332D4 AO4111/AO4111D2
Page 3-126 3-130 3-134 3-138 3-142 3-146 3-149 3-152 3-155 3-158 3-161 3-163 3-167 3-172 3-176 3-178 3-182 3-185 3-189 3-193 3-197 3-201 3-205 3-209 3-212 3-214 3-215 3-216 3-218 3-219 3-220 3-221 3-222 3-223 3-224 3-225 3-226 3-227 3-228 3-229 3-230
Combinational Cell NAND
OA21/OA21D2/OA21D2B/OA21D4 OA211/OA211D2/OA211D2B/OA211D4 OA2111/OA2111D2 OA22/OA22D2/OA22D2B/OA22D4 OA22A/OA22D2A/OA22D4A OA221/OA221D2/OA221D4 OA222/OA222D2/OA222D2B/OA222D4 OA2222/OA2222D2/OA2222D4 OA31/OA31D2/OA31D4 OA311/OA311D2/OA311D4 OA3111/OA3111D2 OA32/OA32D2/OA32D4 OA321/OA321D2/OA321D4 OA322/OA322D2/OA322D4 OA33/OA33D2/OA33D4 OA331/OA331D2/OA331D4 OA332/OA332D2/OA332D4 OA4111/OA4111D2
Complex Cells
SCG1 SCG2 SCG3 SCG4 SCG5 SCG6 SCG7 SCG8 SCG9 SCG10 SCG11 SCG12 SCG13 SCG14 SCG15 SCG16 SCG17
Samsung ASIC
STD90/MDL90
SUMMARY TABLES
INTERNAL MACROCELLS
Cell Type Complex Cells SCG18 SCG19 SCG20 SCG21 SCG22 Delay Cells DL1D2/DL1D4 DL2D2/DL2D4 DL3D2/DL3D4 DL4D2/DL4D4 DL5D2/DL5D4 DL10D2/DL10D4 Inverter Inverting Tri-State Buffer Non-Inverting Buffer
Cell Name
Page 3-231 3-232 3-233 3-234 3-235 3-236 3-237 3-238 3-239 3-240 3-241 3-242 3-245 3-247 3-249 3-251 3-254 3-257
IVCD(11/13)/IVCD(22/26)/IVCD44 IVT/IVTD2/IVTD4/IVTD8/IVTD16 NIT/NITD2/NITD4/NITD8/NITD16
Flip-Flops
Cell Type Flip-Flop FD1/FD1D2 FD1CS/FD1CSD2 FD1S/FD1SD2 FD1SQ/FD1SQD2 FD1Q/FD1QD2 Flip-Flop with Reset FD2/FD2D2 FD2CS/FD2CSD2 FD2S/FD2SD2 FD2SQ/FD2SQD2 FD2Q/FD2QD2 Flip-Flop with FD3/FD3D2 FD3CS/FD3CSD2 FD3S/FD3SD2 FD3SQ/FD3SQD2 FD3Q/FD3QD2 Flip-Flop with Reset, FD4/FD4D2 FD4CS/FD4CSD2 FD4S/FD4SD2 FD4SQ/FD4SQD2 FD4Q/FD4QD2 Cell Name Page 3-263 3-265 3-268 3-270 3-272 3-274 3-276 3-280 3-283 3-286 3-288 3-290 3-293 3-296 3-299 3-301 3-305 3-309 3-313 3-316
STD90/MDL90
Samsung ASIC
INTERNAL MACROCELLS
SUMMARY TABLES
Cell Type Flip-Flop with Negative Edge Trigger FD5/FD5D2 FD5S/FD5SD2 FD6/FD6D2 FD6S/FD6SD2 FD7/FD7D2 FD7S/FD7SD2 FD8/FD8D2 FD8S/FD8SD2 Flip-Flop with Synchronous Clear FDS2/FDS2D2
Cell Name
Page 3-318 3-320 3-322 3-324 3-327 3-329 3-332 3-336 3-340 3-342 3-345 3-347 3-349 3-352 3-355 3-357 3-359 3-361 3-364 3-367 3-370
FDS2CS/FDS2CSD2 FDS2S/FDS2SD2 FDS3/FDS3D2 FDS3CS/FDS3CSD2 FDS3S/FDS3SD2 Flip-Flop FJ1/FJ1D2 FJ1S/FJ1SD2 FJ2/FJ2D2 FJ2S/FJ2SD2 FJ4/FJ4D2 FJ4S/FJ4SD2 Toggle Flip-Flop FT2/FT2D2
Latches
Cell Type Latch with Active High LD1/LD1D2 LD1A/LD1D2A LD1Q/LD1QD2 LD2/LD2D2 LD2Q/LD2QD2 LD3/LD3D2 LD4/LD4D2 Latch with Active LD5/LD5D2 LD5Q/LD5QD2 LD5S/LD5SD2 LD6/LD6D2 LD6Q/LD6QD2 LD7/LD7D2 LD8/LD8D2 Latch LS0/LS0D2 LS1/LS1D2 Cell Name Page 3-373 3-375 3-377 3-379 3-382 3-384 3-387 3-390 3-392 3-394 3-397 3-400 3-402 3-405 3-408 3-410
Samsung ASIC
STD90/MDL90
SUMMARY TABLES
INTERNAL MACROCELLS
Holder
Cell Type Holder BUSHOLDER Cell Name Page 3-414
Internal Clock Drivers
Cell Type Internal Clock Driver Cell Name CK2/CK4/CK6/CK8/CK12/CK16/CK20 Page 3-416
Decoders
Cell Type Non-Inverting Decoder Inverting Decoder DC4I DC8I Cell Name Page 3-419 3-421 3-423
Adders
Cell Type Full Adder Half Adder Complex Cells FADH/FA/FAD2 HADH/HA/HAD2 SCG23 Cell Name Page 3-427 3-431 3-434
Multiplexers
Cell Type Non-Inverting Inverting MX2X4 MX2IDH/MX2I/MX2ID2/MX2ID4 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A MX2IX4 Inverting Non-Inverting Non-Inverting MX3I/MX3ID2/MX3ID4 MX4/MX4D2/MX4D4 MX8/MX8D2/MX8D4 Cell Name MX2DH/MX2/MX2D2/MX2D4 Page 3-436 3-439 3-441 3-444 3-447 3-449 3-453 3-457
STD90/MDL90
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions
Cell Name AD2DH AD2D2 AD2D4 AD3DH AD3D2 AD3D4 AD4DH AD4D2 AD4D4 AD5D2 AD5D4 ND2DH ND2D2 ND2D4 ND3DH ND3D2 ND3D4 ND4DH ND4D2 ND4D2B ND4D4 ND5D2 ND5D4 ND6D2 ND6D4 ND8D2 ND8D4 NR2DH Function Description 2-Input with 0.5X Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input NAND with 0.5X Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 3-Input NAND with 0.5X Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with 2X(Buffered) Drive 4-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 2-Input with 0.5X Drive
Samsung ASIC
STD90/MDL90
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name NR2D2 NR2D2B NR2D4 NR3DH NR3D2 NR3D2B NR3D4 NR4DH NR4D2 NR4D2B NR4D4 NR5D2 NR5D4 NR6D2 NR6D4 NR8D2 NR8D4 OR2DH OR2D2 OR2D4 OR3DH OR3D2 OR3D4 OR4DH OR4D2 OR4D4 OR5D2 OR5D4 Function Description 2-Input with Drive 2-Input with Drive 2-Input with 2X(Buffered) Drive 2-Input with Drive 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with 2X(Buffered) Drive 3-Input with Drive 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with 2X(Buffered) Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 6-Input with Drive 6-Input with Drive 6-Input with Drive 8-Input with Drive 8-Input with Drive 8-Input with Drive 2-Input with 0.5X Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 3-Input with 0.5X Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with 0.5X Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive
STD90/MDL90
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name XN2D2 XN2D4 XN3D2 XN3D4 XO2D2 XO2D4 XO3D2 XO3D4 AO21 AO21D2 AO21D2B AO21D4 AO211 AO211D2 AO211D2B AO211D4 AO2111 AO2111D2 AO22 AO22D2 AO22D2B AO22D4 AO22A AO22D2A AO22D4A AO221 AO221D2 AO221D4 AO222 AO222D2 AO222D2B AO222D4 AO222A AO222D2A Function Description 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with 2X(Buffered) Drive 2-AND into 2-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with 2X(Buffered) Drive 2-AND into 3-NOR with Drive 2-AND into 4-NOR with Drive 2-AND into 4-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with 2X(Buffered) Drive 2-ANDs into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with 2X(Buffered) Drive Three 2-ANDs into 3-NOR with Drive Inverting 2-of-3 Majority with Drive Inverting 2-of-3 Majority with Drive
Samsung ASIC
STD90/MDL90
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO222D4A AO2222 AO2222D2 AO2222D4 AO31 AO31D2 AO31D4 AO311 AO311D2 AO311D4 AO3111 AO3111D2 AO32 AO32D2 AO32D4 AO321 AO321D2 AO321D4 AO322 AO322D2 AO322D4 AO33 AO33D2 AO33D4 AO331 AO331D2 AO331D4 AO332 AO332D2 AO332D4 AO4111 AO4111D2 OA21 OA21D2 OA21D2B OA21D4 OA211 OA211D2 Function Description Inverting 2-of-3 Majority with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 4-NOR with Drive 3-AND into 4-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR 3-ANDs 2-AND into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 4-AND into 4-NOR with Drive 4-AND into 4-NOR with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with 2X(Buffered) Drive 2-OR into 2-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive
STD90/MDL90
3-10
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA211D2B OA211D4 OA2111 OA2111D2 OA22 OA22D2 OA22D2B OA22D4 OA22A OA22D2A OA22D4A OA221 OA221D2 OA221D4 OA222 OA222D2 OA222D2B OA222D4 OA2222 OA2222D2 OA2222D4 OA31 OA31D2 OA31D4 OA311 OA311D2 OA311D4 OA3111 OA3111D2 OA32 OA32D2 OA32D4 OA321 OA321D2 OA321D4 OA322 OA322D2 OA322D4 Function Description 2-OR into 3-NAND with 2X(Buffered) Drive 2-OR into 3-NAND with Drive 2-OR into 4-NAND with Drive 2-OR into 4-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with 2X(Buffered) Drive 2-ORs into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with 2X(Buffered) Drive Three 2-ORs into 3-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 4-NAND with Drive 3-OR into 4-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive
Samsung ASIC
3-11
STD90/MDL90
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA33 OA33D2 OA33D4 OA331 OA331D2 OA331D4 OA332 OA332D2 OA332D4 OA4111 OA4111D2 SCG1 SCG2 SCG3 SCG4 SCG5 SCG6 SCG7 SCG8 SCG9 SCG10 SCG11 SCG12 SCG13 SCG14 SCG15 SCG16 SCG17 SCG18 SCG19 SCG20 SCG21 SCG22 DL1D2 DL1D4 DL2D2 DL2D4 DL3D2 Function Description 3-ORs into 2-NAND with Drive 3-ORs into 2-NAND with Drive 3-ORs into 2-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 3-ORs 2-OR into 3-NAND with Drive 4-OR into 4-NAND with Drive 4-OR into 4-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND 2-ANDs into 2-OR 2-NANDs into 3-NAND (two 2-ANDs into 2-NOR)s into 2-NAND Three 2-ANDs into 3-OR 2-AND into 2-OR 2-NAND (2-AND into 2-NOR) into 2-NAND 2-AND into 3-OR 2-OR into 2-AND 2-ORs into 2-AND 2-NORs into 3-NOR 2-NAND into 2-NOR 2-NOR into 2-NAND 2-NAND into 2-NAND 2-NAND into 3-NAND 2-OR with inverted input into 2-NAND 2-AND into 2-NOR into 2-NAND 2-AND into 2-NOR into 3-NAND 2-AND into 2-AND into 2-NOR 2-NOR into 2-NOR 2-NOR into 3-NOR 2-NAND into 2-OR into 2-NAND Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive
STD90/MDL90
3-12
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name DL3D4 DL4D2 DL4D4 DL5D2 DL5D4 DL10D2 DL10D4 IVDH IVD2 IVD3 IVD4 IVD6 IVD8 IVD16 IVCD11 IVCD13 IVCD22 IVCD26 IVCD44 IVTD2 IVTD4 IVTD8 IVTD16 IVTN IVTND2 IVTND4 IVTND8 IVTND16 NID2 NID3 NID4 NID6 NID8 NID16 Function Description Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive 10ns Delay Cell with Drive 10ns Delay Cell with Drive Inverter with 0.5X Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverter into Inverter Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Tri-State Buffer with Enable High, Drive
Samsung ASIC
3-13
STD90/MDL90
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name NITD2 NITD4 NITD8 NITD16 NITN NITND2 NITND4 NITND8 NITND16 Function Description Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive Non-Inverting Tri-State Buffer with Enable Low, Drive
STD90/MDL90
3-14
Samsung ASIC
AD2DH/AD2/AD2D2/AD2D4
2-Input with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD2DH
Input Load (SL) AD2D2
AD2D4
AD2DH
1.33
Gate Count AD2D2 AD2D4 1.33 1.67 2.33
Switching Characteristics
AD2DH
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.206 0.070 0.068*SL 0.156 0.054 0.051*SL 0.210 0.143 0.034*SL 0.204 0.144 0.030*SL 0.206 0.068 0.069*SL 0.156 0.054 0.051*SL 0.198 0.131 0.034*SL 0.215 0.155 0.030*SL *Group1 *Group2 *Group3
Delay [ns]
Delay Equations [ns] Group2* 0.057 0.072*SL 0.040 0.054*SL 0.146 0.033*SL 0.149 0.029*SL 0.057 0.072*SL 0.041 0.054*SL 0.135 0.033*SL 0.160 0.029*SL Group3* 0.047 0.072*SL 0.031 0.055*SL 0.147 0.033*SL 0.149 0.029*SL 0.047 0.072*SL 0.031 0.055*SL 0.135 0.033*SL 0.160 0.029*SL
Delay [ns] Delay Equations [ns] Group2* 0.068 0.038*SL 0.051 0.033*SL 0.154 0.017*SL 0.153 0.018*SL 0.068 0.038*SL 0.052 0.033*SL 0.142 0.017*SL 0.165 0.018*SL Group3* 0.051 0.039*SL 0.037 0.034*SL 0.156 0.017*SL 0.154 0.018*SL 0.051 0.039*SL 0.037 0.034*SL 0.144 0.017*SL 0.166 0.018*SL
Path
Parameter
Group1* 0.149 0.077 0.036*SL 0.121 0.059 0.031*SL 0.185 0.147 0.019*SL 0.185 0.146 0.019*SL 0.148 0.076 0.036*SL 0.123 0.061 0.031*SL 0.173 0.135 0.019*SL 0.197 0.159 0.019*SL *Group3 *Group1 *Group2
Samsung ASIC
3-15
STD90/MDL90
AD2DH/AD2/AD2D2/AD2D4
2-Input with 0.5X/1X/2X/4X Drive Switching Characteristics
AD2D2
Delay [ns] Delay Equations [ns] Group2* 0.063 0.019*SL 0.046 0.017*SL 0.158 0.009*SL 0.162 0.009*SL 0.064 0.019*SL 0.049 0.017*SL 0.146 0.009*SL 0.174 0.009*SL Group3* 0.038 0.019*SL 0.025 0.017*SL 0.165 0.009*SL 0.168 0.009*SL 0.038 0.019*SL 0.025 0.017*SL 0.153 0.009*SL 0.181 0.009*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.104 0.068 0.018*SL 0.082 0.051 0.015*SL 0.171 0.149 0.011*SL 0.175 0.153 0.011*SL 0.103 0.066 0.018*SL 0.084 0.052 0.016*SL 0.158 0.136 0.011*SL 0.187 0.164 0.011*SL *Group1 *Group2 *Group3
AD2D4
Delay [ns] Delay Equations [ns] Group2* 0.086 0.009*SL 0.064 0.008*SL 0.207 0.005*SL 0.203 0.005*SL 0.087 0.009*SL 0.069 0.008*SL 0.192 0.005*SL 0.214 0.005*SL Group3* 0.065 0.010*SL 0.044 0.008*SL 0.228 0.004*SL 0.221 0.004*SL 0.065 0.010*SL 0.045 0.008*SL 0.214 0.004*SL 0.232 0.004*SL
Path
Parameter
Group1* 0.105 0.087 0.009*SL 0.079 0.062 0.009*SL 0.212 0.198 0.007*SL 0.208 0.195 0.007*SL 0.106 0.087 0.009*SL 0.083 0.066 0.009*SL 0.197 0.184 0.007*SL 0.218 0.205 0.007*SL *Group1 *Group2 *Group3
STD90/MDL90
3-16
Samsung ASIC
AD3DH/AD3/AD3D2/AD3D4
3-Input with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD3DH
Input Load (SL) AD3D2
AD3D4
Gate Count AD3DH AD3D2 AD3D4 1.67 1.67 2.00 2.33
Switching Characteristics
AD3DH
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.218 0.082 0.068*SL 0.159 0.055 0.052*SL 0.242 0.171 0.035*SL 0.229 0.167 0.031*SL 0.219 0.083 0.068*SL 0.162 0.060 0.051*SL 0.237 0.167 0.035*SL 0.243 0.180 0.031*SL 0.219 0.083 0.068*SL 0.165 0.063 0.051*SL 0.232 0.161 0.035*SL 0.256 0.193 0.032*SL *Group3 *Group1 *Group2
Delay [ns]
Delay Equations [ns] Group2* 0.069 0.071*SL 0.046 0.054*SL 0.181 0.033*SL 0.175 0.029*SL 0.069 0.071*SL 0.047 0.054*SL 0.177 0.033*SL 0.189 0.029*SL 0.069 0.071*SL 0.050 0.054*SL 0.171 0.033*SL 0.203 0.029*SL Group3* 0.048 0.072*SL 0.031 0.055*SL 0.182 0.033*SL 0.176 0.029*SL 0.048 0.072*SL 0.031 0.055*SL 0.178 0.033*SL 0.190 0.029*SL 0.048 0.072*SL 0.031 0.055*SL 0.173 0.033*SL 0.204 0.029*SL
Delay [ns] Delay Equations [ns] Group2* 0.079 0.038*SL 0.053 0.033*SL 0.186 0.018*SL 0.174 0.018*SL 0.080 0.038*SL 0.056 0.033*SL 0.183 0.018*SL 0.189 0.018*SL 0.080 0.038*SL 0.060 0.033*SL 0.177 0.018*SL 0.202 0.018*SL Group3* 0.055 0.039*SL 0.036 0.034*SL 0.192 0.017*SL 0.177 0.018*SL 0.055 0.039*SL 0.036 0.034*SL 0.189 0.017*SL 0.192 0.018*SL 0.055 0.039*SL 0.037 0.034*SL 0.184 0.017*SL 0.206 0.018*SL
Path
Parameter
Group1* 0.158 0.085 0.036*SL 0.123 0.061 0.031*SL 0.215 0.173 0.021*SL 0.205 0.165 0.020*SL 0.159 0.087 0.036*SL 0.125 0.062 0.032*SL 0.212 0.170 0.021*SL 0.220 0.179 0.020*SL 0.159 0.087 0.036*SL 0.129 0.066 0.032*SL 0.206 0.164 0.021*SL 0.232 0.192 0.020*SL *Group1 *Group2 *Group3
Samsung ASIC
3-17
STD90/MDL90
AD3DH/AD3/AD3D2/AD3D4
3-Input with 0.5X/1X/2X/4X Drive Switching Characteristics
AD3D2
Delay [ns] Delay Equations [ns] Group2* 0.077 0.019*SL 0.052 0.017*SL 0.191 0.009*SL 0.183 0.009*SL 0.079 0.019*SL 0.057 0.016*SL 0.188 0.009*SL 0.199 0.009*SL 0.079 0.019*SL 0.063 0.016*SL 0.182 0.009*SL 0.212 0.009*SL Group3* 0.048 0.019*SL 0.028 0.017*SL 0.208 0.009*SL 0.193 0.009*SL 0.048 0.019*SL 0.028 0.017*SL 0.204 0.009*SL 0.209 0.009*SL 0.048 0.019*SL 0.030 0.017*SL 0.199 0.009*SL 0.223 0.009*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.116 0.079 0.019*SL 0.086 0.054 0.016*SL 0.202 0.178 0.012*SL 0.196 0.172 0.012*SL 0.118 0.080 0.019*SL 0.090 0.056 0.017*SL 0.199 0.175 0.012*SL 0.211 0.187 0.012*SL 0.117 0.080 0.019*SL 0.095 0.061 0.017*SL 0.193 0.169 0.012*SL 0.223 0.199 0.012*SL *Group3 *Group1 *Group2
AD3D4
Delay [ns] Delay Equations [ns] Group2* 0.105 0.009*SL 0.072 0.008*SL 0.242 0.005*SL 0.226 0.005*SL 0.103 0.009*SL 0.079 0.008*SL 0.239 0.005*SL 0.239 0.005*SL 0.105 0.009*SL 0.083 0.008*SL 0.233 0.005*SL 0.252 0.005*SL Group3* 0.089 0.010*SL 0.053 0.008*SL 0.278 0.004*SL 0.250 0.004*SL 0.088 0.010*SL 0.055 0.008*SL 0.274 0.004*SL 0.265 0.004*SL 0.088 0.010*SL 0.059 0.008*SL 0.269 0.004*SL 0.279 0.004*SL
Path
Parameter
Group1* 0.124 0.105 0.009*SL 0.087 0.070 0.009*SL 0.247 0.231 0.008*SL 0.230 0.216 0.007*SL 0.123 0.106 0.009*SL 0.093 0.075 0.009*SL 0.243 0.227 0.008*SL 0.244 0.229 0.007*SL 0.124 0.106 0.009*SL 0.098 0.081 0.008*SL 0.237 0.222 0.008*SL 0.256 0.241 0.008*SL *Group1 *Group2 *Group3
STD90/MDL90
3-18
Samsung ASIC
AD4DH/AD4/AD4D2/AD4D4
4-Input with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL)
AD4DH AD4DH 2.00
2.00
AD4D2 Gate Counts AD4D2 2.00
AD4D4 AD4D4 2.67
Samsung ASIC
3-19
STD90/MDL90
AD4DH/AD4/AD4D2/AD4D4
4-Input with 0.5X/1X/2X/4X Drive Switching Characteristics
AD4DH
Delay [ns] Delay Equations [ns] Group2* 0.087 0.070*SL 0.052 0.054*SL 0.217 0.032*SL 0.193 0.029*SL 0.088 0.070*SL 0.054 0.054*SL 0.219 0.032*SL 0.208 0.029*SL 0.088 0.070*SL 0.057 0.054*SL 0.219 0.032*SL 0.222 0.029*SL 0.087 0.070*SL 0.062 0.054*SL 0.218 0.032*SL 0.234 0.029*SL Group3* 0.055 0.071*SL 0.033 0.055*SL 0.221 0.032*SL 0.194 0.029*SL 0.055 0.071*SL 0.034 0.055*SL 0.223 0.032*SL 0.209 0.029*SL 0.055 0.071*SL 0.034 0.055*SL 0.224 0.032*SL 0.224 0.029*SL 0.055 0.071*SL 0.035 0.055*SL 0.222 0.032*SL 0.237 0.029*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.231 0.097 0.067*SL 0.165 0.062 0.052*SL 0.272 0.199 0.037*SL 0.246 0.182 0.032*SL 0.232 0.098 0.067*SL 0.168 0.066 0.051*SL 0.274 0.201 0.036*SL 0.261 0.197 0.032*SL 0.232 0.098 0.067*SL 0.173 0.072 0.050*SL 0.275 0.202 0.037*SL 0.274 0.210 0.032*SL 0.232 0.098 0.067*SL 0.177 0.075 0.051*SL 0.273 0.200 0.037*SL 0.286 0.220 0.033*SL *Group1 *Group2 *Group3
Delay [ns] Delay Equations [ns] Group2* 0.097 0.037*SL 0.061 0.032*SL 0.209 0.018*SL 0.193 0.017*SL 0.099 0.037*SL 0.063 0.032*SL 0.213 0.018*SL 0.211 0.017*SL 0.099 0.037*SL 0.069 0.032*SL 0.215 0.018*SL 0.227 0.017*SL 0.098 0.037*SL 0.074 0.032*SL 0.214 0.018*SL 0.240 0.017*SL Group3* 0.069 0.038*SL 0.040 0.033*SL 0.222 0.017*SL 0.198 0.017*SL 0.069 0.038*SL 0.041 0.033*SL 0.226 0.017*SL 0.215 0.017*SL 0.069 0.038*SL 0.042 0.033*SL 0.228 0.017*SL 0.232 0.017*SL 0.069 0.038*SL 0.046 0.033*SL 0.228 0.017*SL 0.248 0.017*SL
Path
Parameter
Group1* 0.173 0.099 0.037*SL 0.128 0.066 0.031*SL 0.236 0.192 0.022*SL 0.223 0.183 0.020*SL 0.173 0.099 0.037*SL 0.131 0.069 0.031*SL 0.240 0.196 0.022*SL 0.240 0.200 0.020*SL 0.174 0.100 0.037*SL 0.137 0.076 0.030*SL 0.242 0.198 0.022*SL 0.256 0.215 0.020*SL 0.173 0.099 0.037*SL 0.141 0.081 0.030*SL 0.241 0.198 0.022*SL 0.268 0.226 0.021*SL *Group1 *Group2 *Group3
STD90/MDL90
3-20
Samsung ASIC
AD4DH/AD4/AD4D2/AD4D4
4-Input with 0.5X/1X/2X/4X Drive Switching Characteristics
AD4D2
Delay [ns] Delay Equations [ns] Group2* 0.095 0.019*SL 0.061 0.016*SL 0.218 0.009*SL 0.205 0.009*SL 0.097 0.019*SL 0.065 0.016*SL 0.222 0.009*SL 0.223 0.009*SL 0.097 0.019*SL 0.073 0.016*SL 0.225 0.009*SL 0.239 0.009*SL 0.095 0.019*SL 0.079 0.016*SL 0.226 0.009*SL 0.253 0.009*SL Group3* 0.064 0.019*SL 0.032 0.017*SL 0.247 0.009*SL 0.218 0.009*SL 0.064 0.019*SL 0.033 0.017*SL 0.251 0.009*SL 0.236 0.009*SL 0.064 0.019*SL 0.035 0.017*SL 0.254 0.009*SL 0.254 0.009*SL 0.065 0.019*SL 0.039 0.017*SL 0.255 0.009*SL 0.272 0.009*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.132 0.094 0.019*SL 0.093 0.059 0.017*SL 0.228 0.201 0.013*SL 0.217 0.193 0.012*SL 0.134 0.096 0.019*SL 0.099 0.067 0.016*SL 0.233 0.206 0.013*SL 0.234 0.209 0.012*SL 0.135 0.097 0.019*SL 0.105 0.071 0.017*SL 0.235 0.209 0.013*SL 0.249 0.224 0.013*SL 0.134 0.097 0.019*SL 0.111 0.077 0.017*SL 0.236 0.209 0.013*SL 0.263 0.236 0.013*SL *Group1 *Group2 *Group3
AD4D4
Delay [ns] Delay Equations [ns] Group2* 0.130 0.009*SL 0.085 0.008*SL 0.281 0.005*SL 0.256 0.005*SL 0.130 0.009*SL 0.092 0.008*SL 0.285 0.005*SL 0.272 0.005*SL 0.130 0.009*SL 0.100 0.008*SL 0.288 0.005*SL 0.287 0.005*SL 0.130 0.009*SL 0.107 0.008*SL 0.288 0.005*SL 0.301 0.005*SL Group3* 0.119 0.009*SL 0.065 0.008*SL 0.330 0.004*SL 0.286 0.004*SL 0.119 0.009*SL 0.069 0.008*SL 0.334 0.004*SL 0.304 0.004*SL 0.119 0.009*SL 0.074 0.008*SL 0.337 0.004*SL 0.322 0.004*SL 0.119 0.009*SL 0.081 0.008*SL 0.337 0.004*SL 0.339 0.004*SL
Path
Parameter
Group1* 0.148 0.129 0.009*SL 0.100 0.084 0.008*SL 0.284 0.267 0.008*SL 0.260 0.245 0.007*SL 0.149 0.130 0.009*SL 0.106 0.088 0.009*SL 0.289 0.272 0.008*SL 0.276 0.261 0.008*SL 0.149 0.131 0.009*SL 0.113 0.096 0.009*SL 0.291 0.274 0.008*SL 0.291 0.275 0.008*SL 0.149 0.131 0.009*SL 0.120 0.101 0.009*SL 0.292 0.275 0.008*SL 0.305 0.288 0.008*SL *Group1 *Group2 *Group3
Samsung ASIC
3-21
STD90/MDL90
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4XDrive Logic Symbol
Truth Table
Cell Data
2.67
Input Load (SL) AD5D2 Gate Count AD5D2 3.00
AD5D4 AD5D4 4.33
Switching Characteristics
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.272 0.129 0.071*SL 0.156 0.100 0.028*SL 0.248 0.180 0.034*SL 0.262 0.224 0.019*SL 0.273 0.130 0.071*SL 0.164 0.109 0.027*SL 0.247 0.179 0.034*SL 0.286 0.248 0.019*SL 0.272 0.130 0.071*SL 0.173 0.120 0.027*SL 0.243 0.175 0.034*SL 0.309 0.270 0.020*SL 0.263 0.119 0.072*SL 0.120 0.064 0.028*SL 0.193 0.126 0.033*SL 0.234 0.197 0.018*SL 0.263 0.119 0.072*SL 0.127 0.073 0.027*SL 0.185 0.119 0.033*SL 0.258 0.220 0.019*SL *Group1 *Group2 *Group3
Delay [ns]
Delay Equations [ns] Group2* 0.120 0.074*SL 0.094 0.029*SL 0.186 0.033*SL 0.235 0.016*SL 0.121 0.074*SL 0.101 0.029*SL 0.184 0.033*SL 0.260 0.016*SL 0.120 0.074*SL 0.110 0.029*SL 0.181 0.033*SL 0.284 0.016*SL 0.113 0.074*SL 0.060 0.029*SL 0.128 0.033*SL 0.208 0.016*SL 0.112 0.074*SL 0.066 0.029*SL 0.121 0.033*SL 0.233 0.016*SL Group3* 0.109 0.074*SL 0.067 0.030*SL 0.189 0.033*SL 0.243 0.016*SL 0.109 0.074*SL 0.068 0.030*SL 0.187 0.033*SL 0.268 0.016*SL 0.109 0.074*SL 0.071 0.030*SL 0.184 0.033*SL 0.293 0.016*SL 0.108 0.074*SL 0.039 0.030*SL 0.130 0.033*SL 0.213 0.016*SL 0.108 0.074*SL 0.041 0.030*SL 0.123 0.033*SL 0.239 0.016*SL
STD90/MDL90
3-22
Samsung ASIC
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D2
Delay [ns] Delay Equations [ns] Group2* 0.115 0.037*SL 0.113 0.014*SL 0.200 0.016*SL 0.271 0.008*SL 0.114 0.037*SL 0.125 0.014*SL 0.199 0.016*SL 0.298 0.008*SL 0.114 0.037*SL 0.136 0.014*SL 0.193 0.016*SL 0.323 0.008*SL 0.102 0.037*SL 0.075 0.015*SL 0.139 0.016*SL 0.241 0.008*SL 0.102 0.037*SL 0.085 0.014*SL 0.132 0.016*SL 0.268 0.008*SL Group3* 0.094 0.037*SL 0.072 0.015*SL 0.207 0.016*SL 0.292 0.008*SL 0.094 0.037*SL 0.075 0.015*SL 0.205 0.016*SL 0.320 0.008*SL 0.094 0.037*SL 0.079 0.015*SL 0.200 0.016*SL 0.348 0.008*SL 0.092 0.037*SL 0.043 0.015*SL 0.141 0.016*SL 0.259 0.008*SL 0.093 0.037*SL 0.046 0.015*SL 0.133 0.016*SL 0.288 0.008*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.192 0.121 0.035*SL 0.143 0.115 0.014*SL 0.229 0.193 0.018*SL 0.281 0.258 0.011*SL 0.192 0.122 0.035*SL 0.154 0.127 0.014*SL 0.227 0.191 0.018*SL 0.307 0.284 0.012*SL 0.192 0.123 0.034*SL 0.165 0.138 0.014*SL 0.222 0.185 0.018*SL 0.331 0.307 0.012*SL 0.178 0.107 0.036*SL 0.104 0.075 0.015*SL 0.170 0.135 0.017*SL 0.251 0.227 0.012*SL 0.178 0.107 0.035*SL 0.114 0.085 0.015*SL 0.162 0.127 0.017*SL 0.276 0.251 0.012*SL *Group1 *Group2 *Group3
Samsung ASIC
3-23
STD90/MDL90
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D4
Delay [ns] Delay Equations [ns] Group2* 0.074 0.009*SL 0.062 0.008*SL 0.410 0.005*SL 0.377 0.005*SL 0.073 0.009*SL 0.063 0.008*SL 0.407 0.005*SL 0.395 0.005*SL 0.073 0.009*SL 0.061 0.008*SL 0.401 0.005*SL 0.411 0.005*SL 0.073 0.009*SL 0.061 0.008*SL 0.352 0.005*SL 0.349 0.005*SL 0.073 0.009*SL 0.062 0.008*SL 0.343 0.005*SL 0.366 0.005*SL Group3* 0.047 0.010*SL 0.041 0.008*SL 0.420 0.004*SL 0.395 0.004*SL 0.047 0.010*SL 0.042 0.008*SL 0.417 0.004*SL 0.412 0.004*SL 0.047 0.010*SL 0.042 0.008*SL 0.410 0.004*SL 0.428 0.004*SL 0.047 0.010*SL 0.042 0.008*SL 0.362 0.004*SL 0.366 0.004*SL 0.047 0.010*SL 0.042 0.008*SL 0.353 0.004*SL 0.384 0.004*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.093 0.075 0.009*SL 0.078 0.061 0.008*SL 0.415 0.403 0.006*SL 0.382 0.369 0.007*SL 0.093 0.076 0.008*SL 0.078 0.061 0.008*SL 0.412 0.400 0.006*SL 0.400 0.387 0.007*SL 0.093 0.076 0.009*SL 0.078 0.062 0.008*SL 0.406 0.394 0.006*SL 0.416 0.402 0.007*SL 0.093 0.076 0.009*SL 0.077 0.061 0.008*SL 0.358 0.346 0.006*SL 0.354 0.340 0.007*SL 0.093 0.076 0.009*SL 0.076 0.058 0.009*SL 0.349 0.336 0.006*SL 0.372 0.358 0.007*SL *Group1 *Group2 *Group3
STD90/MDL90
3-24
Samsung ASIC
ND2DH/ND2/ND2D2/ND2D4
2-Input NAND with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
ND2DH
Input Load (SL) ND2D2
ND2D4
ND2DH
1.00
Gate Count ND2D2 ND2D4 1.00 1.67 2.67
Switching Characteristics
ND2DH
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.231 0.107 0.062*SL 0.240 0.106 0.067*SL 0.149 0.084 0.033*SL 0.142 0.067 0.038*SL 0.244 0.120 0.062*SL 0.232 0.094 0.069*SL 0.159 0.095 0.032*SL 0.128 0.053 0.037*SL *Group1 *Group2 *Group3
Delay [ns]
Delay Equations [ns] Group2* 0.075 0.070*SL 0.076 0.075*SL 0.088 0.032*SL 0.073 0.036*SL 0.088 0.070*SL 0.070 0.075*SL 0.095 0.032*SL 0.058 0.036*SL Group3* 0.053 0.071*SL 0.053 0.075*SL 0.084 0.032*SL 0.070 0.036*SL 0.065 0.071*SL 0.053 0.075*SL 0.091 0.032*SL 0.056 0.036*SL
Delay [ns] Delay Equations [ns] Group2* 0.087 0.038*SL 0.089 0.043*SL 0.088 0.017*SL 0.074 0.021*SL 0.102 0.038*SL 0.080 0.043*SL 0.097 0.017*SL 0.059 0.021*SL Group3* 0.051 0.039*SL 0.055 0.044*SL 0.084 0.017*SL 0.071 0.021*SL 0.065 0.039*SL 0.055 0.044*SL 0.092 0.017*SL 0.057 0.021*SL
Path
Parameter
Group1* 0.175 0.111 0.032*SL 0.184 0.108 0.038*SL 0.116 0.076 0.020*SL 0.109 0.061 0.024*SL 0.190 0.127 0.031*SL 0.176 0.101 0.038*SL 0.128 0.090 0.019*SL 0.097 0.051 0.023*SL *Group3 *Group1 *Group2
Samsung ASIC
3-25
STD90/MDL90
ND2DH/ND2/ND2D2/ND2D4
2-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics
ND2D2
Delay [ns] Delay Equations [ns] Group2* 0.100 0.019*SL 0.100 0.021*SL 0.084 0.009*SL 0.071 0.010*SL 0.115 0.019*SL 0.091 0.021*SL 0.096 0.009*SL 0.057 0.010*SL Group3* 0.053 0.019*SL 0.057 0.022*SL 0.085 0.009*SL 0.072 0.010*SL 0.067 0.019*SL 0.057 0.022*SL 0.093 0.009*SL 0.058 0.010*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.144 0.114 0.015*SL 0.147 0.109 0.019*SL 0.096 0.073 0.012*SL 0.086 0.059 0.013*SL 0.160 0.131 0.015*SL 0.139 0.102 0.019*SL 0.110 0.089 0.011*SL 0.074 0.050 0.012*SL *Group1 *Group2 *Group3
ND2D4
Delay [ns] Delay Equations [ns] Group2* 0.106 0.009*SL 0.103 0.010*SL 0.077 0.004*SL 0.063 0.005*SL 0.122 0.009*SL 0.095 0.010*SL 0.091 0.004*SL 0.052 0.005*SL Group3* 0.059 0.010*SL 0.061 0.011*SL 0.085 0.004*SL 0.072 0.005*SL 0.073 0.010*SL 0.061 0.011*SL 0.093 0.004*SL 0.057 0.005*SL
Path
Parameter
Group1* 0.126 0.110 0.008*SL 0.123 0.102 0.011*SL 0.082 0.068 0.007*SL 0.070 0.055 0.007*SL 0.143 0.129 0.007*SL 0.118 0.098 0.010*SL 0.097 0.085 0.006*SL 0.060 0.047 0.007*SL *Group1 *Group2 *Group3
STD90/MDL90
3-26
Samsung ASIC
ND3DH/ND3/ND3D2/ND3D4
3-Input NAND with 0.5X/1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL)
ND3DH ND3DH 1.33
1.33
Gate Count
ND3D2 ND3D2 2.33
ND3D4 ND3D4 4.00
Samsung ASIC
3-27
STD90/MDL90
ND3DH/ND3/ND3D2/ND3D4
3-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics
ND3DH
Delay [ns] Delay Equations [ns] Group2* 0.102 0.070*SL 0.124 0.086*SL 0.102 0.032*SL 0.089 0.039*SL 0.120 0.070*SL 0.121 0.086*SL 0.114 0.032*SL 0.086 0.040*SL 0.141 0.070*SL 0.117 0.086*SL 0.125 0.032*SL 0.079 0.040*SL Group3* 0.083 0.071*SL 0.107 0.086*SL 0.099 0.032*SL 0.087 0.040*SL 0.102 0.071*SL 0.107 0.086*SL 0.112 0.032*SL 0.085 0.040*SL 0.120 0.071*SL 0.107 0.086*SL 0.123 0.032*SL 0.079 0.040*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.255 0.129 0.063*SL 0.307 0.147 0.080*SL 0.165 0.101 0.032*SL 0.167 0.088 0.040*SL 0.273 0.146 0.064*SL 0.302 0.141 0.081*SL 0.179 0.115 0.032*SL 0.164 0.084 0.040*SL 0.294 0.168 0.063*SL 0.295 0.131 0.082*SL 0.189 0.126 0.032*SL 0.157 0.077 0.040*SL *Group3 *Group1 *Group2
Delay [ns] Delay Equations [ns] Group2* 0.107 0.041*SL 0.129 0.052*SL 0.100 0.019*SL 0.088 0.024*SL 0.126 0.041*SL 0.125 0.052*SL 0.112 0.019*SL 0.084 0.024*SL 0.148 0.041*SL 0.119 0.052*SL 0.123 0.019*SL 0.077 0.024*SL Group3* 0.078 0.042*SL 0.103 0.053*SL 0.098 0.019*SL 0.085 0.024*SL 0.096 0.042*SL 0.103 0.053*SL 0.110 0.019*SL 0.083 0.024*SL 0.116 0.042*SL 0.103 0.053*SL 0.121 0.019*SL 0.077 0.024*SL
Path
Parameter
Group1* 0.200 0.129 0.036*SL 0.242 0.148 0.047*SL 0.135 0.094 0.021*SL 0.133 0.082 0.025*SL 0.220 0.148 0.036*SL 0.238 0.142 0.048*SL 0.149 0.110 0.019*SL 0.130 0.079 0.025*SL 0.242 0.170 0.036*SL 0.230 0.132 0.049*SL 0.160 0.122 0.019*SL 0.123 0.073 0.025*SL *Group1 *Group2 *Group3
STD90/MDL90
3-28
Samsung ASIC
ND3DH/ND3/ND3D2/ND3D4
3-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics
ND3D2
Delay [ns] Delay Equations [ns] Group2* 0.147 0.020*SL 0.109 0.026*SL 0.117 0.009*SL 0.067 0.012*SL 0.124 0.021*SL 0.118 0.026*SL 0.106 0.009*SL 0.074 0.012*SL 0.105 0.021*SL 0.123 0.026*SL 0.092 0.010*SL 0.078 0.012*SL Group3* 0.102 0.021*SL 0.086 0.027*SL 0.115 0.010*SL 0.069 0.012*SL 0.082 0.021*SL 0.086 0.027*SL 0.103 0.010*SL 0.075 0.012*SL 0.064 0.021*SL 0.086 0.027*SL 0.091 0.010*SL 0.077 0.012*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.196 0.163 0.017*SL 0.167 0.120 0.024*SL 0.134 0.113 0.011*SL 0.089 0.063 0.013*SL 0.172 0.139 0.017*SL 0.177 0.132 0.023*SL 0.122 0.100 0.011*SL 0.095 0.067 0.014*SL 0.154 0.120 0.017*SL 0.181 0.135 0.023*SL 0.106 0.081 0.012*SL 0.097 0.068 0.014*SL *Group3 *Group1 *Group2
ND3D4
Delay [ns] Delay Equations [ns] Group2* 0.157 0.010*SL 0.116 0.013*SL 0.116 0.005*SL 0.066 0.006*SL 0.134 0.010*SL 0.126 0.013*SL 0.104 0.005*SL 0.071 0.006*SL 0.115 0.010*SL 0.132 0.013*SL 0.087 0.005*SL 0.074 0.006*SL Group3* 0.109 0.011*SL 0.092 0.013*SL 0.117 0.005*SL 0.070 0.006*SL 0.088 0.011*SL 0.092 0.013*SL 0.105 0.005*SL 0.075 0.006*SL 0.069 0.011*SL 0.090 0.013*SL 0.093 0.005*SL 0.078 0.006*SL
Path
Parameter
Group1* 0.181 0.166 0.008*SL 0.145 0.122 0.012*SL 0.124 0.113 0.006*SL 0.077 0.063 0.007*SL 0.158 0.142 0.008*SL 0.155 0.133 0.011*SL 0.111 0.099 0.006*SL 0.081 0.067 0.007*SL 0.138 0.121 0.008*SL 0.158 0.134 0.012*SL 0.094 0.080 0.007*SL 0.083 0.067 0.008*SL *Group1 *Group2 *Group3
Samsung ASIC
3-29
STD90/MDL90
ND4DH/ND4/ND4D2/ND4D2B/ND4D4
4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Logic Symbol
Truth Table
Cell Data
ND4DH ND4DH 1.67
Input Load (SL) ND4D2 ND4D2B ND4D4 Gate Count ND4D2 ND4D2B ND4D4 1.67 2.67 2.67 3.33 (Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Switching Characteristics
ND4DH
Path
Parameter
Group1* 0.264 0.128 0.068*SL 0.358 0.173 0.093*SL 0.174 0.106 0.034*SL 0.178 0.090 0.044*SL 0.284 0.148 0.068*SL 0.357 0.170 0.094*SL 0.188 0.121 0.033*SL 0.181 0.092 0.044*SL 0.309 0.175 0.067*SL 0.352 0.162 0.095*SL 0.201 0.134 0.034*SL 0.182 0.093 0.045*SL 0.335 0.201 0.067*SL 0.347 0.156 0.096*SL 0.211 0.143 0.034*SL 0.181 0.092 0.045*SL *Group1 *Group2 *Group3
Delay [ns]
Delay Equations [ns] Group2* 0.105 0.074*SL 0.150 0.098*SL 0.106 0.034*SL 0.090 0.044*SL 0.124 0.074*SL 0.151 0.098*SL 0.120 0.034*SL 0.093 0.044*SL 0.148 0.074*SL 0.148 0.098*SL 0.133 0.034*SL 0.094 0.044*SL 0.174 0.074*SL 0.145 0.098*SL 0.144 0.034*SL 0.094 0.044*SL Group3* 0.089 0.074*SL 0.138 0.099*SL 0.105 0.034*SL 0.087 0.044*SL 0.109 0.074*SL 0.138 0.099*SL 0.118 0.034*SL 0.092 0.044*SL 0.131 0.074*SL 0.138 0.099*SL 0.132 0.034*SL 0.095 0.044*SL 0.153 0.074*SL 0.138 0.099*SL 0.146 0.034*SL 0.095 0.044*SL
STD90/MDL90
3-30
Samsung ASIC
ND4DH/ND4/ND4D2/ND4D2B/ND4D4
4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics
Delay [ns] Delay Equations [ns] Group2* 0.107 0.051*SL 0.154 0.067*SL 0.105 0.023*SL 0.087 0.030*SL 0.131 0.051*SL 0.153 0.067*SL 0.121 0.023*SL 0.091 0.030*SL 0.158 0.051*SL 0.149 0.068*SL 0.135 0.023*SL 0.094 0.030*SL 0.187 0.051*SL 0.145 0.068*SL 0.146 0.023*SL 0.093 0.030*SL Group3* 0.085 0.052*SL 0.135 0.068*SL 0.104 0.023*SL 0.084 0.030*SL 0.108 0.052*SL 0.135 0.068*SL 0.119 0.023*SL 0.091 0.030*SL 0.133 0.052*SL 0.135 0.068*SL 0.134 0.023*SL 0.095 0.030*SL 0.158 0.052*SL 0.135 0.068*SL 0.148 0.023*SL 0.094 0.030*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.220 0.127 0.046*SL 0.299 0.174 0.063*SL 0.150 0.102 0.024*SL 0.146 0.084 0.031*SL 0.243 0.150 0.046*SL 0.297 0.171 0.063*SL 0.167 0.121 0.023*SL 0.150 0.088 0.031*SL 0.271 0.180 0.045*SL 0.291 0.162 0.064*SL 0.181 0.135 0.023*SL 0.153 0.091 0.031*SL 0.300 0.210 0.045*SL 0.285 0.156 0.065*SL 0.192 0.144 0.024*SL 0.152 0.090 0.031*SL *Group1 *Group2 *Group3
ND4D2
Delay [ns] Delay Equations [ns] Group2* 0.112 0.025*SL 0.156 0.034*SL 0.103 0.012*SL 0.084 0.015*SL 0.137 0.025*SL 0.154 0.034*SL 0.119 0.012*SL 0.089 0.015*SL 0.164 0.025*SL 0.149 0.034*SL 0.133 0.012*SL 0.092 0.015*SL 0.193 0.025*SL 0.143 0.034*SL 0.142 0.012*SL 0.090 0.015*SL Group3* 0.080 0.026*SL 0.129 0.034*SL 0.101 0.012*SL 0.082 0.015*SL 0.104 0.026*SL 0.129 0.034*SL 0.116 0.012*SL 0.089 0.015*SL 0.128 0.026*SL 0.129 0.034*SL 0.132 0.012*SL 0.093 0.015*SL 0.153 0.026*SL 0.129 0.034*SL 0.146 0.012*SL 0.092 0.015*SL
Path
Parameter
Group1* 0.172 0.130 0.021*SL 0.230 0.168 0.031*SL 0.122 0.095 0.014*SL 0.112 0.078 0.017*SL 0.196 0.153 0.022*SL 0.229 0.169 0.030*SL 0.141 0.116 0.012*SL 0.116 0.083 0.017*SL 0.223 0.179 0.022*SL 0.222 0.160 0.031*SL 0.155 0.131 0.012*SL 0.120 0.086 0.017*SL 0.251 0.207 0.022*SL 0.217 0.154 0.031*SL 0.165 0.141 0.012*SL 0.119 0.087 0.016*SL *Group3 *Group1 *Group2
Samsung ASIC
3-31
STD90/MDL90
ND4DH/ND4/ND4D2/ND4D2B/ND4D4
4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics
ND4D2B
Delay [ns] Delay Equations [ns] Group2* 0.050 0.019*SL 0.048 0.017*SL 0.259 0.009*SL 0.276 0.009*SL 0.050 0.019*SL 0.047 0.017*SL 0.277 0.009*SL 0.281 0.009*SL 0.050 0.019*SL 0.047 0.017*SL 0.292 0.009*SL 0.282 0.009*SL 0.051 0.019*SL 0.048 0.017*SL 0.304 0.009*SL 0.280 0.009*SL Group3* 0.033 0.020*SL 0.025 0.017*SL 0.261 0.009*SL 0.283 0.009*SL 0.033 0.020*SL 0.026 0.017*SL 0.279 0.009*SL 0.288 0.009*SL 0.033 0.020*SL 0.026 0.017*SL 0.294 0.009*SL 0.288 0.009*SL 0.033 0.020*SL 0.026 0.017*SL 0.306 0.009*SL 0.287 0.009*SL
(Typical process, 25°C, 3.3V, tR/tF 0.26ns, Standard Load)
Path
Parameter
Group1* 0.092 0.056 0.018*SL 0.081 0.048 0.017*SL 0.273 0.253 0.010*SL 0.289 0.267 0.011*SL 0.093 0.058 0.017*SL 0.083 0.052 0.015*SL 0.291 0.271 0.010*SL 0.294 0.272 0.011*SL 0.093 0.059 0.017*SL 0.083 0.052 0.015*SL 0.306 0.286 0.010*SL 0.295 0.272 0.011*SL 0.094 0.059 0.017*SL 0.083 0.051 0.016*SL 0.319 0.298 0.010*SL 0.293 0.270 0.011*SL *Group1 *Group2 *Group3
ND4D4
Delay [ns] Delay Equations [ns] Group2* 0.072 0.009*SL 0.068 0.008*SL 0.316 0.005*SL 0.312 0.005*SL 0.073 0.009*SL 0.068 0.008*SL 0.337 0.005*SL 0.318 0.005*SL 0.073 0.009*SL 0.068 0.008*SL 0.356 0.005*SL 0.319 0.005*SL 0.074 0.009*SL 0.068 0.008*SL 0.371 0.005*SL 0.317 0.005*SL Group3* 0.046 0.010*SL 0.045 0.008*SL 0.326 0.004*SL 0.330 0.004*SL 0.046 0.010*SL 0.045 0.008*SL 0.347 0.004*SL 0.335 0.004*SL 0.046 0.010*SL 0.045 0.008*SL 0.365 0.004*SL 0.337 0.004*SL 0.047 0.010*SL 0.045 0.008*SL 0.381 0.004*SL 0.335 0.004*SL
Path
Parameter
Group1* 0.091 0.073 0.009*SL 0.084 0.068 0.008*SL 0.322 0.309 0.006*SL 0.317 0.304 0.007*SL 0.092 0.073 0.009*SL 0.084 0.068 0.008*SL 0.343 0.330 0.006*SL 0.323 0.309 0.007*SL 0.093 0.076 0.009*SL 0.084 0.068 0.008*SL 0.361 0.349 0.006*SL 0.3
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