LC66P2316 Four-Bit Single-Chip Microcontroller with On-Chip PROM

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LC66P2316 Four-Bit Single-Chip Microcontroller with On-Chip PROM

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5487
LC66P2316 Four-Bit Single-Chip Microcontroller with On-Chip PROM
Preliminary Overview
LC66P2316 on-chip PROM version LC6623XX Series CMOS 4-bit single-chip microcontrollers. LC66P2316 appropriate program development product evaluation since provides identical functionality compatibility with LC662316A.
Package Dimensions
unit: 3025B-DIP42S
[LC66P2316]
15.24
On-chip capacity kilobytes, onchip capacity bits. Fully supports LC66000 Series common instruction (128 instructions). ports: pins DTMF generator This microcontroller incorporates circuit that generate sine wave outputs, DTMF output, melody output software applications. 8-bit serial interface: circuit Instruction cycle time: 0.95 Powerful timer functions prescalers Time limit timer, event counter, pulse width measurement, square wave output using 12-bit timer. Time limit timer, event counter, output, square wave output using 8-bit timer. Time base function using 12-bit prescaler. Powerful interrupt system with interrupt factors interrupt vector locations. External interrupts: factors/3 vector locations Internal interrupts: factors/4 vector locations (Waveform output internal interrupts: factors vector; shared with external expansion interrupts) Flexible functions Selectable options include 20-mA drive outputs, inverter circuits, pull-up open drain circuits. Optional runaway detection function (watchdog timer) 8-bit functions Power saving functions using halt hold modes. Packages: DIP42S, QIP48E (QFP48E) Evaluation LSIs: LC66599 (evaluation chip) EVA800/850-TB662YXX2
13.8
Features Functions
37.9
4.25
0.95
0.48
1.78
0.51
1.15
SANYO: DIP42S
unit: 3156-QFP48E
[LC66P2316]
17.2 14.0 0.15
17.2 14.0
0.35
2.70 (STAND OFF)
3.0max
15.6
SANYO: QFP48E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
22897HA (OT) 5487-1/27
0.25
LC66P2316 Series Organization
Type LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B/562B/566B LC66354C/356C/358C LC662104A/06A/08A LC662304A/06A/08A/12A/16A LC662508A/12A/16A LC665304A/06A/08A/12A/16A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2108* LC66E2316 LC66E2516 LC66E5316 LC66P2108* LC66P2316* LC66P2516 LC66P5316 Note: Under development pins 52/48 capacity K/12 K/16 K/12 K/16 K/12 K/16 capacity DIP64S DIP42S DIP64S DIP42S DIP30SD DIP42S DIP64S DIP48S DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP48E MFP30S QFP48E QFP64E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E Window evaluation versions V/0.92 Dual oscillator support V/0.95 On-chip DTMF generator versions V/0.95 Low-voltage versions V/3.92 Low-voltage high-speed versions V/0.92 V/0.92 Normal versions V/0.92 Features
K/12 K/16 K/12 K/16
K/12 K/16 EPROM OTPROM EPROM OTPROM EPROM OTPROM EPROM EPROM EPROM EPROM OTPROM OTPROM OTPROM OTPROM
DIC42S with window DIC64S with window DIC52S with window DIP30SD DIP42S DIP64S DIP48S
QFC48 with window QFC64 with window QFC48 with window MFP30S QFP48E QFP64E QFP48E
Window evaluation versions V/0.92
V/0.95
5487-2/27
LC66P2316 Assignments
DIP42S P20/SI0/A0 P21/SO0/A1 P22/SCK0/A2 P23/INT0/A3 P30/INT1/A4 P31/POUT0/A5 P32/POUT1/A6 OSC1 OSC2 RES/VPP/OE TEST/EPMOD P33/HOLD P40/INV0I/A7 P41/INV0O/A8 P42/INV1I/A9 P43/INV1O/A10 P50/A11 P13/D7 P12/D6 P11/D5 P10/D4 P03/D3 P02/D2 P01/D1 P00/D0 PD3/INV3O PD2/INV3I PD1/INV2O PD0/INV2I PC3/DASEC PC2/CE P63/PIN1 P62/DT P60/ML P53/INT2/TA P52/A13 P51/A12
LC66P2316
QFP48E P02/D2 P01/D1 P00/D0 PD3/INV30 PD2/INV31 PD1/INV20 PD0/INV21 PC3/DASEC PC2/CE P63/PIN P62/DT P03/D3 P10/D4 P11/D5 P12/D6 P13/D7 P20/SI0/A0 P21/SO0/A1 P22/SCK0/A2 P23/INT0/A3 P30/INT1/A4 LC66P2316 P31/POUT0/A5 P32/POUT1/A6 OSC1 OSC2 RES/VPP/OE TEST/EPMOD P33/HOLD P61/DP P60/ML P53/TA P52/A13 P51/A12 P50/A11 P43/INV10/A10 P42/INV11/A9 P41/INV00/A8 P40/INV01/A7
view
recommend reflow-soldering techniques solder-mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed dip-soldering bath (dip-soldering techniques).
5487-3/27
LC66P2316 Usage Notes LC66P2316 created program development, product evaluation, prototype development products based LC6623XX Series microcontrollers. Keep following points mind when using this product. After reset must held additional instruction cycles after oscillator stabilization period elapsed. Also, port output circuit types during instruction cycles immediately after high. Only then program counter program execution started from that location. (The port output circuits revert open-drain type during periods when low.)
VDDmin
least Oscillator stabilization least instruction
Program execution (PC) Open drain
Location Location
Port output type
Option switching Option specification period instruction cycles
Notes LC6623XX evaluation high EPROM area (locations 3FF0H 3FFFH) option specification area. Option specification data must programmed loaded into this area. Sanyo specified cross assembler this product program LC66S.EXE. Also, insert instructions that user programs attempt execute addresses that exceed capacity mask ROM, write zeros (00H) areas (other than 3FF0H 3FFFH) that exceed actual capacity mask ROM. Mounting notes structural considerations, Sanyo unable fully test one-time programmable products. Therefore, user must apply screening procedure described page these products. following procedure when ordering through Sanyo PROM writing service. (Note that this forfee service.) ordering one-time programmable mask versions same time: customer must provide EPROM mask version, order forms mask version, order forms one-time programmable version. ordering only one-time programmable version: customer must provide EPROM order forms one-time programmable version. last section EPROM (locations 3FF0H 3FFFH) option specification area, option specification data must written this area. Sanyo specified cross assembler this product program LC66S.EXE. Also, insert instructions that user programs attempt execute addresses that exceed capacity mask ROM, write zeros (00H) areas (other than 3FF0H 3FFFH) that exceed actual capacity mask ROM. Differences between this product mask version: Carefully read sections following pages that describe these differences.
5487-4/27
LC66P2316 Main differences between LC66E2316, LC66P2316, LC6623XX Series
Item Differences main characteristics Operating temperature range Operating supply voltage/operating frequency (cycle time) Input high-level current (RES) Input low-level current (RES) Current drain (Operating MHz) (Halt mode MHz) (Hold mode) Port output types reset Package LC6623XX Series (mask version) +70°C LC66E2316 +40°C LC66P2316 +70°C
V/0.95
V/0.95 Typical: (normal operation halt mode) Hold mode: maximum Typical: Larger than that mask versions Typical: maximum:
V/0.95 Typical: (normal operation halt mode) Hold mode: maximum Typical: Larger than that mask versions Typical: maximum:
Maximum: Maximum:
Typical: maximum:
output type specified options DIP42S QFP48E
Open-drain outputs DIC42S window package QFC48 window package
Open-drain outputs DIP42S QFP48E
Note: Although microcontroller will remain hold mode while hold mode, always reset start sequence (after switching HOLD from high, switch from high) when clearing hold mode. Also that current about flows from when low. This increases hold mode current drain about
data sheets individual products details other differences. System Block Diagram
STACK (512W) SYSTEM CONTROL FLAG
TEST OSC1 OSC2 HOLD
OTPROM 16KB
EPROM control
DASEC Vpp/OE EPMOD
DTMF GEN.
PRESCALER
TIMER0
SERIAL
POUT0 SCK0 INT0 INT1. INT2
INTERRUPT CONTROL
TIMER1 PIN1. POUT1 INVxO INVxI
(x=0
5487-5/27
LC66P2316 Function Overview
Overview ports Input output 4-bit 1-bit units support halt mode control function (This function specified single-bit units.) Used data pins EPROM mode Output driver type Options State after Standby mode reset operation Hold mode: Output High (option) Halt mode: Output retained Hold mode: Output High (option) Halt mode: Output retained
P00/D0 P01/D1 P02/D2 P03/D3
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
P10/D4 P11/D5 P12/D6 P13/D7
ports Input output 4-bit 1-bit units Used data pins EPROM mode
Pch: Pull-up type Nch: Intermediate sink current type
Pull-up output Output level reset
P20/SI0/A0 P21/SO0/A1 P22/SCK0/ P23/INT0/A3
ports Input output 4-bit 1-bit units also used serial input pin. also used serial output pin. also used serial clock SCK0 pin. also used INT0 interrupt request pin, also timer event counting pulse width measurement input. Used address pins EPROM mode ports Input output 3-bit 1-bit units also used INT1 interrupt request. also used square wave output from timer also used square wave output from timer also support 3-state outputs. Used address pins EPROM mode Hold mode control input Hold mode HOLD instruction when HOLD low. hold mode, restarted setting HOLD high level. This used input port along with P32. When P33/HOLD level, will reset level pin. Therefore, applications must P33/HOLD when power first applied.
Hold mode: Output Pch: CMOS type Nch: Intermediate sink current type CMOS output
Halt mode: Output
P30/INT1/A4 P31/POUT0/ P32/POUT1/
Hold mode: Output Pch: CMOS type Nch: Intermediate sink current type CMOS output Halt mode: Output retained
P33/HOLD
P40/INV0I/ P41/INV0O/ P42/INV1I/ P43/INV1O/
ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P53. used output 8-bit data when used conjunction with P53. Dedicated inverter circuit (option) Used address pins EPROM mode
Pch: Pull-up type CMOS type when inverter circuit option selected Nch: Intermediate sink current type
Pull-up output Output level reset Inverter circuit
High (option) Inverter output state.
Hold mode: Port output off, inverter output Halt mode: Port output retained, inverter output continues
Continued next page. 5487-6/27
LC66P2316
Continued from preceding page.
Overview Output driver type Options State after Standby mode reset operation
P50/A11 P51/A12 P52/A13 P53/INT2/TA
ports Input output 4-bit 1-bit units Input output 8-bit units when used conjunction with P43. used output 8-bit data when used conjunction with P43. also used INT2 interrupt request. Used address pins EPROM mode
Hold mode: Output Pch: Pull-up type Nch: Intermediate sink current type Pull-up output Output level reset High (option) Halt mode: Output retained
P60/ML P62/DT P63/PIN1
ports Input output 4-bit 1-bit units also used melody output pin. also used tone output pin. also used event count input timer
Hold mode: Output Pch: CMOS type Nch: Intermediate sink current type CMOS output Halt mode: Output retained Hold mode: Port output Halt mode: Port output retained Normal input Inverter goes output state. Hold mode: Inverter Output Halt mode: Inverter output continues Hold mode: input disabled
PC2/CE PC3/DASEC
ports Output 2-bit 1-bit units also used control DASEC EPROM mode.
Pch: CMOS type Nch: Intermediate sink current type
CMOS output
PD0/INV2I PD1/INV2O PD2/INV3I PD3/INV3O
Dedicated input ports Dedicated inverter circuits (option)
When inverter circuit option selected. Pch: CMOS type Nch: Intermediate sink current type
Inverter circuits
Dedicated input ports Halt mode: inputs accepted Hold mode: oscillator stops Halt mode: oscillator continues
OSC1 OSC2
System clock oscillator connections When external clock used, leave OSC2 open connect clock signal OSC1.
Ceramic oscillator external clock selection
Option selection
RES/VPP/
System reset input When P33/HOLD high level, level input will initialize CPU. This also used VPP/OE EPROM mode.
TEST/ EPMOD
test This must connected during normal operation. Setting this switches LC66P2316 EPROM mode.
Power supply pins
Note: Pull-up type: output circuit includes transistor that pulls VDD. CMOS output: Complementary output. output: Open-drain output.
5487-7/27
LC66P2316 User Options Port output level reset option output levels reset ports independent 4-bit groups, selected from following options.
Option Output high reset Output reset Conditions notes four bits ports group four bits ports group
Oscillator circuit options Main clock
Option Circuit Conditions notes
External clock
OSC1
input Schmitt characteristics
Ceramic oscillator
OSC1
Ceramic oscillator
OSC2
Note: There oscillator option.
Watchdog timer option runaway detection function (watchdog timer) selected option. Port output type options output type each (pin) ports (except P33/HOLD pin), selected individually from following options.
Option Circuit Conditions notes
Output data
Open-drain output
Input data Output data
port inputs have Schmitt characteristics.
port inputs have Schmitt characteristics. CMOS outputs (ports pull-up outputs (P0, distinguished drive capacity p-channel transistor.
Output with built-in pull-up resistor
Input data
5487-8/27
LC66P2316 Inverter array circuit option following options selected each following port sets: P40/P41, P42/P43, PD0/PD1, PD2/PD3.
Option Circuit Conditions notes
Output data Input data
Normal port circuit When open-drain output type selected
Output data
When built-in pull-up resistor output type selected
Input data Input Output data high Input data
Inverter circuit this option selected, circuit disabled signal. Also note that open-drain port output type option high level reset option must selected.
Output
Output data high Input data
5487-9/27
LC66P2316 LC662316 Series Option Data Area Definitions
area 3FF0H 3FF1H 3FF2H 3FF3H 3FF4H 3FF5H 3FF6H Unused This must Unused This must Unused This must Unused This must Output type Unused This must Unused Oscillator option Unused Output level reset Option specified Output level reset Option/data relationship high level, level This must external clock, ceramic oscillator This must level, high level none, (present)
Watchdog timer option Unused Output type Output type Output type Output type Output type Output type
This must
Continued next page.
LC66P2316
Continued from preceding page.
area 3FF7H 3FF8H 3FF9H 3FFAH 3FFBH 3FFCH 3FFDH Reserved. Must predefined data values. This data generated assembler. assembler used, this data `00'. Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must Unused This must Unused disabled option Unused Unused Unused Inverter output This must inverter output, none Inverter output Output type Unused This must Option specified Option/data relationship
This must disabled, enabled This must This must inverter output, none
Continued next page. 5487-11/27
LC66P2316
Continued from preceding page.
area 3FFEH 3FFFH Reserved. Must predefined data values. This data generated assembler. assembler used, this data `00'. Reserved. Must predefined data values. This data generated assembler. assembler used, this data `00'. Option specified Option/data relationship
Usage Notes Option specification When using Sanyo cross assembler with LC66P2316, version called "LC66S.EXE" specify actual microcontroller evaluated with pseudo instruction source file. port options must specified source file. cross assembler will create option code list option specification area (locations 3FF0H 3FFFH). also possible directly data option specification area. this done, options must specified according option code creation table shown following page. Writing EPROM special-purpose writing conversion board (the W66EP5316D package, W66EP2316Q package) allow EPROM programmers listed below used when writing data created cross assembler LC66P2316. EPROM programmers listed below used.
Manufacturer Advantest Ando AVAL Minato Electronics MODEL1890A Models that used R4945, R4944A, R4943, equivalent products AF9704
"27512 (VPP 12.5 Intel high-speed write" technique must used write EPROM. address range location 3FFFH. DASEC jumper must off. Using data security function data security function sets microcontroller advance that data that written microcontroller EPROM cannot read out. following procedure enable LC66P2316 data security function. write conversion board DASEC jumper position. Write data EPROM once again. this time, since this function will operate, EPROM programmer will issue error. However, this error does indicate that there problem either programmer LSI. Notes: data addresses "FF" step data security function will activated. Notes: data security function will activated step "blank program verify" operation sequence used. Notes: Always return jumper position after data security function been activated.
5487-12/27
LC66P2316
LC66P2316 (DIP) LC66P2316 (QFP)
corner
DASEC
Aligned
DASEC
Write board (W66EP5316D)
Write board (W66EP2316Q)
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input voltage Symbol VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 Output current ION2 -IOP1 -IOP2 ION1 Total current ION2 IOP1 IOP2 Allowable power dissipation Operating temperature Storage temperature Topr Tstg (except P33/HOLD pin), P61, other inputs (except P33/HOLD pin), P61, other inputs (except P33/HOLD pin), P41, P43, PC3, PD1, (except P33/HOLD pin), P6,and (except P33/HOLD pin), (except P33/HOLD pin), +70°C: DIP42S (QFP48E) Conditions Ratings -0.3 +7.0 -0.3 +12.0 -0.3 -0.3 +12.0 -0.3 (430) +125 Unit Note
Note: Applies pins with open-drain output specifications. pins with other than open-drain output specifications, ratings column that apply. oscillator input output pins, levels free-running oscillation level allowed. Sink current (Applies when inverter array specifications have been selected.) Source current (Applies pins except which pull-up output specifications, CMOS output specifications, inverter array specifications have been selected. Applies pins which inverter array specifications have been selected.) Contact your Sanyo representative electrical characteristics when inverter array buffer array options specified. recommend reflow soldering techniques solder mount packages. Please consult with your Sanyo representative details process conditions package itself directly immersed solder bath (solder spray techniques).
5487-13/27
LC66P2316 Allowable Operating Ranges +70°C, unless otherwise specified.
Parameter Operating supply voltage Memory retention supply voltage Symbol VDDH VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Operating frequency (instruction cycle time) [External clock input conditions] OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) OSC1: Defined Figure Input clock signal OSC1 leave OSC2 open. (External clock input must selected oscillator circuit option.) (Tcyc) VDD: During hold mode (except P33/HOLD pin), P61, P63: N-channel output transistor P33/HOLD, RES, OSC1: N-channel output transistor N-channel output transistor (except P33/HOLD pin), RES, OSC1: N-channel output transistor P33/HOLD: TEST: N-channel output transistor Conditions (10) 10.0 4.20 (0.95) Unit (µs) Note
Frequency
fext
4.20
Pulse width
textH, textL
Rise fall times
textR, textF
Note: Applies pins with open-drain specifications. However, VIH2 applies P33/HOLD pin. When ports have CMOS output specifications they cannot used input pins. port pins with CMOS output specifications cannot used input pins. Contact your Sanyo representative allowable operating ranges when inverter array used.
5487-14/27
LC66P2316 Electrical Characteristics +70°C, unless otherwise specified.
Parameter Symbol IIH1 Conditions (except P33/HOLD pin), P61, P63: 10.0 with output transistor OSC1, P33/HOLD (Does apply PC2, PC3, P61, P63):VIN VDD, with output transistor PC2, PC3: VDD, with output transistor RES: VDD, operating, halt mode RES: VDD, hold mode Input ports other than PC2, PC3: VSS, with output transistor PC2, PC3, VSS, with output transistor RES: (except P33/HOLD pin), (except P33/HOLD pin), -0.1 (except P33/HOLD pin): (except P33/HOLD pin): P61, P63: Does apply P61, P63: OSC1 (EXT), OSC1, OSC2: Figure Figure 10.0 -1.0 -1.0 Unit Note
Input high-level current
IIH2
IIH3 IIH4 IIH5 IIL1 Input low-level current IIL2 IIL3
Output high-level voltage
VOH1
Value output pull-up resistor
VOL1
Output low-level voltage VOL2 IOFF1 Output leakage current [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCFS VHYS IOFF2
SCK0: With timing Figure test load Figure
Tcyc Tcyc
Low-level high-level Input pulse widths Output Rise fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time Output
tICK tCKI
SI0: With timing Figure Stipulated with respect rising edge SCK0.
tCKO
SO0: With timing Figure test load Figure Stipulated with respect falling edge SCK0.
Continued next page. 5487-15/27
LC66P2316
Continued from preceding page.
Parameter [Pulse conditions] INT0: Figure conditions under which INT0 interrupt accepted, conditions under which timer event counter pulse width measurement input accepted INT1, INT2: Figure conditions under which corresponding interrupt accepted PIN1: Figure conditions under which timer event counter input accepted RES: Figure conditions under which reset applied. Symbol Conditions Unit Note
INT0 high low-level
tIOH, tIOL
Tcyc
High low-level pulse widths interrupt inputs other than INT0 PIN1 high low-level pulse widths high low-level pulse widths
tIIH, tIIL tPINH, tPINL tRSH, tRSL
Tcyc Tcyc Tcyc
Operating current drain Halt mode current drain Hold mode current drain
IDDHALT IDDHOLD
VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD: 4-MHz ceramic oscillator VDD: 4-MHz external clock VDD:
0.01
Note: With output transistor shared ports with open-drain output specifications. These pins cannot used input pins CMOS output specifications selected.When port option selected With output transistor shared ports with open-drain output specifications. rating pull-up output specification pins stipulated terms output pull-up current IPO. These pins cannot used input pins CMOS output specifications selected. With output transistor CMOS output specification pins. With output transistor pull-up output specification pins. With output transistor open-drain output specification pins. Reset state
Tone (DTMF) Output Characteristics Characteristics +70°C,
Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol DBCR1 THD1 Conditions Dual tones, Dual tones, Single tone, Unit
0.8VDD 0.2VDD External clock OPEN textF textL textR 1/fext textH
OSC1
(OSC2)
Figure External Clock Input Waveform
5487-16/27
LC66P2316
Operating minimum value Stable oscillation Oscillator unstable period tCFS
OSC1
OSC2
Ceramic oscillator
Figure Ceramic Oscillator Circuit Table Guaranteed Ceramic Oscillator Constants External capacitor type
External capacitor type Built-in capacitor type (Murata Mfg. Co., Ltd.) CSA4.00MG (Kyocera Corporation) KBR4.0MS (Murata Mfg. Co., Ltd.) CST4.00MG (Kyocera Corporation) KBR4.0MES
Figure Oscillator Stabilization Period
tCKCY
tCKL SCK0 SCK1 0.2VDD (input) 0.4VDD (output) tCK0
tCKR
tCKH
tCKF 0.8VDD (input) VDD-1 (output)
tICK tCKI 0.8VDD 0.2VDD R=1k VDD-1 0.4VDD TEST point C=50pF
Figure Serial Timing
tI0H tI1H tPINH tRSH 0.8VDD 0.2VDD tI0L tI1L tPINL tRSL
Figure Timing Load
Figure Input Timing INT0, INT1, INT2, PIN1, pins
P60/ML P62/DT
R=10
Figure Tone Output Load
5487-17/27
LC66P2316 Preconditions mounting one-time programmable microprocessors Usage Notes inherent structural considerations, impossible fully test one-time programmable microprocessors before PROM been programmed, i.e. before shipment from factory. recommend that users screen products whose PROM been written according following procedure improve reliability these products. nature product, possible test write operations bits one-time programmable microprocessors whose PROM been written. Therefore impossible guarantee 100% yield writing these products. Please understand that such guarantee made. Storage products moisture-proof packed (unopened) state Store products moisture-proof packages environment which temperature higher than 30°C relative humidity higher than 70%. Storage products after opening moisture-proof packaging After opening products that were packed moisture-proof packaging, mount (solder) those products soon possible. Store products more than hours after opening moisture-proof packaging environment which temperature higher than 30°C relative humidity higher than 70%.
Preconditions mounting products that were programmed user Preconditions mounting products that were programmed Sanyo
DIP/QFP product
DIP/QFP product
Programming verification
Recommended screening conditions High-temperature bake (disconnected) +1HR 150°C ±5°C, -0HR
Program data verification
Mounting
Mounting
Sanyo writing service Sanyo provides for-fee writing service that includes writing one-time programmable ROM, printing, screening, read-out verification. Contact your Sanyo sales representative details.
5487-18/27
LC66P2316 LC66XXXX Series Instruction Table function) Abbreviations: Accumulator register Carry flag Zero flag Data pointer DPH, Data pointer DPX, Data memory (HL): Data memory pointed DPH, data pointer (XY): Data memory pointed DPX, auxiliary data pointer (HL): words data memory (starting even address) pointed DPH, data pointer Stack pointer (SP): words data memory pointed stack pointer (SP): Four words data memory pointed stack pointer bits immediate data specification
PCh: PCm: PCl: TIMER0: TIMER1: SIO: (i4): INT:
Bits Bits Bits User flag, Timer Timer Serial register Port Port indicated bits immediate data Interrupt enable flag Indicates contents location Transfer direction, result Exclusive Logical Logical Addition Subtraction Taking one's complement
5487-19/27
LC66P2316
Instruction code Mnemonic [Accumulator manipulation instructions] Clear Decimal adjust addition Decimal adjust subtraction Clear Complement Increment Decrement Rotate right through Rotate left through Transfer Transfer Exchange with Clear (Equivalent (AC) (Equivalent (AC) (Equivalent 0AH.) (AC) (AC) (AC) (CF), (ACn (AC0) (CF), (ACn), (AC3) (AC) (AC) Clear Take one's complement Increment Decrement Shift (including right. vertical skip function. Number bytes Number cycles Affected status bits
Operation
Description
Note
Shift (including left.
Transfer contents
Transfer contents
Exchange contents
[Memory manipulation instructions] IMDR Increment Decrement Increment direct (HL) (HL)] (HL) (HL)] (i8) (i8)] (i8) (i8)] (HL), (HL), Increment (HL). Decrement (HL). Increment (i8). Decrement (i8). (HL) specified Clear (HL) specified
DMDR Decrement direct data Reset data
[Arithmetic, logic comparison instructions] (AC) (HL)] contents (HL) two's complement values store result
ADDR direct
contents (i8) two's complement (AC) (i8)] values store result (AC) (HL)] (CF) contents (HL) two's complement values store result contents immediate data two's complement values store result Subtract contents from (HL) two's complement values store result Take logical (HL) store result Take logical (HL) store result
with
immediate data
(AC)
SUBC
Subtract from with
(HL)] (AC) (CF) (AC) (HL)] (AC) (HL)]
will zero there borrow otherwise.
ANDA
with then store with then store
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LC66P2316
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Instruction code Mnemonic [Arithmetic, logic comparison instructions] Exclusive with then store with then store with then store (AC) (HL)] (HL) (AC) (HL)] (HL) (AC) (HL)] Take logical exclusive (HL) store result Take logical (HL) store result (HL). Take logical (HL) store result (HL). Compare contents (HL) clear according result. Compare with (HL)] (AC) Magnitude comparison (HL)] (AC) (HL)] (AC) (HL)] (AC) Number bytes Number cycles Affected status bits
Operation
Description
Note
ANDM
Compare contents immediate data clear according result. Compare with immediate data (AC) Magnitude comparison (DPL) (DPL) (AC, (HL), (AC, (HL), (HL), (i8)] (HL) (AC) (HL) (AC)
Compare with immediate data
Compare contents with immediate data. identical clear not. Compare corresponding bits specified (HL). identical clear not.
Compare with data
[Load store instructions] LADR Load from (HL) Load with immediate data Load from direct Store Store (HL) Load contents (HL) into Load immediate data into Load contents (i8) into Store contents into (HL). Store contents into (HL). Load contents (reg) into either depending vertical skip function
Load from (reg)
(reg)]
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Instruction code Mnemonic [Load store instructions] Load contents (reg) into (The either XY.) Then increment contents either DPY. relationship between same that instruction. Load contents (reg) into (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (reg) either depending according result incrementing DPY. Number bytes Number cycles Affected status bits
Operation
Description
Note
reg,
Load from (reg) then increment
(reg)] (DPL) (DPY)
Load from (reg) reg, then decrement
(reg)] (DPL) (DPY)
according result decrementing DPY.
Exchange with (reg)
(AC) (reg)]
Exchange with reg, (reg) then increment
(AC) (reg)] (DPL) (DPY)
Exchange contents (reg) (The either XY.) Then increment contents either DPY. relationship between same that instruction. Exchange contents (reg) (The either XY.) Then decrement contents either DPY. relationship between same that instruction. Exchange contents (i8). Load immediate data into Load into data location determined replacing lower bits with Output from ports data location determined replacing lower bits with
according result incrementing DPY.
Exchange with reg, (reg) then decrement
(AC) (reg)] (DPL) (DPY)
according result decrementing DPY.
XADR LEAI
Exchange with direct Load with immediate data
(AC) (i8)] [ROM (PCh, AC)]
RTBL
Read table data from program
RTBLP
Read table data from program then output
Port [ROM (PCh, AC)]
[Data pointer manipulation instructions] Load with zero with immediate data respectively Load with immediate data Load with immediate data Load DPH, with immediate data Load DPX, with immediate data Load zero into immediate data into DPL. Load immediate data into DPH. Load immediate data into DPL. Load immediate data into DLH, DPL. Load immediate data into DLX, DPY.
LHLI LXYI
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Instruction code Mnemonic [Data pointer manipulation instructions] Increment Decrement Increment Decrement Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with Transfer Transfer Exchange with (DPL) (DPL) (DPY) (DPY) (AC) (DPH) (AC) (DPH) (AC) (DPL) (AC) (DPL) (AC) (DPX) (AC) (DPX) (AC) (DPY) (AC) (DPY) Increment contents DPL. Decrement contents DPL. Increment contents DPY. Decrement contents DPY. Transfer contents DPH. Transfer contents Exchange contents DPH. Transfer contents DPL. Transfer contents Exchange contents DPL. Transfer contents DPX. Transfer contents Exchange contents DPX. Transfer contents DPY. Transfer contents Exchange contents DPY. flag specified Reset flag specified Number bytes Number cycles Affected status bits
Operation
Description
Note
[Flag manipulation instructions] flag Reset flag
[Jump subroutine instructions] PC13, PC13, PC11 PC13 PC13 (E), (AC) PC13 PC10 (SP) (CF, PC13 (SP)-4 Jump location same bank specified immediate data P12. Jump location determined replacing lower bits This becomes PC12 (PC12) immediately following BANK instruction.
addr
Jump current bank
P11P10P9
JPEA
Jump address stored current page
addr
Call subroutine
Call subroutine.
addr
Call subroutine zero page
PC13 PC10 Call subroutine page (SP) bank (CF, PC12 SP-4 Change memory bank register bank.
BANK
Change bank
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Instruction code Mnemonic [Jump subroutine instructions] Store contents (SP). Subtract from after store. PUSH Push (SP) (SP) (reg) (SP) Illegal value Number bytes Number cycles Affected status bits
Operation
Description
Note
(SP)
(SP) (SP)]
then load contents M2(SP) into reg. relation between i1i0 same that PUSH instruction. Return from subroutine interrupt handling routine. restored. Return from subroutine interrupt handling routine. restored.
Return from subroutine Return from interrupt routine
(SP) (SP)] (SP) (SP)] (SP)] (AC, (AC, (HL),t2] (HL),t2]
[Branch instructions] BAt2 addr Branch location same page specified specified immediate data one. Branch location same page specified specified immediate data zero. Branch location same page specified (HL) specified immediate data one. Branch location same page specified (HL) specified immediate data zero. Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out. Internal control registers also tested executing this instruction immediately after BANK instruction. However, this limited registers that read out.
Branch
BNAt2 addr
Branch
BMt2 addr
Branch
BNMt2 addr
Branch
BPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data one.
BNPt2 addr
Branch Port
(DPL),
Branch location same page specified port (DPL) specified immediate data zero.
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Instruction code Mnemonic [Branch instructions] (CF) (CF) (ZF) (ZF) (Fn) (Fn) Branch location same page specified one. Branch location same page specified zero. Branch location same page specified one. Branch location same page specified zero. Branch location same page specified flag user flags) specified one. Branch location same page specified flag user flags) specified zero. Number bytes Number cycles Affected status bits
Operation
Description
Note
addr
Branch
addr
Branch
addr
Branch
addr
Branch
BFn4 addr
Branch flag
BNFn4 addr
Branch flag
[I/O instructions] IPDR Input port Input port Input port Input port direct Input port respectively Output port Output port Output port direct Output port respectively (P0) (DPL)] (HL) (DPL)] (i4)] (4)] (5)] (DPL) (AC) (DPL) (HL)] (i4) (AC) (AC) (DPL), Input contents port Input contents port (DPL) Input contents port (DPL) (HL). Input contents (i4) Input contents ports respectively. Output contents port (DPL). Output contents (HL) port (DPL). Output contents (i4). Output contents ports respectively. port (DPL) specified immediate data Clear zero port (DPL) specified immediate data
IP45
OPDR
OP45
port
Reset port
(DPL), P0)] P0)]
port with ANDPDR immediate data then output port with immediate data then output
Take logical immediate data output result P0). Take logical immediate data output result P0).
ORPDR
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Instruction code Mnemonic [Timer control instructions] WTTM0 Write timer Write contents (HL), TIMER0 (HL)], into timer reload (AC) register. Write contents TIMER1 (E), (AC) into timer reload register (HL), (TIMER0) (TIMER1) Start timer counter Start timer counter Stop timer counter Stop timer counter Read contents timer counter into (HL), Read contents timer counter into Start timer counter. Start timer counter. Stop timer counter. Stop timer counter. Number bytes Number cycles Affected status bits
Operation
Description
Note
WTTM1
Write timer
RTIM0
Read timer
RTIM1
Read timer
START0 Start timer START1 Start timer STOP0 STOP1 Stop timer Stop timer
[Interrupt control instructions] MSET MRESET WTSP interrupt master enable flag Reset interrupt master enable flag Enable interrupt high Enable interrupt Disable interrupt high Disable interrupt Write Read EDIH (EDIH) EDIL (EDIL) EDIH (EDIH) EDIL (EDIL) (E), (AC) (SP) interrupt master enable flag one. Clear interrupt master enable flag zero. interrupt enable flag one. interrupt enable flag one. Clear interrupt enable flag zero. Clear interrupt enable flag zero. Transfer contents Transfer contents
[Standby control instructions] HALT HOLD HALT HOLD HALT HOLD Enter halt mode. Enter hold mode.
[Serial control instructions] STARTS Start serial WTSIO RSIO Write serial Read serial START (E), (AC) (SIO) Start operation. Write contents SIO. Read contents into
[Other instructions] operation operation PC13, PC12 Consume machine cycle without performing operation. Specify memory bank.
Select bank
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products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information February, 1997. Specifications information herein subject change without notice. 5487-27/27

LC66P2316 Four-Bit Single-Chip Microcontroller with On-Chip PROM

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