KS8995X Integrated 5-Port 10/100 Switch Rev. 1.13 General De

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KS8995X
KS8995X
Integrated 5-Port 10/100 Switch Rev. 1.13
General Description
KS8995X highly integrated Layer-2 (Quality Service) switch with optimized (Bill Materials) cost port count, cost-sensitive 10/100Mbps switch systems. also provides extensive feature including three different priority schemes, dual interface cost reduction, rate limiting offload tasks, software hardware power-down, MDC/MDIO control interface port mirroring/monitoring effectively address both current emerging Fast Ethernet applications. KS8995X contains five 10/100 transceivers with patented mixed-signal low-power technology, five (Media Access Control) units, high-speed non-blocking switch fabric, dedicated address lookup engine, on-chip frame buffer memory. units support 10BaseT 100BaseTX. addition, units support 100BaseFX (Ports support documentation found Micrel's site www.micrel.com.
Features
Integrated switch with five MACs five Fast Ethernet transceivers fully compliant IEEE 802.3u standard Shared memory based switch fabric with fully nonblocking configuration 10BaseT, 100BaseTX 100BaseFX modes Ports Dual configuration: MII-Switch (MAC mode MII) MII-P5 (PHY mode MII) VLAN tag/untag options, per-port basis Enable/disable option huge frame size 1916 bytes frame Broadcast storm protection with percent control global per-port basis Optimization fiber-to-copper media conversion Full-chip hardware power-down support (register configuration saved) Per-port-based software power-save (idle link detection, register configuration preserved) QoS/CoS packets prioritization supports: port, 802.1p DiffServ based
Functional Diagram
Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX Auto MDI/MDIX MII-P5 MDC, MDI/O MII-SW LED0[5:1] LED1[5:1] LED2[5:1]
10/100 T/Tx 10/100 T/Tx 10/100 T/Tx 10/100 T/Tx/Fx 10/100 T/Tx/Fx
10/100
FIFO, Flow Control, VLAN Tagging, Priority
look-up Engine Queue Mgmnt Buffer Mgmnt Frame Buffers
10/100 10/100 10/100 10/100
Control Registers
EEPROM
Micrel, Inc. 1849 Fortune Drive Jose, 95131 (408) 944-0800 (408) 944-0970 http://www.micrel.com
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Features (continued)
802.1p/q insertion removal per-port basis (egress) Port-based VLAN support MDI/O interface support access control registers (not control registers) local loopback support On-chip 64Kbyte memory frame buffering (not shared with unicast address table) 1.4Gbps high-performance memory bandwidth Wire-speed reception transmission Integrated look-up engine with dedicated unicast addresses Automatic address learning, address aging address migration Full-duplex IEEE 802.3x half-duplex back pressure flow control Comprehensive support 7-wire support legacy interface Automatic MDI/MDI-X crossover plug-and-play Disable automatic MDI/MDIX option power Core: 1.8V I/O: 3.3V 0.18µm CMOS technology Commercial temperature range: +70°C Available 128-pin PQFP package
Applications
Broadband gateway/firewall/VPN Integrated cable modem multi-port router Wireless access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Media converter
Ordering Information
Part Number Temperature Range Package KS8995X KSZ8995X +70°C +70°C 128-Pin PQFP 128-Pin PQFP Lead Free
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Revision History
Revision 1.08 1.09 Date 4/01/02 5/20/02 Summary Changes Created. Changed setting descriptions. Changed pu/pd descriptions SMRXD2. Changed pu/pd description forced flow control. Edited large packet sizes back also "Register Added typical supply current numbers 100BaseTX 10BaseTX operation. Added note illegal half-duplex, force flow control. Added extra clock input description. Updated chip only current numbers. "Register "Pin Description" PMRXER correction. Changed SMRXC SMTXC I/O. Input mode, output mode MII. Changed polarity pins. "Electrical Characteristics" modified current consumption chip only numbers. Added description dropped packets half duplex mode. Added recommended operating conditions. Added Idle mode current consumption. Added "Selection Isolation Transformers." Added 3.01k resistor instructions ISET "Pin Description." Changed Polarity transmit pairs "Pin Description." Changed description register "Register Description." Added "Reset Tming." Added "QoS Description." "Register changed 802.1x 802.3x. "Register changed default column disable flow control pull-down, enable flow control pull "Register "MIIM Register indicate loop back Removed caption under table "Register 18." Changed definition MDI/MDIX "Register 29," "Register 30," "MIIM Register Refer 8995XA data sheet. Convert format.
1.10
10/9/02
1.11 1.12 1.13
10/24/02 5/20/03 8/29/03
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Table Contents
System Level Applications Description Number) Description Name) Configuration Introduction Functional Overview: Physical Layer Transceiver 100BaseTX Transmit 100BaseTX Receive Clock Synthesizer Scrambler/De-scrambler (100BaseTX only) 100BaseFX Operation 100BaseFX Signal Detection 100BaseFX Fault 10BaseT Transmit 10BaseT Receive Power Management MDI/MDI-X Auto Crossover Auto-Negotiation Functional Overview: Switch Core Address Look Learning Migration Aging
Switching Engine (Media Access Controller) Operation Inter-Packet Backoff Algorithm Late Collision Illegal Frame Flow Control Half-Duplex Back Pressure Broadcast Storm Protection Interface Operation Interface Operation Advanced Functionality Support Rate Limit Support Configuration Interface Master Serial Configuration Management Interface (MIIM) Register Global Registers Register (0x00): Chip Register (0x01): Chip ID1/Start Switch Register (0x02): Global Control Register (0x03): Global Control Register (0x04): Global Control Register (0x05): Global Control Register (0x06): Global Control Register (0x07): Global Control M9999-120403
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Register (0x08): Global Control Register (0x09): Global Control Register (0x0A): Global Control Register (0x0B): Global Control
Port Registers Register (0x10): Port Control Register (0x11): Port Control Register (0x12): Port Control Register (0x13): Port Control Register (0x14): Port Control Register (0x15): Port Control Register (0x16): Port Control Register (0x17): Port Control Register (0x18): Port Control Register (0x19): Port Control Register (0x1A): Port Control Register (0x1B): Port Control Register (0x1C): Port Control Register (0x1D): Port Control Register (0x1E): Port Status Register (0x1F): Port Status Advanced Control Registers Register (0x60): Priority Control Register Register (0x61): Priority Control Register Register (0x62): Priority Control Register Register (0x63): Priority Control Register Register (0x64): Priority Control Register Register (0x65): Priority Control Register Register (0x66): Priority Control Register Register (0x67): Priority Control Register Register (0x68): Address Register Register (0x69): Address Register Register (0x6A): Address Register Register (0x6B): Address Register Register (0x6C): Address Register Register (0X6D): Address Register MIIM Registers Register Control Register Status Register PHYID HIGH Register PHYID Register Advertisement Ability Register Link Partner Ability Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams Selection Isolation Transformers Package Information
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System Level Applications
10/100
Switch Controller On-Chip Frame Buffers
10/100 10/100 10/100 10/100 10/10
EEPROM 1-port EEPROM 4-port
10/100 10/100 10/100 10/100
Ethernet Ethernet
MII-SW
MII-P5
KS8995X
External port needed
Figure Broadband Gateway
Switch Controller On-Chip Frame Buffers
10/100 10/100 10/100 10/100 10/100
10/100 10/100 10/100 10/100 10/100
EEPROM EEPROM 4-port
(XDSL, CM.)
Ethernet MII-SW
MII-P5
KS8995X
Figure Integrated Broadband Router
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10/100
Switch Controller On-Chip Frame Buffers
10/100
10/100 10/100 10/100
5-port
10/100 10/100 10/100 10/100
10/100
EEPROM
EEPROM
KS8995X
Figure Standalone Switch
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Description Number)
Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name TEST1 GNDA VDDAR RXP1 RXM1 GNDA TXM1 TXP1 VDDAT RXP2 RXM2 GNDA TXM2 TXP2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXM3 TXP3 VDDAT RXP4 RXM4 GNDA TXM4 TXP4 GNDA
Type(1)
Port
Function normal operation. Factory test pin. Analog ground 1.8V analog
Physical receive signal (differential) Physical receive signal (differential) Analog ground
Physical transmit signal (differential) Physical transmit signal (differential) 2.5V analog
Physical receive signal (differential) Physical receive signal (differential) Analog ground
Physical transmit signal (differential) Physical transmit signal (differential) 1.8V analog Analog ground physical transmit output current. Pull-down with 3.01k resistor.
2.5V analog Physical receive signal (differential) Physical receive signal (differential) Analog ground Physical transmit signal (differential) Physical transmit signal (differential) 2.5V analog Physical receive signal (differential) Physical receive signal (differential) Analog ground Physical transmit signal (differential) Physical transmit signal (differential) Analog ground
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Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name VDDAR RXP5 RXM5 GNDA TXM5 TXP5 VDDAT FXSD5 FXSD4 GNDA VDDAR GNDA VDDAR GNDA MUX1 MUX2 PWRDN_N RESERVE/NC GNDD VDDC PMTXEN PMTXD3 PMTXD2 PMTXD1 PMTXD0 PMTXER PMTXC GNDD VDDIO PMRXC PMRXDV PMRXD3 Ipd/O Ipd/O Type(1) Port Function 1.8V analog Physical receive signal (differential) Physical receive signal (differential) Analog ground Physical transmit signal (differential) Physical transmit signal (differential) 2.5V analog Fiber signal detect/factory test Fiber signal detect/factory test Analog ground 1.8V analog Analog ground 1.8V analog Analog ground connect. Factory test pin. connect. Factory test pin. Full-chip power down. Active low. Reserved pin. connect. Digital ground 1.8V digital core PHY[5] transmit enable PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit error PHY[5] transmit clock. mode MII. Digital ground 3.3/2.5V digital digital circuitry PHY[5] receive clock. mode MII. PHY[5] receive data valid PHY[5] receive Strap option: (default) enable flow control; disable flow control.
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Number Name PMRXD2 PMRXD1 PMRXD0 Type(1) Ipd/O Ipd/O Ipd/O Port Function PHY[5] receive Strap option: (default) disable back pressure; enable back pressure.
PHY[5] receive Strap option: (default) drop excessive collision packets; does drop excessive collision packets. PHY[5] receive Strap option: (default) disable aggressive back-off algorithm half-duplex mode; enable performance enhancement. PHY[5] receive error. Strap option: (default) packet size 1518/1522 bytes; 1536 bytes. PHY[5] carrier sense/force duplex mode. "Register 28." PHY[5] collision detect/force flow control. "Register 18." Switch transmit enable Switch transmit Switch transmit Switch transmit Switch transmit Switch transmit error Switch transmit clock. mode MII. Digital ground 3.3/2.5V digital digital circuitry. Switch receive clock. mode MII. Switch receive data valid Switch receive Strap option: (default) Disable Switch full-duplex flow control; Enable Switch full-duplex flow control. Switch receive Strap option: (default) Switch full-duplex mode; Switch half-duplex mode. Switch receive Strap option: (default) Switch 100Mbps mode; Switch 10Mbps mode. Switch receive Strap option: "Register 11[1]." Switch collision detect Switch mode carrier sense
Note: Power supply Input Output Bi-directional Ground
PMRXER PCRS PCOL SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC GNDD VDDIO SMRXC SMRXDV SMRXD3 SMRXD2 SMRXD1 SMRXD0 SCOL SCRS
Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O
Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
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Number Name SCONF1 Type(1) Port Function Dual configuration pin. Pin# (91, 87):
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Switch Disable, Otri Mode Mode Mode Disable Mode Mode Mode
Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable Mode Mode Mode
SCONF0 GNDD VDDC LED5-2 LED5-1 LED5-0 LED4-2 LED4-1 LED4-0 LED3-2 LED3-1 LED3-0 GNDD VDDIO LED2-2 LED2-1 LED2-0 LED1-2 LED1-1 LED1-0 MDIO
Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O
Dual configuration pin. Digital ground 1.8V digital core indicator Aging setup. "Aging" section. indicator Strap option: (default): enable tristate output. "pin# SCONF1." indicator indicator indicator indicator indicator indicator indicator Digital ground 3.3/2.5V digital digital I/O. indicator indicator indicator indicator indicator indicator Switch PHY[5] management data clock. Switch PHY[5] management data I/O.
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Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name Reserved Reserved RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2 Type(1) Port Function connect Output clock 81KHz master mode. Serial data input/output master mode. connect connect pull-down. connect pull-down. Reset KS8995X. Active low. Digital ground 1.8V digital core Factory test pin. Factory test pin. connection 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should ±100ppm. 25MHz crystal clock connection. 1.8V analog Analog ground 1.8V analog Analog ground Analog ground Factory test
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Description Name)
Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name FXSD4 FXSD5 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDD GNDD GNDD GNDD GNDD GNDD ISET LED1-0 LED1-1 LED1-2 LED2-0 LED2-1 LED2-2 LED3-0
Type(1)
Port
Function Fiber signal detect/factory test pin. Fiber signal detect/factory test pin. Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground Analog ground connection Analog ground Analog ground Analog ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground physical transmit output current. Pull down with 3.01k resistor.
Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O
indicator indicator indicator indicator indicator indicator indicator
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Number Name LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 MDIO MUX1 MUX2 PCOL PCRS PMRXC PMRXD0 Ipd/O Ipd/O Ipd/O Type(1) Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Ipu/O Port Function indicator indicator indicator indicator indicator indicator
indicator Strap option: (default): enable I/F. tristate output. "pin# SCONF1." indicator Aging setup. "Aging" section. Switch PHY[5] management data clock. Switch PHY[5] management data I/O. connect. Factory test pin. connect. Factory test pin. PHY[5] collision detect/ Force flow control. "Register 18." PHY[5] carrier sense/Force duplex mode. "Register 28." PHY[5] receive clock. mode MII. PHY[5] receive Strap option: (default) disable aggressive back-off algorithm half-duplex mode; enable performance enhancement. PHY[5] receive Strap option: (default) drop excessive collision packets; does drop excessive collision packets. PHY[5] receive Strap option: (default) disable back pressure; enable back pressure. PHY[5] receive Strap option: (default) enable flow control; disable flow control. PHY[5] receive data valid. PHY[5] receive error. Strap option: (default) packet size 1518/ 1522 bytes; 1536 bytes. PHY[5] transmit clock. mode MII. PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit PHY[5] transmit enable PHY[5] transmit error
Note: Power supply Input Output Bi-directional Ground
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXER PMTXC PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN PMTXER
Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O
Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
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Number Name PWRDN_N RESERVE/NC Reserved Reserved RST_N RXM1 RXM2 RXM3 RXM4 RXM5 RXP1 RXP2 RXP3 RXP4 RXP5 SCANEN SCOL SCONF0 SCONF1 Ipd/O Type(1) Port Function connect pull down connect pull down Full-chip power down. Active low. Reserved pin. connect. connect connect Reset KS8995X. Active low. Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Physical receive signal (differential) Factory test Output clock 81KHz master mode. "pin# 113." Switch collision detect Dual configuration Dual configuration Pin# (91, 87):
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Switch Disable, Otri Mode Mode Mode Disable Mode Mode Mode
Disable, Otri Disable, Otri Disable, Otri Disable, Otri Disable Mode Mode Mode
SCRS
Ipd/O
Switch carrier sense
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Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name SMRXC SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMTXC SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN SMTXER TEST1 TEST2 TESTEN TXP1 TXP2 TXP3 TXP4 TXP5 TXM1 TXM2 TXM3 TXM4 TXM5 VDDAP VDDAR VDDAR VDDAR Type(1) Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Port Function Serial data input/output master mode. "pin# 113." Switch receive clock. mode Switch receive Strap option: "Register 11[1]." Switch receive Strap option: (default) Switch 100Mbps mode; Switch 10Mbps mode. Switch receive Strap option: (default) Switch full duplex mode; Switch half-duplex mode. Switch receive Strap option: (default) Disable Switch full-duplex flow control; Enable Switch full-duplex flow control. Switch receive data valid Switch transmit clock. mode MII. Switch transmit Switch transmit Switch transmit Switch transmit Switch transmit enable Switch transmit error normal operation. Factory test pin. Factory test Factory test Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) Physical transmit signal (differential) 1.8V analog 1.8V analog 1.8V analog 1.8V analog
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Number
Note: Power supply Input Output Bi-directional Ground Input w/internal pull-up Input w/internal pull-down Ipd/O Input w/internal pull-down during reset, output otherwise Ipu/O Input w/internal pull-up during reset, output otherwise Strap pull-up Strap pull-down Otri Output tristated
Name VDDAR VDDAR VDDAR VDDAT VDDAT VDDAT VDDAT VDDC VDDC VDDC VDDIO VDDIO VDDIO Type(1) Port Function 1.8V analog 1.8V analog 1.8V analog 2.5V analog 2.5V analog 2.5V analog 2.5V analog 1.8V digital core 1.8V digital core 1.8V digital core 3.3/2.5V digital digital circuitry 3.3/2.5V digital digital circuitry 3.3/2.5V digital digital circuitry 25MHz crystal clock connection/or 3.3V tolerant oscillator input. Oscillator should ±100ppm. 25MHz crystal clock connection
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LED2-0 LED1-2 LED1-1 LED1-0 MDIO SPIQ SPIC/SCL SPID/SDA SPIS_N RST_N GNDD VDDC TESTEN SCANEN VDDAP GNDA VDDAR GNDA GNDA TEST2
Configuration
128-Pin PQFP (PQ)
TEST1 GNDA VDDAR RXP1 RXM1 GNDA TXM1 TXP1 VDDAT RXP2 RXM2 GNDA TXM2 TXP2 VDDAR GNDA ISET VDDAT RXP3 RXM3 GNDA TXM3 TXP3 VDDAT RXP4 RXM4 GNDA TXM4 TXP4 GNDA VDDAR RXP5 RXM5 GNDA TXM5 TXP5 VDDAT FXSD5
LED2-1 LED2-2 VDDIO GNDD LED3-0 LED3-1 LED3-2 LED4-0 LED4-1 LED4-2 LED5-0 LED5-1 LED5-2 VDDC GNDD SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC VDDIO GNDD SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTEXN PCOL PCRS PMRXER PMRXD0
PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4
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Introduction
KS8995X contains five 10/100 physical layer transceivers five (Media Access Control) units with integrated layer switch. device runs three modes. first mode five-port integrated switch. second five-port switch with fifth port decoupled from physical port. this mode access fifth provided through (Media Independent Interface). This useful implementing integrated broadband router. third mode uses dual feature recover fifth PHY. This allows additional broadband gateway configuration, where fifth accessed through MII-P5 port. KS8995X optimized unmanaged design which configuration achieved through strapping EEPROM programming system reset time. media side, KS8995X supports IEEE 802.3 10BaseT, 100BaseTX ports, 100BaseFX ports KS8995X used separate media converters. Physical signal transmission reception enhanced through patented analog circuitry that makes design more efficient allows lower power consumption smaller chip size. major enhancements from KS8995E KS8995X support programmable rate limiting, dual interface, MDC/MDIO control interface IEEE 802.3-defined register configuration (not registers), per-port broadcast storm protection, local loopback lower power consumption. KS8995X pin-compatible managed switch, KS8995M.
Functional Overview: Physical Layer Transceiver
100BaseTX Transmit
100BaseTX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding transmission. circuit starts with parallel-to-serial conversion, which converts data from into 125MHz serial stream. data control stream then converted into 4B/5B coding followed scrambler. serialized data further converted from NRZI format, then transmitted MLT3 current output. output current external 3.01k resistor transformer ratio. typical rise/fall time complies with ANSI TP-PMD standard regarding amplitude balance, overshoot timing jitter. wave-shaped 10BaseT output also incorporated into 100BaseTX transmitter.
100BaseTX Receive
100BaseTX receiver function performs adaptive equalization, restoration, MLT3-to-NRZI conversion, data clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding serial-to-parallel conversion. receiving side starts with equalization filter compensate inter-symbol interference (ISI) over twisted pair cable. Since amplitude loss phase distortion function length cable, equalizer adjust characteristics optimize performance. this design, variable equalizer will make initial estimation based comparisons incoming signal strength against some known cable characteristics, then tunes itself optimization. This ongoing process self adjust against environmental changes such temperature variations. equalized signal then goes through restoration data conversion block. restoration circuit used compensate effect baseline wander improve dynamic range. differential data conversion circuit converts MLT3 format back NRZI. slicing threshold also adaptive. clock recovery circuit extracts 125MHz clock from edges NRZI signal. This recovered clock then used convert NRZI signal into format. signal then sent through de-scrambler followed 4B/5B decoder. Finally, serial data converted format provided input data MAC.
Clock Synthesizer
KS8995X generates 125MHz, 42MHz, 25MHz 10MHz clocks system timing. Internal clocks generated from external 25MHz crystal.
Scrambler/De-Scrambler (100BaseTX only)
purpose scrambler spread power spectrum signal order reduce baseline wander. data scrambled through 11-bit wide linear feedback shift register (LFSR). This generate 2047-bit nonrepetitive sequence. receiver will then de-scramble incoming data stream with same sequence transmitter.
100BaseFX Operation
100BaseFX operation very similar 100BaseTX operation except that scrambler/de-scrambler MLT3 encoder/ decoder bypassed transmission reception. this mode auto-negotiation feature bypassed since there standard that supports fiber auto-negotiation.
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100BaseFX Signal Detection
physical port runs 100BaseFX mode FXSDx >0.6V ports only. This signal internally referenced 1.25V.The fiber module interface should voltage divider such that FXSDx above this 1.25V reference, indicating signal detect, FXSDx below 1.25V reference indicate signal. When FXSDx below 0.6V then 100BaseFX mode disabled.
100BaseFX Fault
fault occurs when signal detection logically false from receive fiber module. When this occurs, transmission side signals other link sending followed zero idle period between frames. fault disabled through register settings.
10BaseT Transmit
output 10BaseT driver incorporated into 100BaseT driver allow transmission with same magnetics. They internally wave-shaped pre-emphasized into outputs with typical 2.3V amplitude. harmonic contents least 27dB below fundamental when driven all-ones Manchester-encoded signal.
10BaseT Receive
receive side, input buffer level detecting squelch circuits employed. differential input receiver circuit perform decoding function. Manchester-encoded data stream separated into clock signal data. squelch circuit rejects signals with levels less than 400mV with short pulsewidths order prevent noises input from falsely triggering decoder. When input exceeds squelch limit, locks onto incoming signal KS8995X decodes data frame. receiver clock maintained active during idle periods between data reception.
Power Management
KS8995X features port power down mode. save power user power down ports that setting port control registers control registers. addition, also supports full chip power down mode. When activated, entire chip will shutdown.
MDI/MDI-X Auto Crossover
KS8995X supports MDI/MDI-X auto crossover. This facilitates either straight connection CAT-5 cable crossover CAT-5 cable. auto-sense function will detect remote transmit receive pairs, correctly assign transmit receive pairs from Micrel device. This highly useful when users unaware cable types also save additional uplink configuration connection. auto crossover feature disabled through port control registers.
Auto-Negotiation
KS8995X conforms auto-negotiation protocol described 802.3 committee. Auto-negotiation allows (Unshielded Twisted Pair) link partners select best common mode operation. auto-negotiation link partners advertise capabilities across link each other. auto-negotiation supported link partner KS8995X forced bypass auto-negotiation, then mode observing signal receiver. This known parallel mode because while transmitter sending auto-negotiation advertisements, receiver listening advertisements fixed signal protocol. flow link depicted Figure
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Start Auto Negotiation
Force Link Setting
Parallel Operation
Bypass Auto-Negotiation Link Mode
Attempt Auto-Negotiation
Listen 100BaseTX Idles
Listen 10BaseT Link Pulses
Join Flow
Link Mode
Link Mode
Figure Auto-Negotiation
Functional Overview: Switch Core
Address Look-Up
internal look-up table stores addresses their associated information. contains unicast address table plus switching information. KS8995X guaranteed learn addresses distinguishes itself from hash-based look-up tables which, depending operating environment probabilities, guarantee absolute number addresses learn.
Learning
internal look-up engine will update table with entry following conditions met: received packet's (Source Address) does exist look-up table. received packet good; packet receiving errors, legal length. look-up engine will insert qualified into table, along with port number, time stamp. table full, last entry table will deleted first make room entry.
Migration
internal look-up engine also monitors whether station moved. happens, will update table accordingly. Migration happens when following conditions met: received packet's table associated source port information different. received packet good; packet receiving errors, legal length. look-up engine will update existing record table with source port information.
Aging
look-up engine will update time stamp information record whenever corresponding appears. time stamp used aging process. record updated period time, look-up engine will remove record from table. look-up engine constantly performs aging process will continuously remove aging records. aging period seconds. This feature enabled disabled through Register external pull-up pull-down resistors LED[5][2]. "Register section.
Switching Engine
KS8995X features high performance switching engine move data from MAC's, packet buffers. operates store forward mode, while efficient switching mechanism reduces overall latency. KS8995X 64kB internal frame buffer. This resource shared between five ports. buffer sharing mode programmed through register "Register mode, ports allowed free buffers buffer pool. second mode, each port only allowed total buffer pool. There total buffers available. Each buffer sized 128B.
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(Media Access Controller) Operation
KS8995X strictly abides IEEE 802.3 standards maximize compatibility.
Inter-Packet (IPG)
frame successfully transmitted, time measured between consecutive MTXEN. current packet experiencing collision, time measured from MCRS next MTXEN.
Backoff Algorithm
KS8995X implements IEEE 802.3 binary exponential back-off algorithm, optional "aggressive mode" back off. After collisions, packet will optionally dropped depending chip configuration Register "Register
Late Collision
transmit packet experiences collisions after 512-bit times transmission, packet will dropped.
Illegal Frames
KS8995X discards frames less than bytes programmed accept frames 1536 bytes Register special applications, KS8995X also programmed accept frames 1916 bytes Register Since KS8995X supports VLAN tags, maximum sizing adjusted when these tags present.
Flow Control
KS8995X supports standard 802.3x flow control frames both transmit receive sides. receive side, KS8995X receives pause control frame, KS8995X will transmit next normal frame until timer, specified pause control frame, expires. another pause frame received before current timer expires, timer will updated with value second pause frame. During this period (being flow controlled), only flow control packets from KS8995X will transmitted. transmit side, KS8995X intelligent efficient ways determine when invoke flow control. flow control based availability system resources, including available buffers, available transmit queues available receive queues. KS8995X will flow control port, which just received packet, destination port resource being used KS8995X will issue flow control frame (XOFF), containing maximum pause time defined IEEE standard 802.3x. Once resource freed KS8995X will send other flow control frame (XON) with zero pause time turn flow control (turn transmission port). hysteresis feature provided prevent flow control mechanism from being activated deactivated many times. KS8995X will flow control ports receive queue becomes full.
Half-Duplex Back Pressure
half-duplex back pressure option (note: 802.3 standards) also provided. activation deactivation conditions same above full-duplex mode. back pressure required, KS8995X will send preambles defer other stations' transmission (carrier sense deference). avoid jabber excessive deference defined 802.3 standard, after certain time will discontinue carrier sense will raise carrier sense quickly. This short silent time carrier sense) prevent other stations from sending packets keeps other stations carrier sense deferred state. port packets send during back pressure situation, carrier-sense-type back pressure will interrupted those packets will transmitted instead. there more packets send, carrier-sense-type back pressure will active again until switch resources free. collision occurs, binary exponential backoff algorithm skipped carrier sense generated immediately, reducing chance further colliding maintaining carrier sense prevent reception packets. ensure packet loss 10BaseT 100BaseTX half-duplex modes, user must enable following: Aggressive backoff (register excessive collision drop (register Back pressure (register These bits default because this IEEE standard.
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Broadcast Storm Protection
KS8995X intelligent option protect switch system from receiving many broadcast packets. Broadcast packets will forwarded ports except source port, thus many switch resources (bandwidth available space transmit queues). KS8995X option include "multicast packets" storm control. broadcast storm rate parameters programmed globally, enabled disabled port basis. rate based 50ms interval 100BT 500ms interval 10BT. beginning each interval, counter cleared zero, rate limit mechanism starts count number bytes during interval. rate definition described Register Register default setting Registers 0x4A, which decimal. This equal rate calculated follows: 148,800 frames/sec 50ms/interval frames/interval (approx.) 0x4A
Interface Operation
(Media Independent Interface) specified IEEE 802.3 committee provides common interface between physical layer layer devices. KS8995X provides such interfaces. MII-P5 interface used connect fifth PHY, whereas MII-SW interface used connect fifth MAC. Each these interfaces contains distinct groups signals, transmission other receiving. table below describes signals used MII-P5 interface. MII-P5 interface operates mode only, while MII-SW interface operates either mode mode. These interfaces nibble wide data interfaces therefore network rate (not encoded). Additional signals transmit side indicate when data valid when error occurs during transmission. Likewise, receive side indicators that convey when data valid without physical layer errors. half-duplex operation there signal that indicates collision occurred during transmission. Note that signal MRXER provided MII-SW interface mode operation signal MTXER provided MII-SW interface mode operation. Normally MRXER would indicate receive error coming from physical layer device. MTXER would indicate transmit error from device. These signals appropriate this configuration. mode operation, device interfacing with KS8995X MRXER pin, should tied low. mode operation, device interfacing with KS8995X MTXER pin, should tied low.
Signal MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC MDIO
Description Transmit enable Transmit error Transmit data Transmit data Transmit data Transmit data Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data Receive data Receive data Receive data Receive clock Management data clock Management data
KS8995X Signal PMTXEN PMTXER PMTXD[3] PMTXD[2] PMTXD[1] PMTXD[0] PMTXC PCOL PCRS PMRXDV PMRXER PMRXD[3] PMRXD[2] PMRXD[1] PMRXD[0] PMRXC MDIO
Table MII-P5 Signals (PHY Mode)
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Mode Connection External MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995X Signal SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC SCOL SCRS SMRXDV used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC Description Transmit enable Transmit error Transmit data Transmit data Transmit data Transmit data Transmit clock Collision detection Carrier sense Receive data valid Receive error Receive data Receive data Receive data Receive data Receive clock
Mode Connection External MTXEN MTXER MTXD3 MTXD2 MTXD1 MTXD0 MTXC MCOL MCRS MRXDV MRXER MRXD3 MRXD2 MRXD1 MRXD0 MRXC KS8995X Signal SMRXDV used SMRXD[3] SMRXD[2] SMRXD[1] SMRXD[0] SMRXC SCOL SCRS SMTXEN SMTXER SMTXD[3] SMTXD[2] SMTXD[1] SMTXD[0] SMTXC
Table MII-SW Signals
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Interface Operation
(Serial Network Interface) compatible with some controllers used network layer protocol processing. This interface directly connected these types devices. signals divided into groups, transmission other reception. signals involved described table below.
Signal TXEN Description Transmit Enable Serial Transmit Data Transmit Clock Collision Detection Carrier Sense Serial Receive Data Receive Clock KS8995X Signal SMTXEN SMTXD[0] SMTXC SCOL SMRXDV SMRXD[0] SMRXC
Table Signals This interface wide data interface therefore runs network rate (not encoded). additional signal transmit side indicates when data valid. Likewise, receive side indicator that conveys when data valid. half-duplex operation there signal that indicates collision occurred during transmission.
Advanced Functionality
Support
KS8995X switch, meaning that able identify selected packets ingress ports, prioritize them, service packets according their priority egress ports. this way, KS8995X provide statistically better service high priority packets that latency sensitive, require higher bandwidth. KS8995X supports ingress classification using three different mechanisms: port-based priority, 802.1p tag-based priority, DSCP priority IPv4 packets. Port-based priority useful when user wants give device given port high priority. example Figure port given high priority because connected phone port given lower priority because connected computer whose data traffic less sensitive network congestion. Each port KS8995X high priority with EEPROM. port priority registers 0x10, 0x20, 0x30, 0x40, 0x50 ports respectively. Port-based priority overridden OR'ed result 802.1p DSCP priorities they enabled same time.
Router P5[0]=1, Hi/Lo Priority Queues enabled
Hi-Pri Queue
Lo-Pri
Queue
8995X
P1[3]=1 High Priority Port
Phone
P4[3]=0 Priority Port
Figure Port-Based Priority
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KS8995X classify tagged packets using 802.1p based priority. this prioritization scheme, user enable 802.1p classification port basis registers 0x10, 0x20, 0x30, 0x40 0x50 ports respectively. Then user specifies 802.1p base priority register 0x02, bits [6-4]. When tagged packet received, KS8995X examines 802.1p priority field shown Figure These bits compared against base priority. prioritization policy follows:
Comparison 802.1p Priority Base Priority 802.1p Priority Base Priority Priority High
Table 802.1p Priority
Bytes
Preamble
Length
46-1500 Data
Bits
Tagged Packet Type (8100 Ethernet)
802.1p
VLAN
Figure 802.3 Tagged Packet
Bytes Preamble Type Data 46-1500
Bits
Ver.
Header Size DiffServ
Res.
Figure IPv4 Packet order support from end-to-end network, KS8995X also classify packets based IPv4 DiffServ field shown Figure DiffServ field consists bits, which used specify code points. KS8995X provides bits (DSCP[63:0]) registers (0x60 0x67), which user specifies priority each code points. DiffServ classification enabled port basis registers 0x10, 0x20, 0x30, 0x40 0x50 ports respectively. DiffServ classification enabled port, KS8995X will decode IPv4 DiffServ field look user defined code point determine packet high priority priority. code point `1', packet high priority. code point `0', packet priority.
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DiffServ Field (Binary) 000000 000001 000010 000011 000100 Code Point DSCP[0] DSCP[1] DSCP[2] DSCP[3] DSCP[4] KS8995X (Reg. Bit) 0x67, 0x67, 0x67, 0x67, 0x67,
111011 111100 111101 111110 111111
DSCP[59] DSCP[60] DSCP[61] DSCP[62] DSCP[63]
0x60, 0x60, 0x60, 0x60, 0x60,
Table DiffServ Code Point Once classification packets been determined either port-based priority, 802.1p tag-based priority DiffServ priority, they placed either high priority queue egress port. user enable egress priority queues port basis setting registers 0x10, 0x20, 0x30, 0x40, 0x50 ports respectively. egress priority queue given port set, port will treat packets they same priority, even though packets classified their ingress ports. egress priority queue given port enabled, packets serviced based user programmable egress policy. priority scheme selection register 0x05 bits[3-2] shown Table
Register 0x05, Register 0x05,
Egress Priority Scheme Always deliver high priority packets first Deliver high/low priority packets ratio 10/1 Deliver high/low priority packets ratio Deliver high/low priority packets ratio
Table Transmit Priority Ratio KS8995X offers support port-based, 802.1p tag-based, IPv4 DiffServ priority, well programmable egress policies. These KS8995X features enable identifying, classifying forwarding packets based their priority. system designer able this device build network elements that give more control over system resources, priority service mission critical applications, integrated into next generation multimedia networks.
Rate Limit Support
KS8995X supports hardware rate limiting "receive" "transmit" independently port basis. also supports rate limiting priority non-priority environment. rate limit starts from 0Kbps goes line rate steps 32Kbps. KS8995X uses second interval. beginning each interval, counter cleared zero, rate limit mechanism starts count number bytes during this interval. receive, number bytes exceeds programmed limit, switch will stop receiving packets port until "one second" interval expires. There option provided flow control prevent packet loss. rate limit programmed greater than equal 128Kbps byte counter bytes below limit, flow control will triggered. rate limit programmed lower than 128Kbps byte counter bytes below limit, flow control will triggered. transmit, number bytes exceeds programmed limit, switch will stop transmitting packets port until "one second" interval expires. priority enabled, KS8995X support different rate controls both high priority priority packets. This programmed through registers
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Configuration Interface
KS8995X functions unmanaged switch. EEPROM exists, KS8995X will operate from default strapin settings.
Master Serial Configuration
2-wire EEPROM exists, KS8995X perform more advanced features like broadcast storm protection rate control. EEPROM should have entire valid configuration data from register register defined memory map, except status registers. configuration access time (tprgm) less than 15ms shown Figure
RST_N
prgm<15
Figure EEPROM Configuration Timing Diagram configure KS8995X with pre-configured EEPROM following steps: board level, connect KS8995X EEPROM. Connect KS8995X EEPROM. sure board level reset signal connected KS8995X reset signal (RST_N). Program contents EEPROM before placing board with desired configuration data. Note that first byte EEPROM must "95" loading occur properly. this value correct, other data will ignored. Place EEPROM board power board. Assert active-low board level reset RST_N KS8995X. After reset deasserted, KS8995X will begin reading configuration data from EEPROM. configuration access time (tprgm) less than 15ms. Note: proper operation, make sure (PWRDN_N) asserted during reset operation.
Management Interface (MIIM)
standard MIIM interface provided five devices KS8995X. external device with MDC/MDIO capability able read status configure settings. details MIIM interface standard please reference IEEE 802.3 specification (section 22.2.4.5). MIIM interface does have access configuration registers KS8995X. only access standard registers. "MIIM Registers" section.
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Register
Offset Decimal 2-11 12-15 16-29 30-31 32-45 46-47 48-61 62-63 64-77 78-79 80-93 94-95 96-103 104-109 0x00-0x01 0x02-0x0B 0x0C-0x0F 0x10-0x1D 0x1E-0x2F 0x20-0x2D 0x2E-0x2F 0x30-0x3D 0x3E-0x3F 0x40-0x4D 0x4E-0x4F 0x50-0x5D 0x5E-0x5F 0x60-0x67 0x68-0x6D Description Chip Registers Global Control Registers Reserved Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Port Control Registers Port Status Registers Priority Control Registers Address Registers
Global Registers
Address Name Description Mode Default Register (0x00): Chip Family Chip family 0x95
Register (0x01): Chip ID1/Start Switch Chip Revision Start switch assigned series. (95X) Revision chip starts automatically after trying read external EEPROM. EEPROM does exist, chip will default values internal registers. EEPROM present, contents EEPROM will checked. switch will check: Register 0x95, Register [7:4] 0x0. this check contents EEPROM will override chip register default values.
Register (0x02): Global Control Reserved 802.1p base priority Reserved Used classify priority incoming 802.1q packets. "User priority" compared against this value. classified high priority classified priority enable interface (note: enabled, switch will tri-state outputs)
Enable
LED[5][1] strap option. Pull-down (0): isolate Pull-up (1): Enable. Note: LED[5][1] internal pull-up.
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Address Name Description Mode Default
Register (0x02): Global Control (continued) Buffer share mode buffer pool shared ports. port more buffer when other ports busy. port only allowed buffer pool. switch will drop packets with 0x8808 filed, DA=01-80-C2-00-00-01. switch will drop packets qualified "flow control" packets. link change from "link" link" will cause fast aging (<800µs) address table faster. After cycle complete, logic will return normal (300 seconds). Note: port unplugged, addresses will automatically aged out.
mode
Link change
Register (0x03): Global Control Pass frames switch packets including ones. Used solely debugging purpose. Works conjunction with sniffer mode. Reserved will enable transmit flow control based result. will enable transmit flow control regardless result.
Reserved IEEE 802.3x transmit flow control disable
PMRXD3 strap option. Pull-down (0): Enable flow control. Pull-up (1): Disable tx/rx flow control. Note: PMRXD3 internal pulldown. PMRXD3 strap option. Pull-down (0): Enable flow control. Pull-up (1): Disable tx/rx flow control. Note: PMRXD3 internal pulldown.
IEEE 802.3x receive flow control disable
will enable receive flow control based result. will enable receive flow controlregardless result.
Note: default values controlled same pin, they programmed independently.
Frame length field check Aging enable
will check frame length field IEEE packets. actual length does match, packet will dropped. (for 1500) Enable function chip Disable aging function
LED[5][2] strap option. Pull-down (0): Aging disable. Pull-up (1): Aging Enable. Note: LED[5][2] internal pull-up. PMRXD0 strap option. Pull-down (0): Disable aggressive backoff. Pull-up (1): Aggressive back off. Note: PMRXD0 internal pulldown.
Fast enable Aggressive back enable
turn fast (800µs) enable more aggressive backoff algorithm halfduplex mode enhance performance. This IEEE standard.
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Address Name Description Mode Default
Register (0x04): Global Control Reserved Multicast storm protection disable Reserved "Broadcast Storm Protection" does include multicast packets. Only DA=FFFFFFFFFFFF packets will regulated. "Broadcast Storm Protection" includes FFFFFFFFFFFF DA[40] packets. Reserved fair mode selected. this mode, flow control port non-flow control port talk same destination port, packets from non-flow control port dropped. This prevent flow control port from being flow controlled extended period time. this mode, flow control port non-flow control port talk same destination port, flow control port will flow controlled. This "fair" flow control port. switch will drop packets when more collisions occur. switch will drop packets when more collisions occur.
Reserved Flow control back pressure fair mode
excessive collision drop
PMRXD1 strap option. Pull-down (0): Drop excessive collision packets Pull-up (1): Don't drop excessive collision packets. Note: PMRXD1 internal pulldown.
Huge packet support
will accept packet sizes 1916 bytes (inclusive). This setting will override setting from same register. packet size will determined this register. will accept packet sizes 1536 bytes (inclusive). 1522 bytes tagged packets (not including packets with STPID from ports 1-4), 1518 bytes untagged packets. packets larger than specified value will dropped."
Legal maximum packet size check disable
PMRXER strap option. Pull-down (0): 1518/1522 byte packets Pull-up value will dropped. (1): 1536 byte packets. Note: PMRXER internal pull down.
Priority Buffer Reserve
each output queue pre-allocated buffers, used exclusively high priority packets. recommended enable this when priority queue feature turned reserved buffers high priority packets.
Register (0x05): Global Control Reserved Reserved Reserved Reserved Priority scheme select Reserved Reserved Reserved Reserved always deliver high priority packets first. deliver high/low packets ratio 10/1. deliver high/low packets ratio 5/1. deliver high/low packets ratio 2/1.
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Address Name Description Mode Default
Register (0x05): Global Control (continued) Reserved Sniff mode select Reserved will sniff (both source port destination port need match). will sniff (Either source port destination port needs match). This mode used implement only sniff.
Register (0x06): Global Control Switch back Pressure enable Switch half duplex mode enable half-duplex back pressure switch interface. disable back pressure switch interface. enable interface half-duplex mode. enable interface full-duplex mode.
SMRXD2 strap option. Pull-down (0): Full-duplex mode Pull-up (1): Halfduplex mode. Note: SMRXD2 internal pulldown. SMRXD3 strap option. Pull-down (0): disable flow control Pull-up (1): enable flow control Note: SMRXD3 internal pulldown. SMRXD1 strap option. Pull-down (0): Enable 100Mbps Pull-up (1): Enable 10Mpbs Note: SMRXD1 internal pull-down.
Switch flow control enable
enable full-duplex flow control switch interface. disable full-duplex flow control switch interface.
Switch 10BT
switch interface 10Mbps mode. switch interface 100Mbps mode.
Null replacement Broadcast storm protection rate [10:8]
will replace null with port VID(12 bits). replacement null VID. This along with next register determines many byte blocks" packet data allowed input port preset period. period 50ms 100BT 500ms 10BT. default
Register (0x07): Global Control Broadcast storm protection rate [7:0] This along with previous register determines many byte blocks" packet data allowed input port preset period. period 50ms 100BT 500ms 10BT. default 0x4A(1)
Notes: 148,800 frames/sec 50ms/interval frames/interval (approx.) 0x4A
Register (0x08): Global Control Factory testing Reserved 0x24
Register (0x09): Global Control Factory testing Reserved 0x24
Register (0x0A): Global Control Factory testing Reserved 0x24
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Address Name Description Mode Default
Register (0x0B): Global Control Reserved mode mode mode SMRXD0 strap option. Pull-down(0): Enabled mode Pull-up(1): Enabled. mode Note: SMRXD0 internal pull-down Mode LEDX_2 LEDX_1 LEDX_0 Reserved Reserved Lnk/Act Fulld/Col Speed Mode 100Lnk/Act 10Lnk/Act Fulld
Port Registers
following registers used enable features that assigned port basis. register assignments same ports, address each port different, indicated.
Register (0x10): Port Control Register (0x20): Port Control Register (0x30): Port Control Register (0x40): Port Control Register (0x50): Port Control Address Name Broadcast storm protection enable DiffServ priority classification enable 802.1p priority classification enable Port-based priority classification enable Description enable broadcast storm protection ingress packets port. disable broadcast storm protection. enable DiffServ priority classification ingress packets port. disable DiffServ function. enable 802.1p priority classification ingress packets port. disable 802.1p. ingress packets port will classified high priority "DiffServ" "802.1p" classification enabled fails classify. ingress packets port will classified priority "DiffServ" "802.1p" classification enabled fails classify. Mode Default
Note: "DiffServ", "802.1p" port priority enabled same time. OR'ed result 802.1p DSCP overwrites port priority.
Reserved insertion Reserved
when packets output port, switch will 802.1q tags packets without 802.1q tags when received. switch will tags packets already tagged. inserted ingress port's "port VID." disable insertion. when packets output port, switch will remove 802.1q tags from packets with 802.1q tags when received. switch will modify packets received without tags. disable removal.
removal
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Address Name Priority enable Description port output queue split into high priority queues. single output queue port. There priority differentiation even though packets classified into high priority. Mode Default
Register (0x11): Port Control Register (0x21): Port Control Register (0x31): Port Control Register (0x41): Port Control Register (0x51): Port Control Address Name Sniffer port Description port designated sniffer port will transmit packets that monitored. port normal port. packets received port will marked "monitored packets" forwarded designated "sniffer port." receive monitoring. packets transmitted port will marked "monitored packets" forwarded designated "sniffer port." transmit monitoring. Define port's Port VLAN membership. stands port port port Port only communicate within membership. includes port membership, excludes port from membership. Mode Default
Receive sniff
Transmit sniff
Port VLAN membership
0x1f
Register (0x12): Port Control Register (0x22): Port Control Register (0x32): Port Control Register (0x42): Port Control Register (0x52): Port Control Address Name Reserved Reserved Discard PVID packets Force flow control Description Reserved Reserved switch will discard packets whose does match ingress port default VID. packets will discarded. will always enable flow control port, regardless result. flow control enabled based result. Mode Default
Note: Setting port both half-duplex forced flow control illegal configuration. half-duplex enable back pressure.
port only, there special configuration default,Pin PCOL strap option. Pull-down (0): Force flow control. Pull-up (1): Force flow control. Note: PCOL internal pull-down.
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Address Name Back pressure enable Description enable port's half-duplex back pressure. disable port's half-duplex back pressure. Mode Default
PMRXD2 strap option. Pull-down (0): disable back pressure. Pull-up(1): enable back pressure. Note: PMRXD2 internal pull-down.
Transmit enable Receive enable Learning disable
enable packet transmission port. disable packet transmission port. enable packet reception port. disable packet reception port. disable switch address learning capability. enable switch address learning.
Register (0x13): Port Control Register (0x23): Port Control Register (0x33): Port Control Register (0x43): Port Control Register (0x53): Port Control Address Name Default [15:8] Description Port's default tag, containing 7-5: user priority bits VID[11:8] Mode Default
Register (0x14): Port Control Register (0x24): Port Control Register (0x34): Port Control Register (0x44): Port Control Register (0x54): Port Control Address
Note: Registers (and those corresponding other ports) serve purposes: Associated with ingress untagged packets, used egress tagging; Default ingress untagged null-VID-tagged packets, used address look
Name Default [7:0]
Description Default port tag, containing 7-0: VID[7:0]
Mode
Default
Register (0x15): Port Control Register (0x25): Port Control Register (0x35): Port Control Register (0x45): Port Control Register (0x55): Port Control Address Name Transmit high priority rate control [7:0] Description This along with port control bits [3:0] form 12-bit field determine many "32Kbps" high priority blocks transmitted. unit bytes second period.) Mode Default
Register (0x16): Port Control Register (0x26): Port Control Register (0x36): Port Control Register (0x46): Port Control Register (0x56): Port Control Address Name Transmit priority rate control [7:0] Description This along with port control bits [7:4] form 12-bit field determine many "32Kbps" priority blocks transmitted. unit bytes second period.) Mode Default
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Register (0x17): Port Control Register (0x27): Port Control Register (0x37): Port Control Register (0x47): Port Control Register (0x57): Port Control Address Name Transmit priority rate control [11:8] Description This along with port control bits [7:0] form 12-bit field determine many "32Kbps" priority blocks transmitted. unit bytes second period.) This along with port control bits [7:0] form 12-bit field determine many "32Kbps" high priority blocks transmitted. unit bytes second period.) Mode Default
Transmit high priority rate control [11:8]
Register (0x18): Port Control Register (0x28): Port Control Register (0x38): Port Control Register (0x48): Port Control Register (0x58): Port Control Address Name Receive high priority rate control [7:0] Description This along with port control bits [3:0] form 12-bit field determine many "32Kbps" high priority blocks received. unit bytes second period.) Mode Default
Register (0x19): Port Control Register (0x29): Port Control Register (0x39): Port Control Register (0x49): Port Control Register (0x59): Port Control Address Name Receive priority rate control [7:0] Description This along with port control bits [7:4] form 12-bit field determine many "32Kbps" priority blocks received. unit bytes second period.) Mode Default
Register (0x1A): Port Control Register (0x2A): Port Control Register (0x3A): Port Control Register (0x4A): Port Control Register (0x5A): Port Control Address Name Receive priority rate control [11:8] Description This along with port control bits [7:0] form 12-bit field determine many "32Kbps" priority blocks received. unit bytes second period.) This along with port control bits [7:0] form 12-bit field determine many "32Kbps" high priority blocks received. unit bytes second period.) Mode Default
Receive high priority rate control [11:8]
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Register (0x1B): Port Control Register (0x2B): Port Control Register (0x3B): Port Control Register (0x4B): Port Control Register (0x5B): Port Control Address Name Receive differential priority rate control Description also this will enable receive rate control this port priority packets priority rate. also `1', this will enable receive rate control high priority packets high priority rate. receive rate control will based priority rate packets this port. enable port's priority receive rate control feature. disable port's priority receive rate control. Mode Default
priority receive rate control enable High priority receive rate control enable
also this will enable port's high priority receive rate control feature. `1', receive packets this port will rate controlled priority rate. disable port's high priority receive rate control feature. flow control asserted port's priority receive rate exceeded. flow control asserted port's priority receive rate exceeded. flow control asserted port's high priority receive rate exceeded. this, differential receive rate control must on.) flow control asserted port's high priority receive rate exceeded. will transmit rate control both high priority packets based rate counters defined high priority packets respectively. will transmit rate control packets rate counters defined priority will used. enable port's priority transmit rate control feature. disable port's priority transmit rate control feature. enable port's high priority transmit rate control feature. disable port's high priority transmit rate control feature.
priority receive rate flow control enable
High priority receive rate flow control enable
Transmit differential priority rate control
priority transmit rate control enable
High priority transmit rate control enable
Register (0x1C): Port Control Register (0x2C): Port Control Register (0x3C): Port Control Register (0x4C): Port Control Register (0x5C): Port Control
Note: Port Control Port Status contents accessed MIIM (MDC/MDIO) interface standard MIIM register definition.
Address
Name Disable auto-negotiation
Description disable auto-negotiation, speed duplex decided same register. auto-negotiation forced 100BT disabled (bit forced 10BT disabled (bit
Mode
Default
Forced speed
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Address Name Forced duplex Description forced full-duplex disabled enabled failed. forced half-duplex disabled enabled failed. Mode Default
(For port only, there special configure default, PCRS strap option. Pull-down (0): Force half-duplex. Pull-up (1): Force full-duplex. Note: PCRS internal pull down)
Advertised flow control capability Advertised 100BT full-duplex capability Advertised 100BT half-duplex capability Advertised 10BT full-duplex capability Advertised 10BT half-duplex capability
advertise flow control capability. suppress flow control capability from transmission link partner. advertise 100BT full-duplex capability. suppress 100BT full-duplex capability from transmission link partner. advertise 100BT half-duplex capability. suppress 100BT half-duplex capability from transmission link partner. advertise 10BT full-duplex capability. suppress 10BT full-duplex capability from transmission link partner. advertise 10BT half-duplex capability. suppress 10BT half-duplex capability from transmission link partner.
Register (0x1D): Port Control Register (0x2D): Port Control Register (0x3D): Port Control Register (0x4D): Port Control Register (0x5D): Port Control Address Name Description turn port's LEDs (LEDx_2, LEDx_1, LEDx_0, where port number). These pins will driven high this one. normal operation. disable port's transmitter. normal operation. restart auto-negotiation. normal operation. disable fault detection pattern transmission. enable fault detection pattern transmission. power down. normal operation. disable auto MDI/MDIX function. enable auto MDI/MDIX function. auto MDI/MDIX disabled, force into mode. force into mode. perform "local loopback", ie., loopback PHYs back normal operation. Mode Default
Txids Restart Disable fault Power down Disable auto MDI/MDIX Forced
Loopback
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Register (0x1E): Port Status Register (0x2E): Port Status Register (0x3E): Port Status Register (0x4E): Port Status Register (0x5E): Port Status Address Name MDIX status done Link good Partner flow control capability Partner 100BT full-duplex capability Partner 100BT half-duplex capability Partner 10BT full-duplex capability Partner 10BT half-duplex capability Description MDIX done done link good link good link partner flow control capable link partner flow control capable link partner 100BT full-duplex capable link partner 100BT full-duplex capable link partner 100BT half-duplex capable link partner 100BT half-duplex capable link partner 10BT full-duplex capable link partner 10BT full-duplex capable link partner 10BT half-duplex capable link partner 10BT half-duplex capable Mode Default
Register (0x1F): Port Status Register (0x2F): Port Status Register (0x3F): Port Status Register (0x4F): Port Status Register (0x5F): Port Status Address Name Reserved fault fault status detected fault status detected Description Mode Default
Advanced Control Registers
IPv4 priority control registers implement fully decoded DSCP (Differentiated Services Code Point) register used determine priority from field header. most significant bits field fully decoded into possibilities, singular code that results compared against corresponding DSCP register. register priority high; priority low.
Address Name Description Mode Default
Register (0x60): priority control register DSCP[63:56] 00000000
Register (0x61): priority control register DSCP[55:48] 00000000
Register (0x62): priority control register DSCP[47:40] 00000000
Register (0x63): priority control register DSCP[39:32] 00000000
Register (0x64): priority control register DSCP[31:24] 00000000
Register (0x65): priority control register DSCP[23:16] 00000000 M9999-120403
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Address Name Description Mode Default
Register (0x66): priority control register DSCP[15:8] 00000000
Register (0x67): priority control register DSCP[7:0] 00000000
Registers define switching engine's address. This 48-bit address used source address pause control frames.
Register (0x68): address register MACA[47:40] 0x00
Register (0x69): address register MACA[39:32] 0x10
Register (0x6A): address register MACA[31:24] 0xA1
Register (0x6B): address register MACA[23:16] 0xff
Register (0x6C): address register MACA[15:8] 0xff
Register (0X6D): address register MACA[7:0] 0xff
MIIM Registers
"PHYAD" defined IEEE assigned "0x1" port "0x2" port "0x3" port "0x4" port "0x5" port "REGAD" supported 0,1,2,3,4,5.
Address Name Description Mode Default
Register Control Soft reset Loop back Force enable Power down Isolate Restart Force full-duplex Collision test Reserved Reserved Force Disable auto MDIX Disable fault force normal operation disable auto MDIX normal operation disable fault detection normal operation soft reset normal operation loop back mode (loop back PHY) normal operation 100Mbps 10Mbps auto-negotiation enabled auto-negotiation disabled power down normal operation SUPPORTED restart auto-negotiation normal operation full-duplex half-duplex SUPPORTED
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Address Name Disable transmit Disable Description disable transmit normal operation disable normal operation Mode Default
Register Status 10-7 capable Full capable Half capable Full capable Half capable Reserved Preamble suppressed complete fault capable Link status Jabber test Extended capable SUPPORTED auto-negotiation complete auto-negotiation completed fault detected fault detected auto-negotiation capable auto-negotiation capable link link down SUPPORTED extended register capable BaseT4 capable 100BaseTX full-duplex capable capable 100BaseTX full-duplex 100BaseTX half-duplex capable 100BaseTX half-duplex capable 10BaseT full-duplex capable 10BaseT full-duplex capable 10BaseT half-duplex capable 10BaseT half-duplex capable
Register PHYID HIGH 15-0 Phyid high High order PHYID bits 0x0022
Register PHYID 15-0 Phyid order PHYID bits 0x1450
Register Advertisement Ability 12-11 Next page Reserved Remote fault Reserved Pause Reserved Full Half Full Half Selector field advertise full-duplex ability advertise full-duplex ability advertise half-duplex ability advertise half-duplex ability advertise full-duplex ability advertise full-duplex ability advertise half-duplex ability advertise half-duplex ability 802.3 advertise pause ability advertise pause ability SUPPORTED SUPPORTED 00001
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Register Link Partner Ability 12-11 Next page Remote fault Reserved Pause Reserved full half full half Reserved Link partner full capability Link partner half capability Link partner full capability Link partner half capability Link partner pause capability SUPPORTED SUPPORTED SUPPORTED 00000
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Absolute Maximum Ratings(1)
Supply Voltage (VDDAR, VDDAP, VDDC) -0.5V +2.4V (VDDAT, VDDIO) -0.5V +4.0V Input Voltage (All Inputs) -0.5V +4.0V Output Voltage (All Outputs) -0.5V +4.0V Lead Temperature (soldering, sec.) 270°C Storage Temperature (TS) -55°C +150°C
Operating Ratings(2)
Supply Voltage (VDDAR, VDDAP, VDDC) +1.7V +1.9V (VDDAT, VDDIO) +2.4V +2.6V +3.0 +3.6 Ambient Temperature (TA) Commercial -0°C +70°C Package Thermal Resistance(3) PQFP (JA) Flow 42.91°C/W
Electrical Characteristics(4)
1.8V/2.5V (typ.); 1.9V/3.6V (max.); +70°C; unless noted. Symbol Parameter Condition Units 100BaseTX Operation-All Ports 100% Utilization IDDC IDDIO IDDC IDDIO IDDC IDDIO Inputs Outputs |IOZ| VIMB Output High Voltage Output Voltage Output Tri-State Leakage -8mA VDDIO -0.4 +0.4 Input High Voltage Input Voltage Input Current (Excluding Pull-up/Pull-down) VDDIO (1/2 VDDIO) +0.4 (1/2 VDDIO) -0.4 100BaseTX (Transmitter) VDDAT VDDIO VDDAT VDDC, VDDAP VDDIO VDDAT VDDC, VDDAP VDDIO
100BaseTX (Digital Core/PLL Analog VDDC, VDDAP, VDDAR 100BaseTX (Digital
10BaseTX Operation-All Ports 100% Utilization 10BaseTX (Transmitter) 10BaseTX (Digital Core Analog 10BaseTX (Digital
Auto-Negotiation Mode 10BaseTX (Transmitter) 10BaseTX (Digital Core Analog 10BaseTX (Digital
100BaseTX Transmit (measured differentially after transformer) Peak Differential Output Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance
Notes: Exceeding absolute maximum rating damage device. device guaranteed function outside operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). (heat spreader) package. Specification packaged product only.
termination differential output termination differential output
0.95
1.05
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Symbol Parameter Condition ±0.5 Peak-to-peak
Units
100BaseTX Transmit (measured differentially after transformer) Duty Cycle Distortion Overshoot VSET Reference Voltage ISET Output Jitters 10BaseT Receive Squelch Threshold 5MHz square wave
10BaseT Transmit (measured differentially after transformer) VDDAT 2.5V Peak Differential Output Voltage Jitters Added Rise/Fall Times termination differential output termination differential output ±3.5
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Timing Diagrams
Receive Timing tcyc1
Figure EEPROM Interface Input Receive Timing Diagram
tcyc1 Transmit Timing
tov1
Figure EEPROM Interface Output Transmit Timing Diagram
Symbol tCYC1 tOV1
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
16384
Units
4096 4112 4128
Table EEPROM Timing Parameters
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Receive Timing
tcyc2
MTXC MTXEN
MTXD[0]
Figure Input Timing
tcyc2 Transmit Timing
MRXC MRXDV MCOL MRXD[0]
tov2
Figure Output Timing
Symbol tCYC2
Parameter Clock Cycle Set-Up Time Hold Time Output Valid
Units
Table Timing Parameters
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Receive Timing
tcyc3
MRXCLK MTXEN MTXER MTXD[3:0]
Figure Mode Timing-Data Received from
tcyc3 Transmit Timing
MTXCLK MRXDV MRXD[3:0]
tov3
Figure Mode Timing-Data Transmitted from
Symbol tCYC3 tCYC3 tOV3
Parameter Clock Cycle Clock Cycle Set-Up Time Hold Time Output Valid (100BaseT) (10BaseT)
Units
Table Mode Timing Parameters
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Receive Timing
tcyc4
MTXCLK MTXEN MTXER MTXD[3:0]
Figure Mode Timing Data Received from
tcyc4 Transmit Timing
MRXCLK MRXDV MRXD[3:0]
tov4
Figure Mode Timing Data Transmitted from
Symbol tCYC4 tCYC4 tOV4
Parameter Clock Cycle Clock Cycle Set-Up Time Hold Time Output Valid (100BaseT) (10BaseT)
Units
Table Mode Timing Parameters
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Supply Voltage
RST_N
Strap-In Value Strap-In Output
Figure Reset Timing
Symbol
Parameter Stable Supply Voltages Reset High Configuration Set-Up Time Configuration Hold Time Reset Strap-In Output
Units
Table Reset Timing Parameters
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Selection Isolation Transformer(1)
simple isolation transformer needed line interface. isolation transformer with integrated common-mode choke recommended exceeding requirements. following table gives recommended transformer characteristics.
Characteristics Name Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.)
Note: IEEE 802.3u standard 100BaseTX assumes transformer loss 0.5dB. transmit line transformer, insertion loss 1.3dB compensated increasing line drive current means reducing ISET resistor value.
Value 350µH 0.4µH 12pF 1.0dB 1500Vrms
Test Condition
100mV, KHz, 1MHz (min.)
0MHz 65MHz
following transformer vendors provide compatible magnetic parts Micrel's device: 4-Port Integrated Vendor Part Pulse Fuse Transpower Delta LanKom H1164 558-5999-Q9 PH406466 HB826-2 LF8731 SQ-H48W Auto MDIX Number Ports Single-Port Vendor Pulse Fuse Transpower Delta LanKom Part H1102 S558-5999-U7 PT163020 HB726 LF8505 LF-H41S Auto MDIX Number Ports
Table Qualified Magnetics Lists
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Package Information
128-Pin PQFP (PQ) MICREL, INC. 1849 FORTUNE DRIVE JOSE, 95131
(408) 944-0800
(408) 944-0970
http://www.micrel.com
information furnished Micrel this data sheet believed accurate reliable. However, responsibility assumed Micrel use. Micrel reserves right change circuitry specifications time without notification customer. Micrel Products designed authorized components life support appliances, devices systems where malfunction product reasonably expected result personal injury. Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform reasonably expected result significant injury user. Purchaser's sale Micrel Products life support appliances, devices systems Purchaser's risk Purchaser agrees fully indemnify Micrel damages resulting from such sale. 2003 Micrel, Incorporated.
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KS8995X Integrated 5-Port 10/100 Switch Rev. 1.13 General De

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