August 2001; ver. 1.02 Data Sheet Full-duplex processing capabili
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ACell Processor Mbps MegaCore Function (CP155)
August 2001; ver. 1.02 Data Sheet
Full-duplex processing capability 155.52 megabits second (Mbps) transmission rate Easy-to-use MegaWizard® Plug-In generates MegaCore® variants Quartus® software OpenCore® feature allow place-and-route, static timing analysis designs prior licensing Secure register transfer level (RTL) simulation models allow simulation with user design third-party simulators Optimized Altera® APEX20KE device architecture Complies with applicable standards, including: International Telecommunications Union, Recommendation, ISDN User Network Interfaces, ITU-T I.432, March 1993 AForum, Utopia, ATM-PHY Interface Specification, Level Version 1.0, af-phy039.000, June 1995 Altera Corporation, AtlanticInterface Functional Specification.
Typical Applications
Figure shows example system implementation CP155 interfacing with other Altera MegaCore variants achieve transmission Acells over SONET. Midbus Atlantic interfaces allow CP155 connect several other devices including:
Digital signal level (DS3) framer Physical layer convergence protocol (PLCP) framer
Figure Typical Application
Midbus Atlantic
rxclk Fiber Optic Module Clock Data Recovery SONET/SDH STS-3c/ STM-1 Framer (STS3CFRM) ACell Processor Mbps (CP155) UTOPIA Interface (UTOPIA2SL)
UTOPIA Level
Serializer Deserializer
txclk External Processor Interface
AIRbus
APEX Boundary
Altera Corporation
A-DS-IPCP155-1.02
ACell Processor Mbps MegaCore Function (CP155) Data Sheet
Functional Description
CP155 capable performing operations required support transmission convergence (TC) layer APhysical (PHY) device. operates full-duplex mode, comprises blocks, illustrated Figure
following list functions based full-feature CP155. Table possible options. Atransmission convergence receiver (RXATC) Acell delineation Byte alignment (software programmable) Loss cell delineation indication Header single-bit error correction, multi-bit error detection (software programmable) External Acell generic flow control (GFC) extraction (software programmable) Payload descrambling (software programmable) Discarding operations, administration, maintenance (OAM) cells selectable cell filtering Cell insertion extraction through AIRbus interface Performance monitoring received corrected, corrupted, filtered cells Acell formatting bits) Atransmission convergence transmitter (TXATC) Acell formatting bits) Discarding cells selectable cell filtering Cell insertion extraction through AIRbus interface Performance monitoring transmitted corrected, corrupted, filtered cells Internal header error control (HEC) generation insertion (software programmable) External Acell insertion (software programmable) Payload scrambling (software programmable) Cell rate decoupling with programmable idle cell header payload
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) Data Sheet
Interfaces Protocols
Three interfaces support CP155: middle interface (Midbus), access internal registers (AIRbus) interface, Atlantic interface.
Midbus Interface
Midbus interface simple synchronous full-duplex data path bus. CP155 Midbus runs 19.44 over single byte lane each direction. receive direction (RX), data transferred from Midbus master slave (CP155). transmit direction (TX), data transferred from slave (CP155) master. each direction, Midbus carry eight bits clock cycle. includes Midbus receive data (mrxdat[7:0]) Midbus receive enable (mrxena) lines indicate valid data transfers direction, Midbus transmit data (mtxdat[7:0]) Midbus transmit enable (mtxena) lines indicate valid data requests direction. Since CP155 slave Midbus work with Midbus master.
AIRbus Interface
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[15:0]) write data (wdata[15:0]) buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[7:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. CP155 AIRbus slave with data width bits.
Atlantic Interface
Atlantic interface full-duplex synchronous protocol supporting both packets cells. CP155 Atlantic interface master using 16-bit wide data path deliver cells slave. example slave UTOPIA interface MegaCore variant shown Figure UTOPIA interface MegaCore variant includes multi-cell first first (FIFO) buffer crossing clock domain.
More detailed information Midbus, AIRbus, Atlantic interfaces available from Altera site http://www.altera.com.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) Data Sheet
Figure Block Diagram
CP155 rxclk rxreset_n RXATC arxena arxdav arxdat[15:0] arxsop arxeop arxerr atxena TXATC atxdav atxval atxdat[15:0] atxsop atxeop atxerr
Midbus Interface
Extraction Interface
mrxdat[7:0] mrxena rxgfcclk rxgfcfp rxgfc rxcp
txclk
txreset_n
Atlantic Interface
Midbus Interface
Insertion Interface
mtxdat[7:0] mtxena txgfcclk txgfcfp txgfc txcp
read
addr[7:1]
wdata[15:0]
rdata[15:0]
dtack
AIRbus Interface
Signals
following port list CP155. signal direction indicated input, output. Clock Domain Signals: rxclk (I), rxreset_n (I); Midbus Signals: mrxdat[7:0] (I), mrxena (I); Extraction Signals: rxgfcclk (O), rxgfcfp (O), rxgfc (O); Miscellaneous Signals: (O), rxcp (O); Atlantic Signals: arxena (O), arxdav (I), arxdat[15:0] (O), arxsop (O), arxeop (O), arxerr (O). AIRbus Signals: (I), read (I), addr[7:1] (I), wdata[15:0] (I), rdata[15:0] (O), dtack (O), (O). Clock Domain Signals: txclk (I), txreset_n (I); Midbus Signals: mtxdat[7:0] (O), mtxena (I); Insertion Signals: txgfcclk (O), txgfcfp (O), txgfc (I); Miscellaneous Signal: txcp (O); Atlantic Signals: atxena (O), atxdav (I), atxval (I), atxdat[15:0] (I), atxsop (I), atxeop atxerr (I).
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) Data Sheet
Performance
Table shows required speed estimated gate count CP155 APEX 20KE device.
Table Performance
1,916 4,745 Notes:
Note
ESBs
fMAX (MHz)
19.44 required support 155.52 Mbps
numbers logic elements (LEs) embedded system blocks (ESBs) approximate August, 2001. They reflect range from basic fullfeature variant.
Generating Variants
Table shows optional features available generate variants.
Table Optional Options
Generic cell filters Cell insertion extraction processor interface Performance monitoring of-received transmitted- corrected, corrupted, filtered cells Notes:
cell filter included base core design filter cells. Requires four generic cell filters. allows performance monitor counts: received cells, transmitted cells, discarded cells, corrected HECs, uncorrected HECs, error cells, Atlantic error cells, cells, generic filtered cells. allows only count errored cells.
Parameters
FILT
Choices
0,1,4
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-route Static timing analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
current variants single license with ordering code: PLSM-CP155.
Altera Corporation
ACell Processor Mbps MegaCore Function (CP155) Data Sheet
Deliverables
following elements provided with CP155 package:
Data sheet User guide Midbus, AIRbus, Atlantic interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Demo testbench Access problem reporting system
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Copyright 2001 Altera Corporation. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation
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