(EPC4, EPC8, EPC16) September 2001, ver. Features Preli
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Enhanced Configuration Devices
(EPC4, EPC8, EPC16)
September 2001, ver.
Features
Preliminary Information
Enhanced configuration devices include EPC4, EPC8, EPC16 devices 16-Mbit Flash memory devices that configure APEXII, APEX 20K, MercuryTM, ACEX1K, FLEX® devices Compression increases effective configuration density these devices Mbits Available 100-pin plastic quad flat pack (PQFP) package 88-pin Ultra FineLine BGApackage Standard Flash controller combined into package VCCINT VCCIO both Supports true N-bit programmable logic device (PLD) concurrent configuration mode Configures multiple PLDs parallel Supports 8-bit parallel data output every DCLK cycle Pin-selectable 2-ms 100-ms power-on reset (POR) time Programmable clock speed with three clock modes faster configuration time Internal oscillator defaults Programmable internal oscillator higher frequencies External clock source with frequencies EPC16 configuration device allows processor access unused Flash memory locations external flash interface Flash memory hold eight pages configuration files, enabling systems reconfigure PLDs with different configuration files Flash block/sector protection capability (EPC16 configuration devices only) Compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports JamStandard Test Programming Language (STAPL) Supports Joint Test Action Group (JTAG) boundary scan nINIT_CONF allows private JTAG instruction initiate configuration Programmable configuration done error detection capability Internal programmable weak pull-ups pins, Flash address, control lines, hold data line Standby mode with reduced power consumption
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Enhanced Configuration Devices
Preliminary Information
Architecture Description
Altera® enhanced configuration devices support single-device solution very high-density PLDs while decreasing configuration time. core enhanced configuration device divided into major blocks, controller Flash memory. Flash memory used APEX APEX 20K, Mercury, ACEX, FLEX device configuration, unused locations used memory storage processor. references direct Flash interface this document EPC16 configuration devices only. information using Flash memory interface EPC4 EPC8 configuration devices, please contact Altera Applications.
Figure shows block diagram enhanced configuration device's core blocks, their connection PLD, their interface with JTAG/ISP interface. Figure Enhanced Configuration Device Block Diagram
JTAG/ISP Interface
Enhanced Configuration Device
Flash
Controller
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Preliminary Information
Enhanced Configuration Devices
Enhanced Configuration Device Controller Unit
controller unit enhanced configuration device 3.3-V core interface. controller synchronous system that includes following:
Power-on reset circuitry (POR) Internal oscillator (IOSC) Clock divider unit (CDU) Decompression engine configuration unit (PCU) JTAG interface unit (JIU)
Figure shows block diagram enhanced configuration device controller unit. Figure Enhanced Configuration Device Controller Unit Block Diagram
Page Mode Select TDI, TDO, EXCLK
Enhanced Configuration Device Controller
A[20:0]
nINIT_CONF IOSC Oscillator INTOSC
nCONFIG
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Flash Memory
DQ[15:0] Decompression Engine Flash Data Flash Data
DCLK
Divide
SYSCLK
Divide
DCLK Pause [7:0]
DATA[7:0]
DCLK
Unit RD/BY# Counter Flash Reset Reset [15:8]
DATA[7:0] CONF_DONE
nSTATUS
PORSEL
Note Figure
EXCLK should connected being used.
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Enhanced Configuration Devices
Preliminary Information
Power-On Reset Unit
circuit keeps system reset until power supply voltage levels have stabilized. enhanced configuration device options time: user either keep time 100-ms default value reduce time through selectable input applications that require fast power-up. PORSEL input controls reduction time from Table page more information. unit manages controller's reset scheme. When counter expires, unit releases pin. time further extended from external source driving low. execute JTAG instructions until complete.
enhanced configuration device reset divided into three categories:
reset starts initial power-up reset during ramp drops anytime after stabilized. initiates re-configuration driving nSTATUS low, which occurs detects cyclic redundancy check (CRC) error nCONFIG input asserted PLD. controller detects error asserts initiate reconfiguration APEX APEX 20K, Mercury, ACEX FLEX devices when auto restart upon error option enabled software.
Internal Oscillator
Frequencies internal oscillator (IOSC) enhanced configuration device, which supports four modes internal clock frequencies, shown Table user program oscillator, which controlled option bits through software. Table Internal Oscillator Frequencies Mode
(MHz)
21.0 32.0 42.0
(MHz)
26.5 40.0 53.0
(MHz)
10.0 33.0 50.0 66.0
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Enhanced Configuration Devices
Clock Divider Unit
generates SYSCLK DCLK controller dividing internal oscillator clock (INTOSC) external clock (EXCLK). CDU's clock division architecture dividers. first divider divides down selected reference clock generate DCLK. second divider divides down DCLK generate SYSCLK. Each divider contains integer divider. Both divider divider also implemented first divider (N), second divider only divide integers. default from power-up, INTOSC mode first divider divide generate DCLK, second divider divide generate SYSCLK (see Figure default duty cycle clock divisions other than non-integer divisions (for non-integer dividers, duty cycle will 50%). integer divisions, allows duty cycle DCLK SYSCLK programmable setting appropriate option bits through software. DCLK frequency limited maximum DCLK frequency PLD, SYSCLK frequency limited maximum Flash performance (about MHz). Therefore, DCLK SYSCLK might different frequencies. Figure details CDU.
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maximum DCLK frequency each family specified Application Note (Configuring SRAM-Based Devices).
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Enhanced Configuration Devices
Preliminary Information
Figure Clock Divider Unit
INTOSC EXCLK
Divide DCLK
Divide SYSCLK
Decompression Engine
Enhanced configuration devices support decompression. Configuration data compressed QuartusII software stored enhanced configuration device. During configuration, decompression engine inside enhanced configuration device will decompress expand data. This feature increases effective configuration density enhanced configuration device Mbits EPC4, EPC8, EPC16, respectively. enhanced configuration device also supports parallel data reduce configuration time. However, some cases, data transfer limited Flash data transfer rate. With parallel programming mode (when DCLK frequency MHz), data output bandwidth faster than data input bandwidth reading from Flash. Because configuration time depends ratio data bits read bandwidth used, compression will improve configuration time. decompression engine decompresses configuration data before sending configuration unit (PCU) configuration.
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Preliminary Information
Enhanced Configuration Devices
Configuration Unit
function transmit decompressed data PLD, depending configuration mode. enhanced configuration device supports four concurrent configuration modes, with Depending data width, shifts data transmit appropriate data valid data pins. Unused data pins drive low. addition transmitting data PLD, responsible delaying DCLK whenever there insufficient decompressed data, i.e., when waiting decompression engine decompress data. This technique called "Pausing DCLK." manages CONF_DONE error detection logic. CONF_DONE error occurs when de-asserted within certain number clock cycles after last data transmitted PLD. When CONF_DONE error detected, asserts signals unit, which asserts start re-configuring PLD. This done only when auto-restart configuration upon frame error option enabled software.
JTAG Interface Unit
IEEE Std. 1149.1 JTAG Boundary Scan implemented enhanced configuration devices facilitate testing interconnection functionality. Enhanced configuration devices also support mode. enhanced configuration device's compliant with IEEE Std. 1532 draft specification. addition programming, erasing, verifying Flash, enhanced configuration devices (EPC16 configuration devices) also support block/sector protection through IEEE Std. 1532compliant instructions. JTAG interface unit (JIU) communicates directly with Flash memory (see Figure operates maximum JTAG frequency MHz.
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Enhanced Configuration Devices
Preliminary Information
Figure JTAG/ISP Interface
JTAG/ISP Interface
Controller
Flash Memory
Before JTAG/ISP interface programs Flash memory, JTAG instruction (PENDCFG) asserts PLD's nCONFIG (connected nINIT_CONF pin), which will terminate access Flash. When mode starts, takes over Flash memory. mode starts during configuration, configuration terminates immediately.
Flash Memory
Flash memory EPC4, EPC8, EPC16 devices Mbits, respectively, with boot block bottom. Flash memory divided into three types blocks: boot block, parameter block, main block. Each block protection capability erased individually. enhanced configuration device also program erase Flash lock bits through JTAG interface. lock bits protect Flash against inadvertent erase; block cannot erased when lock set.
Boot Block
boot block, which words EPC16 configuration device, replace dedicated boot PROM microprocessor found Excaliburembedded processor solutions). also store other system data, configuration data. boot block features hardwarecontrollable write protection protect crucial microprocessor boot code from accidental modification using combination pins block lock bit. Each block contains lock that disables program erase operation block. bottom boot block Flash memory, should connected VCC. connected GND, bottom boot block locked cannot programmed erased. only exists bottom boot blocks; other blocks affected.
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Preliminary Information
Enhanced Configuration Devices
When using Quartus software versions 1.1, should connected VCC, otherwise, Quartus software cannot successfully program device.
Parameter Block
parameter block used storing small, frequently updated parameters. EPC16 devices, there parameter blocks words. Parameter block protection controlled using combination block lock bits.
Main Block
main block fills remainder Flash memory contains configuration user memory space. EPC16 configuration devices, there blocks words. Similar parameter block, protection main block controlled using combination block lock bits.
Memory
EPC16 configuration device memory divided into main sections: controller memory space user memory space. controller memory space consists controller's option bits maximum eight pages configuration data. memory space starts with address 08000h (after words boot/parameter blocks) continues upward. bits reside from address 08000h 00801fh, they reserved option bits. Figure shows 16-Mbit Flash memory EPC16 devices.
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Enhanced Configuration Devices
Preliminary Information
Figure Flash Memory EPC16 Configuration Device (Bottom Boot)
FFFFFh
Empty locations that used PLD/processor
Used
used PLD/processor
Page
Main Block Page mode section
Page 08020h 0801Fh
Option Bits Controller's option bits
08000h Bottom words reserved processor
Boot/Parameter Block
Reserved Bottom Boot/Parameter
00000h
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Preliminary Information
Enhanced Configuration Devices
EPC16 configuration devices, boot blocks parameter blocks located bottom 32K-word blocks. lock flexibility available with blocks feature boot blocks, user want bottom 32K-word block (boot parameter blocks) processor memory space. Altera recommends using bottom 32K-word blocks (boot/parameter blocks). However, processor will boot from 32K-word blocks, user should re-map address bottom block using glue logic. systems that processor memory space, system user bottom 32K-word blocks configuration data memory space.
Page Mode Selection
Page Mode Selection feature allows enhanced configuration device store eight different designs PLD. user chooses which design will configure configuration. Page Mode Selection will enable designers switch functionality PLDs) switching pins. Each page mode have 8-bit concurrent configuration devices.
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Three input pins (PGM[2:0]) select eight pages configuration files that configure PLDs. Page defined default page (see Figure page 10). Connect these pins board select userspecified page Quartus software when generating EPC4, EPC8, EPC16 file. PGM2 most significant (MSB).
Operating Modes
operating modes define enhanced configuration device's process flow data control signals. data process flow explains data transferred between blocks during read write cycles. control process flow explains control signals handshake between blocks facilitate data transfer. main modes normal mode programming mode.
Normal Mode
Normal mode controls configuration process using compressed data Flash memory. process involves reading data from Flash memory, data decompression, sending data PLD.
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Enhanced Configuration Devices
Preliminary Information
Upon power-up, unit generates reset signals. unit resets enhanced configuration device's control units using 10-MHz default internal clock main clock source. After counter expires, unit de-asserts holding low, time extended. Upon start configuration process, device samples PGM[] select pins determine which page configuration files Flash memory should used configuration. will switch internal clock clock settings according option setting. device starts read Flash configuration data. When goes high, starts DCLK configures PLD. When last configuration data bits have been read from Flash memory, page counter expires stops reading from Flash memory. error detected CONF_DONE, DCLK will continue toggling until goes high, indicating successful configuration cycle. CONF_DONE error detection detects error, unit will assert start reconfiguration. After configuration process complete, stops DCLK. keep Flash memory idle state, device enables pull-ups, pulldowns, and/or bus-keepers Flash interface pins.
Programming Mode
During mode, JTAG interface accesses Flash memory. controller processes instructions access Flash memory through JIU. After receiving instruction, decodes instruction performs necessary Flash cycle. programming mode, interfaces with initiate reconfiguration cycle. When JTAG interface takes bus-mastership, starts reconfigure PLD. During configuration, JTAG interface should used, using interfere with configuration. After re-configuration cycle successfully completed, asserts CONF_DONE high. Upon this assertion, DCLK drives low, DATA[7:0] remains last logic state.
Device Configuration
control signals from enhanced configuration device (DATA[], DCLK, nCS, nINIT_CONF, interface directly with APEX APEX 20K, Mercury, ACEX, FLEX devices' control signals. more information parallel configuration, refer Application Note (Configuring SRAM-Based Devices).
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Preliminary Information
Enhanced Configuration Devices
DCLK pin, which driven from enhanced configuration device PLD, acts configuration cycle reference clock. functions configuration data "write-enable" strobe signal. opendrain driven when complete. built-in 2-ms 100-ms counter holds release during initial power-up permit voltage level stabilization. After expires, time extended externally driving low. When driven low, enhanced configuration device resets address counters. enhanced configuration device connected CONF_DONE PLD. checks successful configuration after last configuration data been transmitted PLD. always drives when pulled low. Both pins have programmable weak internal pull-up resistor. enhanced configuration device allows user initiate configuration APEX APEX 20K, Mercury, ACEX, FLEX devices nINIT_CONF pin, which tied nCONFIG LUT-based PLDs. JTAG instruction causes enhanced configuration device drive nINIT_CONF low, which, turn, pulls nCONFIG low. enhanced configuration device then drives nINIT_CONF high start configuration. When JTAG state machine exits this stage, nINIT_CONF releases nCONFIG, configuration initiated.
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Serial Configuration Mode
APEX APEX 20K, Mercury, ACEX, FLEX devices configured through enhanced configuration device serial programming mode. this mode, enhanced configuration device sends serial bit-stream configuration data DATA0 pin, which routed DATA0 input LUT-based PLDs. Figure shows APEX APEX 20K, Mercury, ACEX, FLEX devices configured with enhanced configuration device serial programming mode.
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Enhanced Configuration Devices
Preliminary Information
Figure Serial Configuration Mode
Enhanced Configuration Device VCCW C_WE# F_WE# C_RP# F_RP# DCLK A[20.0] DATA0 RY/BY# nINIT_CONF PORSEL PGM[2.0] EXCLK Optional External Clock Source DQ[15.0]
Processor
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
A[20.0] RY/BY# DQ[15.0]
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, external pull-up should used. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
enhanced configuration device, Flash memory stores configuration data, controller transfers configuration data through DATA0 LUT-based PLDs. DATA0, DCLK, nCS, nINIT_CONF, pins interface enhanced configuration device PLD.
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Preliminary Information
Enhanced Configuration Devices
External Flash Memory Interface
EPC16 configuration devices, unused memory portion main block (i.e., memory that used configuration file) used external source such microprocessor PLD. This external source uses unused Flash memory store application codes. address, data, control ports Flash memory internally connected enhanced configuration device controller external device pins. external source drive these external device pins access Flash memory when interface Flash available, (i.e., when controller accessing Flash memory). When controller accesses Flash memory while configuring programming enhanced configuration device, processor must tristate Flash interface pins avoid contention. When controller accessing Flash memory, interface pins tri-state allow processor access Flash memory. Flash memory access available after successful configuration PLD, indicated Table which lists signals that indicate when Flash memory available. Table Enhanced Configuration Devices Interface Signals nINIT_CONF/ nCONFIG
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nSTATUS
nCS/ CONF_DONE
External Flash Interface
available
State
enhanced configuration device power-on reset (POR) mode, nCONFIG asserted external source (PLD processor), private JTAG initiates configuration instruction. enhanced configuration device mode failed configuration. Configuration process when DCLK toggling. Enhanced configuration device blank when CONF-DONE DCLK toggling. configured.
available
(DCLK active) (DCLK inactive)
available Available
Available
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Enhanced Configuration Devices
Preliminary Information
When using external source (processor PLD) access Flash memory, following considerations should made:
User cannot force enhanced configuration device's controller relinquish Flash access external source (processor PLD). external source (processor PLD) must wait until configuration complete, when CONF_DONE goes high, before accessing Flash memory. Auto_Restart configuration option enabled corrupted programming data Flash memory, enhanced configuration devices will continuously configure PLD. such cases, external source (processor PLD) cannot access Flash memory until valid programming file downloaded enhanced configuration device. external source (processor PLD) cause configuration process restart releasing control interface then toggling nCONFIG.
Multiple Device Configuration Serial Mode
enhanced configuration device supports parallel configuration multiple devices serial configuration mode (see Figure enhanced configuration device simultaneously output parallel DATA outputs multiple LUT-based PLDs. user selects configuration modes software.
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Preliminary Information
Enhanced Configuration Devices
Figure Concurrent Configuration Multiple Devices Serial Mode (Different Data with
Enhanced Configuration Device C_WE# C_RP# DCLK DATA0 DATA1 DATA[2.6] VCCW F_WE# F_RP# A[20.0] RY/BY# DQ[15.0]
External Processor
PLD0
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
A[20.0] RY/BY# DQ[15.0]
PLD1
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
nINIT_CONF DATA PORSEL PGM[2.0] EXCLK
Optional External Clock Source
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PLD7
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used.
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Enhanced Configuration Devices
Preliminary Information
nINIT_CONF internal pull-up resistor which always active. nINIT_CONF available used, external pull-up should used. When configuring APEX 20KE device, external pull-up should used. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
Table summarizes configuration modes enhanced configuration device. Table Enhanced Configuration Device Mode Mode Name
Passive Serial Mode Passive Multi-Device Parallel Synchronous Mode Passive Multi-Device Parallel Synchronous Mode Passive Multi-Device Parallel Synchronous Mode Note Table
mode category gives number valid DATA outputs each configuration mode.
Mode Used Outputs
DATA0 DATA[1.0]
Unused Outputs
DATA[7.1] drive DATA[7.2] drive
DATA[3.0]
DATA[7.4] drive
DATA[7.0]
Figure shows parallel configuration multiple devices serial mode with same DATA.
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Enhanced Configuration Devices
Figure Concurrent Configuration Multiple Devices Serial Mode (Same Data with
EPC16 Configuration Device VCCW C_WE# F_WE# C_RP# F_RP# DCLK A[20.0] DATA0 RY/BY# nINIT_CONF DQ[15.0]
Processor
PLD0
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
A[20.0] RY/BY# DQ[15.0]
PLD1
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
PORSEL PGM[2.0] EXCLK Optional External Clock Source
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PLD7
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL1 MSEL0
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source external EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used.
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Enhanced Configuration Devices
Preliminary Information
nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, external pull-up should used. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
Parallel Configuration Mode
APEX devices configured through enhanced configuration devices fast parallel configuration mode. this mode, enhanced configuration device sends byte data DATA[7.0] pins, which route DATA[7.0] input pins APEX device. APEX devices receive byte-wide configuration data each clock cycle. Figure shows enhanced configuration device parallel configuration mode. Figure Parallel Configuration Mode
Enhanced Configuration Device VCCW C_WE# F_WE# C_RP# F_RP# DCLK A[20.0] DATA[7.0] RY/BY#
Processor
APEX Device DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
A[20.0] RY/BY# DQ[15.0]
PORSEL PGM[2.0]
DQ[15.0]
EXCLK
Optional External Clock Source
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com).
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Preliminary Information
Enhanced Configuration Devices
Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. pull-up resistors 1-k. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
Figure shows diagram multiple APEX device configuration with enhanced configuration device parallel programming mode. this mode, multiple APEX devices cascaded together. After first APEX device completes configuration, nCEO activates second APEX device's pin. This activation prompts second device start configuration. (See Figure 10.) Because CONF_DONE pins tied together, devices initialize simultaneously enter user mode. enhanced configuration device detects error, configuration stops whole chain because nSTATUS pins tied together.
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Preliminary Information
Figure Parallel Configuration Multiple Devices Chain
Enhanced Configuration Device VCCW C_WE# F_WE# C_RP# F_RP# DCLK DATA[7.0] A[20.0] RY/BY#
External Processor
APEX Device DCLK nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
APEX Device DCLK DATA[7.0] nSTATUS CONF_DONE nCEO nCONFIG MSEL0 MSEL1
A[20.0] RY/BY# DQ[15.0]
PORSEL PGM[2.0]
DQ[15.0]
EXCLK
Optional External Clock Source
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. pull-up resistors 1-k. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
Serial Configuration Multiple Devices Chain
Because enhanced configuration devices contain significant amount Flash memory, user does need cascade multiple enhanced configuration devices configure large devices.
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Enhanced Configuration Devices
enhanced configuration device configure chain PLDs that cascaded together. Figure shows enhanced configuration device configuring chain multiple PLDs serial mode. Figure Serial Configuration Multiple Devices Chain
Enhanced Configuration Device VCCW C_WE# F_WE# C_RP# F_RP# DCLK A[20.0] DATA0 RY/BY# nINIT_CONF PORSEL PGM[2.0] EXCLK Optional External Clock Source DQ[15.0]
External Processor
PLDN DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
PLD0 DCLK DATA0 nSTATUS CONF_DONE nCEO nCONFIG MSEL0 MSEL1
A[20.0] RY/BY# DQ[15.0]
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Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source external EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). Flash interface EPC4 EPC8 configuration devices, please contact Altera Applications. nCS, nINIT_CONF pins enhanced configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices should left floating. These pins should connected signal, i.e., they no-connect pins. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, external pull-up should used. more information, refer Application Note (Configuring SRAM-Based Devices). Flash interface exists only EPC16 configuration devices tri-state interface. signals displayed dotted lines should driven when Flash interface available. Flash interface availability, refer Table page EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source.
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Enhanced Configuration Devices
Preliminary Information
Figure shows timing waveform enhanced configuration device scheme. Figure Enhanced Configuration Device Scheme Timing Waveform
nINIT_CONF VCC/nCONFIG OE/nSTATUS tLOE
Note
nCS/CONF_DONE DCLK DATA User INIT_DONE
Driven High
bit/byte bit/byte
bit/byte
User Mode
Notes Figure
timing information, refer Table page configuration device will drive DATA after configuration. APEX APEX devices enter user mode clock cycles after CONF_DONE goes high. Mercury devices enter user mode clock cycles after CONF_DONE goes high. ACEX FLEX 10K, FLEX 6000 devices enter user mode clock cycles after CONF_DONE goes high.
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Enhanced Configuration Devices
Table defines enhanced configuration device timing parameters when using enhanced configuration devices Table Enhanced Configuration Device Configuration Parameters (PLD Interface) Symbol
fDCLK tDCLK tCAC tLOE fECLK tECLK tECLKH tECLKL tECLKR tECLKF tPOR
Parameter
DCLK frequency DCLK period DCLK duty cycle high time DCLK duty cycle time first DCLK delay first DATA available DCLK rising edge DATA change assert DCLK disable delay assert DATA disable delay DATA hold time from last DCLK rising edge DCLK rising edge assert time assure reset EXCLK input frequency EXCLK input period EXCLK input duty cycle high time EXCLK input duty cycle time EXCLK input rise time EXCLK input fall time time
Condition
duty cycle
66.7
Unit
duty cycle duty cycle
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133.3
duty cycle duty cycle duty cycle 3.375 3.375
Notes Table
This parameter used CONF_DONE error detection enhanced configuration device. Contact Altera Applications detailed information. This parameter used cyclic redundancy check (CRC) error detection CPLD. ramp time should less than 2-ms POR, should less than 100-ms POR.
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Enhanced Configuration Devices
Preliminary Information
Power Sequencing
Altera recommends that power-up before enhanced configuration device's expires. pin-selectable time feature useful ensuring this power-up sequence. enhanced configuration device settings, more margin, 100-ms setting selected allow power-up before configuration attempted.
Enhanced Configuration Device Pin-Outs
Tables through describe definitions enhanced configuration device. These tables include interface pins, Flash interface pins, JTAG interface pins, other pins. Table Interface Pins with Respect Controller Name
DATA[7.0] DCLK
Type
Output Output
Description
This configuration output data bus. DATA changes each rising edge DCLK. DCLK always output. enhanced configuration device drives DCLK signal configuration clock. input enhanced configuration device used input PLD's CONF_DONE signal error detection after last configuration data transmitted PLD. will always drive when asserted. This contains programmable internal weak pull-up. nINIT_CONF connected nCONFIG LUT-based PLDs initiate configuration enhanced configuration device private JTAG instruction. This contains programmable internal weak pull-up. This driven when complete. user-selectable 2-ms 100-ms counter holds release during initial power permit voltage levels stabilize. time extended externally driving low. After enhanced configuration device controller releases waits high before starting configuration process. This contains programmable internal weak pull-up.
Input
nINIT_CONF
Output
Open-Drain
Altera Corporation
Preliminary Information
Enhanced Configuration Devices
Table Flash Interface Pins Name
A[20:0]
Note Description
These pins address input Flash memory read write operations. addresses internally latched during write cycle. These pins Data that interface with Flash memory controller. controller external source drives DQ[15:0] during Flash command data write cycles. During data read cycle, Flash memory drives DQ[15:0] controller. When asserted, activates Flash memory. When high, deselects device reduces power consumption standby levels. When asserted, resets Flash memory. When high, enables normal operation. When low, inhibits write operation Flash memory, which provides data protection during power transitions. controller asserts this during Flash read cycles. When asserted, enables drivers Flash output pins. controller asserts during Flash write cycle. When asserted, controls writes Flash memory. Flash memory, addresses data latched rising edge pulse. This usually tied ground board. controller does drive this because could cause contention. Block erase, full chip erase, word write, lock configuration power supply. Flash asserts this when write erase operation complete. This Flash only pin.
Type
Input
DQ[15:0]
Input/Output
Input
(3),
Input
(3),
Input Input
Development Tools
(3), VCCW RY/BY# Notes Table
Input Supply Output
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). EPC16 devices, pins EPC8 devices, pins A20, A19, EPC4 devices floating. These pins should connected signal, i.e., they no-connect pins. symbol means active low. These pins driven during Flash testing. Because controller cannot tolerate 12-V level, connection these pins from controller Flash will bonded internally package they will available separate pins. user required connect pins board level (for example, PCB, connect from controller from Flash memory, shown Figure page 29). should connected board when using Quartus software versions 1.1.
Altera Corporation
Enhanced Configuration Devices
Preliminary Information
Table JTAG Interface Pins Other Pins with Respect Controller Name
PGM[2.0]
Type
Input Output Input Input Input
Description
This JTAG data input pin. Connect this JTAG circuitry used. This JTAG data output pin. connect this JTAG circuitry used. This JTAG clock pin. Connect this ground JTAG circuitry used. This JTAG mode select pin. Connect this JTAG circuitry used. These three input pins select eight pages configuration files configure PLD. Connect these pins board select page specified designer Quartus software when generating enhanced configuration device file. PGM[2] MSB. During Normal mode, EXCLK operates external clock source. This selects 2-ms 100-ms counter delay during power When PORSEL Low, time When PORSEL High, time Test mode selects different test modes. operating mode, this should connected Test mode selects different test modes. operating mode, this should connected
EXCLK PORSEL
Input Input
Input Input
Package
EPC16 configuration device available both 88-pin Ultra FineLine package 100-pin PQFP package. Ultra FineLine package, which based 0.8-mm pitch, maximizes board space efficiency. board laid this package using only layer. EPC8 EPC4 devices available 100-pin PQFP package. Figure shows routing 88-pin Ultra FineLine package. Gerber file this layout Altera site http://www.altera.com.
Altera Corporation
Preliminary Information
Enhanced Configuration Devices
Figure Routing 88-Pin Ultra FineLine Package
Note
DCLK
DATA7
DQ15
PGM0
DQ14
DATA5
DATA6
RY/BY#
nINIT CONF
PGM1
DQ13
DATA4
DQ12
DATA3
VCCW
DQ11
DQ10
DATA2
PGM2
PORSEL
DATA1
DATA0
Development Tools
EXCLK
Notes Figure
direct Flash interface used enhanced configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#. Flash being used external memory source EPC16 configuration devices), then Flash pins should connected. more information, consult LHF16J06 Data Sheet Altera site (http://www.altera.com). RP#F WE#F pins Flash die. RP#C WE#C pins controller die. WE#C WE#F should connected together PCB. RP#F RP#C should also connected together PCB. should connected able program bottom boot block, which required when programming device from Quartus software.
Altera Corporation
Enhanced Configuration Devices
Preliminary Information
Package Layout Recommendation
Enhanced configuration devices 100-pin PQFP packages have different package dimension than other 100-pin PQFP devices. Figure shows 100-pin PQFP footprint specifications enhanced configuration devices. These footprint dimensions based vendor-supplied package outline diagrams. Figure Enhanced Configuration Device Footprint Specifications 100-Pin PQFP Packages Notes (1), (2),
0.65-mm pitch
0.325
19.3
0.410
25.3
Altera Corporation
Preliminary Information Notes Figure
Enhanced Configuration Devices
Used 0.5-mm increase front back nominal foot length Used 0.3-mm increase maximum foot width. Diagrams based vendor-supplied drawings.
Programming Configuration File Support
Quartus development software provides programming support enhanced configuration device automatically generates programming files EPC4, EPC8, EPC16 configuration devices. multi-device project, software combine programming files multiple APEX APEX 20K, Mercury, ACEX, FLEX devices into EPC4, EPC8, EPC16 configuration device. Enhanced configuration devices programmed in-system through industry-standard 4-pin JTAG interface. enhanced configuration device provides ease prototyping updating APEX APEX 20K, Mercury, ACEX, FLEX device functionality. Enhanced configuration devices also programmed third-party Flash programmers. After programming enhanced configuration device in-system, LUTbased configuration initiated including enhanced configuration device's JTAG INIT_CONF instruction. Table
Development Tools
Altera Corporation
Enhanced Configuration Devices
Preliminary Information
circuitry enhanced configuration device compliant with IEEE Std. 1532 specification. IEEE Std. 1532 standard that allows concurrent between devices from multiple vendors. Table Enhanced Configuration Device JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Description
Allows snapshot state enhanced configuration device pins captured examined during normal device operation permits initial data pattern output device pins. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing results input pins. Places 1-bit bypass register between pins, which allow data pass synchronously through selected device adjacent devices during normal device operation. Selects device IDCODE register places between TDO, allowing device IDCODE serially shifted TDO. device IDCODE enhanced configuration device shown below: 0100A0DDh Selects USERCODE register places between TDO, allowing USERCODE serially shifted TDO. 32-bit USERCODE programmable user-defined pattern. This function initiates re-configuration process tying nINIT_CONF PLD(s) nCONFIG pin(s). After this instruction updated, nINIT_CONF released starts configuration. This function asserts nINIT_CONF before accessing Flash memory, external PLD/processor connected Flash. This avoids Flash contention when both JTAG/ISP external PLD/processor want access Flash. Before JTAG/ISP access Flash, external PLD/processor needs reset asserting nINIT_CONF, which puts external PLD/processor "reset" state waits de-assertion INIT_CONF.
EXTEST
BYPASS
IDCODE
USERCODE
INIT_CONF
PENDCFG
Note Table
enhanced configuration devices, instruction register length boundary scan length 174.
Altera Corporation
Preliminary Information
Enhanced Configuration Devices
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
enhanced configuration device provides JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundaryscan testing performed before after configuration, during configuration. Table shows timing parameters values enhanced configuration device. Table JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register highimpedance valid output Update register valid output high impedance
Unit
Development Tools
Altera Corporation
Enhanced Configuration Devices
Preliminary Information
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, supply current values, capacitance, configuration parameters enhanced configuration device.
Table Enhanced Configuration Device Absolute Maximum Rating Symbol
IMAX IOUT TSTG TAMB
Parameter
Supply voltage input voltage ground current output current, Power dissipation Storage temperature Ambient temperature Junction temperature
Condition
With respect ground With respect ground
-0.5 -0.5
Unit
bias Under bias Under bias
Table Enhanced Configuration Device Recommended Operating Conditions Symbol
Parameter
Supplies voltage 3.3-V operation Input voltage Output voltage Operating temperature
Condition
Unit
With respect ground commercial industrial
-0.3
Input rise time Input fall time
Altera Corporation
Preliminary Information
Enhanced Configuration Devices
Table Enhanced Configuration Device Operating Conditions Symbol
Parameter
Supplies voltage core High-level input voltage Low-level input voltage 3.3-V mode high-level output voltage
Condition
Unit
0.45
3.3-V mode high-level CMOS -0.1 output voltage Low-level output voltage Low-level output voltage CMOS RCONF Input leakage current Tri-state output off-state current Configuration pins -0.1 ground ground Internal pull (OE, nCS, nINIT, CONF)
Development Tools
Table Enhanced Configuration Device Supply Current Values Symbol
ICC0 ICC1
Parameter
supply current (standby) supply current (during configuration)
Condition
Unit
Table Enhanced Configuration Device Capacitance Symbol
COUT
Parameter
Input capacitance Output capacitance
Condition
Unit
Altera Corporation
Enhanced Configuration Devices
Preliminary Information
Table Enhanced Configuration Device Configuration Parameters (Flash Interface) Symbol
fSCLK tSCLK tSCLKH tSCLKL tAVQV(F) tGLQV(F) tWLWH(F) tWHR0(F)
Parameter
SYSCLK frequency SYSCLK period SYSCLK duty cycle high time SYSCLK duty cycle time Flash address data DQ[15:0] delay Flash data DQ[15:0] delay Flash pulse width Flash high ready
Condition
Unit
Device Pin-Outs
Altera site (http://www.altera.com) Altera Digital Library pin-out information.
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Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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Altera Corporation
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