40-Channel SEG/COM Driver MAY. 2001 Version SUNPLUS TECHNOLO

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40-Channel SEG/COM Driver MAY. 2001 Version SUNPLUS TECHNOLO

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SPLC100A2
40-Channel SEG/COM Driver
MAY. 2001 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC100A2
Table Contents
PAGE
GENERAL DESCRIPTION. BLOCK DIAGRAM FEATURES SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. SEGMENT DRIVER 5.2. COMMON DRIVER 5.3. BOTH CHANNEL CHANNEL USED COMMON DRIVERS (FCS VDD). ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS. 6.3. CHARACTERISTICS APPLICATION CIRCUITS. 7.1. SEGMENT DRIVER 7.2. COMMON DRIVER 7.3. SEGMENT COMMON DRIVER PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT 8.2. ORDERING INFORMATION 8.3. LOCATIONS 8.4. PACKAGE CONFIGURATION 8.5. PACKAGE INFORMATION DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2001 Version:
SPLC100A2
40-CHANNEL SEG/COM DRIVER
GENERAL DESCRIPTION
SPLC100A2 Liquid Crystal Display driver that contains sets 20-bit bi-directional shift registers, data latch flip-flops Liquid Crystal Display drivers. driver. also features 40-channel outputs that applied common segment SPLC100A2 receives serial display data from display control LSI, converts into parallel data supplies liquid crystal display waveforms liquid crystal.
FEATURES
Liquid Crystal Display driver with serial/parallel conversion function. Serial transfer facilitates board design. Capable interfacing liquid crystal display controllers: HD43160AH, HD61830, HD44780, HD44790, SPLC780 internal drivers. Internal serial/parallel conversion circuits: 20-bit shift register 20-bit latch
BLOCK DIAGRAM
V1,V2 V3,V4 Latch signal V1,V2 V5,V6 Data Shift signal 20-bit latch
Power supply: Internal logic: 2.7V 5.5V Liquid crystal display driver circuit: 3.0V 11.0V
Drivers Shift direction Data Data Shift direction
CMOS process.
SHL1 SHL2
Package form: bare chip available
20-bit bidirectional shift register Switching circuit 20-bit bidirectional shift register Data 20-bit latch Drivers
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2001 Version:
SPLC100A2
SIGNAL DESCRIPTIONS
Mnemonic SHL1 Power supply liquid crystal display drive (Select level) Power supply liquid crystal display drive (Non-select level channel Power supply liquid crystal display drive (Non-select level channel Selection shift direction channel shift register
SHL1
Type Positive power supply voltage input Ground input
Description
Power supply voltage liquid crystal display drive Liquid crystal driver output (Channel Liquid crystal driver output (Channel
SHL2
Selection shift direction channel shift register
SHL2
DL1, DL2,
Data Input Output channel shift register Data Input Output channel shift register Alternated signal liquid crystal driver output Latch signal channel Shift signal channel signal exchanges latch signal shift Used channel when Used channel when Mode select signal channel
Level Channel Latch signal Shift signal Polarity Function common drive segment drive
channel inverts channel 2.Thus, this signal exchanges function channel
Note:
indicate latches rise fall times, respectively.
Note: output level relationship between channel channel based signal level follows:
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MAY. 2001 Version:
SPLC100A2
Data
Output Level Channel 1(Y1 Y20) Channel 2(Y21 Y40)
(Select) (Non-select)
(Select) (Non-select)
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2001 Version:
SPLC100A2
FUNCTIONAL DESCRIPTIONS
5.1. Segment Driver
When SPLC100A2 used segment driver, connected VSS. this case, both channel channel shift data falling edge latch falling edge CL1. liquid crystal display driver power supply short-circuited, respectively.
(FLM) Output latch Y40)
Enlarged view DL1/DR1 DL2/DR2
Segment data waveforms type waveforms, duty cycle)
Latch Shift
5.2. Common Driver
this case, channel used segment driver channel common driver. When channel SPLC100A2 used this case, channel common driver, connected VDD. shifts data rising edge latches rising edge CL2.
Common data waveforms type waveforms channel duty cycle)
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MAY. 2001 Version:
SPLC100A2
5.3. Both Channel Channel Used Common Drivers (FCS VDD) 5.3.1. Common drivers (FCS VDD)
When both channel channel used common drives, connected signals (CL1, CL2, FLM) from controller connected following. this case, connection Liquid Crystal Display driver power supply different from that segment driver, Select level segment common Non-select level segment Non-select level common
Common driver SPLC100A2 Drive voltage liquid crystal display SHL1 SHL2
Y1-Y40 PANEL
Controller
Y1-Y40 SPLC100A2 Segment driver
Y1-Y40 SPLC100A2 Segment driver
MAY. 2001 Version:
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SPLC100A2
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Operating Voltage Driver Supply Voltage Input Voltage Input Voltage Operating Temperature Storage Temperature
Note1: will cause damage supply voltage greater than above. Note2: Connect protection resistor 220±5% VEE. Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device. conditions AC/DC Electrical Characteristics. normal operational
Symbol VIN1 VIN2 TOPR TSTG
Ratings -0.3V 7.0V 13.5V VDD+ 0.3V -0.3V 0.3V 0.3V -0.3V
6.2. Characteristics
(VDD 2.7V 5.5V, 3.0V 11.0V +25) Characteristics Input Voltage (CL1, CL2, DL1, DL2, DR1, DR2, SHL1, SHL2, FCS) Output Voltage (DL1, DL2, DR1, DR2) Driver Voltage Vi-Yj Voltage Descending V(V1 V6)-Y(Y1 Y40) Input Leakage Current (CL1, CL2, DL1, DL2, DR1, DR2, SHL1, SHL2, FCS) Leakage Current Power Supply Current Symbol VLCD Min. 0.7VDD VDD-0.4 -5.0 Typ. Max. 0.3VDD 11.0 Unit -0.1mA +0.1mA 0.1mA 0.05mA each (Output Y40: floating) FCL2 400KHz FCL1 1.0KHz Test Condition
6.3. Characteristics
Characteristics Data Shift Frequency (CL2) Clock Width High Level (CL1, CL2) Level (CL2) Symbol tCWH tCWL Min. Typ. Max. Unit (CL2CL1) (CL1CL2) 15pF Test Condition
Data Set-up Time (DL1, DL2, DR1, DR2, FLM) Clock Set-up Time (CL1, CL2) Clock Set-up Time (CL1, CL2) Date Delay Time (DL1, DL2, DR1, DR2) Clock Rise/Fall Time (CL1, CL2) Date Hold Time (DL1, DL2, DR1, DR2, FLM)
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MAY. 2001 Version:
SPLC100A2
tCWH
tCWL
Data (DL1,DL2,DR1,DR2)
Data (DL1,DL2,DR1,DR2)
tCWH
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MAY. 2001 Version:
SPLC100A2
APPLICATION CIRCUITS
7.1. Segment Driver
COM1-COM16 Controller
PANEL Common signal
7.2. Common Driver
SHL1 SHL2
Controller
SPLC100A2 Common driver
Y1-Y40 PANEL
Y1-Y40 SPLC100A2 Segment driver
SPLC100A2 (segment driver)
Y1-Y40
Segment signal
Y1-Y40 SPLC100A2 (segment driver)
Y1-Y40 SPLC100A2 Segment driver
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MAY. 2001 Version:
SPLC100A2
7.3. Segment Common Driver
Controller
Common signal Y1-Y20 Y21-Y40 SPLC100A2 (segment /common driver)
PANEL
Segment signal
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Y1-Y40 SPLC100A2 (segment driver)
MAY. 2001 Version:
SPLC100A2
PACKAGE/PAD LOCATIONS
8.1. Assignment
Chip Size: 2180µm 2410µm Size: 96µm 96µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
8.2. Ordering Information
Product Number SPLC100A2-nnnnV-C SPLC100A2-nnnnV-P
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type Chip form Package form
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MAY. 2001 Version:
SPLC100A2
8.3. Locations
Name -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -888 -748 -622 -496 -370 -244 -111 -132 -253 -374 -495 -616 -738 -859 -992 -1000 -1000 -1000 -1000 -1000 -1023 -1000 -1000 -1000 -1000 -1000 -1000 -1023 Name SHL1 SHL2 -128 -252 -375 -499 -622 -746 -944 -817 -690 -566 -442 -319 -195
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MAY. 2001 Version:
SPLC100A2
8.4. Package Configuration
View
SHL2 SHL1
SPLC100
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MAY. 2001 Version:
SPLC100A2
8.5. Package Information
Outline Dimensions Unit: inch/mm
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MAY. 2001 Version:
SPLC100A2
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2001 Version:
SPLC100A2
REVISION HISTORY
Date MAY. 2000 OCT. 2000
Revision Original Delete "PRELIMINARY" Modify Operating Current
Description
Page
Modify sequence COM/SEG application circuit same panel sequence size description MAY. 2001 Correct Chip size size "8.1 Assignment" Correct "8.2 Ordering Information" Renew document format
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MAY. 2001 Version:

40-Channel SEG/COM Driver MAY. 2001 Version SUNPLUS TECHNOLO

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