26COM/80SEG Controller/Driver JUL. 2001 Version SUNPLUS TECH

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26COM/80SEG Controller/Driver JUL. 2001 Version SUNPLUS TECH

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SPLC093C
26COM/80SEG Controller/Driver
JUL. 2001 Version
SUNPLUS TECHNOLOGY infringement patent other rights third parties which result from use. addition, SUNPLUS products authorized critical components life support devices/ systems aviation devices/systems, where malfunction failure product reasonably expected result significant injury user, without express written approval Sunplus.
SPLC093C
Table Contents
PAGE
GENERAL DESCRIPTION. FEATURES BLOCK DIAGRAM SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. SYSTEM INTERFACE 5.2. ADDRESS COUNTER (AC) 5.3. DISPLAY DATA (DDRAM) 5.4. CHARACTER GENERATOR (CGRAM) 5.5. CHARACTER GENERATOR (CGROM) 5.6. SEGMENT ICON (ICONRAM) 5.7. DRIVER CIRCUIT 5.8. POWER CONSUMPTION MODE 5.9. INSTRUCTION DESCRIPTION 5.10. DD/CG ADDRESS 5.11. ICONRAM ADDRESS 5.12. WRITE DATA 5.13. READ DATA INITIALIZING POWER SAVE MODE SETUP 6.1. HARDWARE RESET 6.2. INITIALIZING POWER SAVE SETUP DRIVING POWER SUPPLY CIRCUIT 7.1. VOLTAGE CONVERTER 7.2. VOLTAGE REGULATOR 7.3. ELECTRONIC CONTRAST CONTROL STEPS). 7.4. VOLTAGE GENERATOR CIRCUIT 7.5. INTERFACE ELECTRICAL SPECIFICATIONS 8.1. ABSOLUTE MAXIMUM RATINGS 8.2. CHARACTERISTICS. 8.3. CHARACTERISTICS APPLICATION INFORMATION PANEL 9.1. CHIP BOTTOM LOWER VIEW "0", DIRS "0"). 9.2. CHIP BOTTOM UPPER VIEW "1", DIRS "1") 9.3. CHIP LOWER VIEW "0", DIRS "1") 9.4. CHIP UPPER VIEW "1", DIRS "0") FRAME FREQUENCY. 10.1. 1/17 DUTY (2-LINE MODE) 10.2. 1/25 DUTY (3-LINE MODE)
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CHARACTER GENERATOR 11.1. SPLC093C PACKAGE/PAD LOCATIONS 12.1. ASSIGNMENT 12.2. SPLC093C DIMENSIONS 12.3. ORDERING INFORMATION 12.4. LOCATIONS DISCLAIMER. REVISION HISTORY
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26COM/80SEG CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPLC093C, driver controller matrix character display system, designed display lines 16-character with dots format. Cooperating with microprocessors, supports 4-bit 8-bit parallel modes well clock synchronized serial mode. voltage converter, double oscillator, voltage regulator, voltage follower bias circuit have been built SPLC093C advanced functions. supported. strong height character mode line vertical scroll functions also With SUNPLUS state-of-the-art technology SPLC093C provides best cost backup, Package Type Gold bumped chip Built-in Analog Circuit Internal oscillator circuit external clock Electronic volume contrast control steps) Voltage converter voltage regulator voltage follower bias circuit Power Operation Sleep mode operation Normal mode operation Operating Voltage Range Power supply voltage (VDD): 2.4V 5.5V driving voltage (VLCD VSS): 6.0V Max.
performance ratio industry.
FEATURES
Driver Output Common output: common Segment output: segment Internal Memory Character Generator (CGROM): 10,240 bits (256 characters dots) Character Generator (CGRAM): bits characters dots) Display Data (DDRAM): bits characters lines) Segment Icon (ICONRAM): bits icons) Interface busy interface busy check execution waiting time) 8-bit parallel interface mode: 68-series 80-Series 4-bit parallel interface mode: 68-series 80-Series. Serial interface mode: pins clock synchronized serial interface Function Various instruction set: display control, power save, power control, etc. bi-directional (4-type application available) Hardware reset RESET
Applicable Panel Size
Font Display 2-line characters 3-line characters Duty 1/17 1/25 Contents outputs characters icons characters icons
BLOCK DIAGRAM
RESET DB7(SI) bit/8 Address Counter DB6(SCL) Serial Display Data (DDRAM) bits bits Shift Register bits Latch Circuit Segment Driver SEG1 SEG80 Interface Parallel Instruction Register (IR)
Oscillator
Timing Generator
Instruction Decoder
bits Shift Register
Common Driver
COM1 COM24
Data Register (DR)
Interface
Data Output Register (OR)
Input Buffer
Icon bits
Character Generator (CGRAM) bits
Character Generator (CGROM) 10240 bits
Cursor Blink Controller
Driver Voltage Selector
Segment Data Conversion
Driving Power Circuit Voltage Converter Voltage Regulator Voltage Follower Bias Resister
CAP1P
CAP1N CAP2P
CAP2N
VOUT
VEXT
DIRS
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SIGNAL DESCRIPTIONS
Mnemonic Bias voltage level driving Voltages should have following relationships: V0V1V2V3V4VSS When built-in power circuit active internal bias resistors used. Power Type Power Power supply Connect power supply pin. (GND) Description
bias bias
(4/5)
(3/5)
(2/5)
(1/5)
When built-in power circuit active internal bias resistors used.
bias bias
CAP1P CAP1N CAP2P
(3/4)
(2/4)
(1/4)
Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter Capacitor connecting internal voltage converter
CAP2N
VOUT
DC/DC voltage converter output (7.2V) Voltage adjust This gives voltage between resistance-division voltage.
External reference voltage internal regulator (instead internal VREF, 1.8V) "Low (VSS)": VEXT used (open). "High (VDD)": VEXT reference-input voltage internal voltage regulator.
VEXT
Select input voltage internal voltage regulator "Low (VSS)": input voltage internal Voltage regulator internal VREF(1.8V). "High (VDD)": input voltage internal Voltage regulator voltage VEXT.
RESET
Reset input SPLC093C initialized while RESET low.
External clock input.
must fixed "High" "Low" when internal case external clock mode, used
oscillation circuit used.
clock should OFF. interface selection input "Low": 80-series
"High": 68-series Parallel serial selection input When "Low": serial mode When "High": 4-bit 8-bit mode
Register selection input When "Low", instruction register When "High", data register.
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Mnemonic Type Description Interface data length selection parallel data input When "Low" "Low" "High": serial interface mode
When "High"
"Low": 4-bit mode "High": 8-bit mode DIRS direction selection input When DIRS "Low" SEG1SEG2SEG79SEG80
When DIRS "High" SEG80SEG79SEG2SEG1
Chip selection input SPLC093C selected while low.
80-series interface mode This connected active write signal
68-series interface mode This connected When "Low", write mode When "High", read mode
COMI1 COMI2 SEG1 SEG80
Common signal output icon display These same signal name different. Segment signal output driving Test This used normal operation. 80-series interface mode (TEST1, TEST2: open)
TEST1
TEST2
This connected active read signal
68-series interface mode
This connected enabling read write command
according signal.
When 8-bit mode, used bi-directional data During 4-bit mode, only used. this case pins used. When serial mode, DB6(SCL) used serial clock input DB7(SI) used
(SCL) (SI)
COM21 COM24
serial data input pin.
Common signal output driving
COM17 COM20
COM9 COM16 COM1 COM8
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FUNCTIONAL DESCRIPTIONS
5.1. System Interface
types interface with available: mode
serial mode. mode, 4-bit 8-bit selected pin, series series selected pin.
Serial mode selected pin.
series
mode
series
(H)/(L)
(H)/(L)
Serial mode
(H)/(L)
(H)/(L)
Note1: Don't care (high, open) Note2: Fixed high (VDD) (VSS)
"High" mode, "Low" serial mode
"High" 68-series MPU, "Low" 80-series
"High" 8-bit mode, "Low" 4-bit mode (PS: "High")
(DB7)
"High" chip selected, "Low" chip selected
"High" data register, "Low" instruction register
Read Write indicating signal mode active signal enabling write mode
Enable read write command according signal mode. Serial data input
Active signal enabling read mode.
(DB6) Serial clock input
5.1.1. Interface with Parallel Mode "High")
During writing operation, 8-bit registers, Data Register (DR)
Instruction Register (IR), used. Data Register (DR) used temporary data storage place being written into DDRAM CGRAM ICONRAM these RAMs selected address setting instruction. Instruction Register (IR) used only storing instruction code transferred dummy reading makes Address Counter (AC) increased Therefore, recommended address again before writing.
instruction read cycle supported regarded operation cycle.
4-bit mode, needs transfer 4-bit data (through DB7) twice. high bits (for 8-bit mode DB7) written
before bits (for 8-bit mode DB3) write.
from MPU.
select register, input used.
During reading operation, 8-bit register Output Data Register
bits (for 8-bit mode DB3) read before high bits (for 8-bit mode DB7) read transaction. floated this 4-bit mode.
(OR) used.
Output Data Register (OR) used
pins
temporary data storage place being read from DDRAM CGRAM ICONRAM these RAMs selected
After RESET resets,
address setting instruction.
After address setting, first
4-bit mode, after
SPLC093C considers first 4-bit data from high bits.
reading dummy cycle 8-bit mode (figure
valid data comes from second reading. (figure
address setting, first second reading dummy cycles valid data comes from third reading.
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Instruction Write Dummy Read
Valid Data
Read
Data Write
Figure 8-bit Parallel Mode Data Transfer (68-series Mode)
Instruction Write Dummy Read
Valid Data
Read
Data Write
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (80-series Mode)
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upper 4-bit
lower 4-bit
lower 4-bit
upper 4-bit
upper 4-bit
lower 4-bit
Instruction Write
Dummy Read
Read
Data Write
Figure3: Timing Diagram 4-bit Parallel Mode Data Transfer (68-series Mode)
upper 4-bit
lower 4-bit
lower 4-bit
upper 4-bit
upper 4-bit
lower 4-bit
Instruction Write
Dummy Read
Read
Data Write
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (80-series Mode)
5.1.2. Interface with serial mode "Low")
When input "Low", clock synchronized serial interface
mode selected. this moment, RESET (reset input),
from serial data input
DB7) rising edge serial clock (SCL DB6).
rising edge serial clock, serial data converted into 8-bit mode data. input DR/IR
(DB6, synchronizing transfer clock), (DB7, serial input data), (register selection input) (chip selection input) used.
setting "Low", SPLC093C able receive input. "High", SPLC093C resets internal 8-bit shift
selection latched rising edge serial clock (SCL).
register 3-bit counter.
Serial data input order "D7,
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SI(DB7) SCL(DB6)
Figure Timing Diagram Serial Data Transfer
5.2. Address Counter (AC)
Address Counter (AC) SPLC093C stores DDRAM/ CGRAM/ ICONRAM address. After writing into reading from DDRAM
CGRAM ICONRAM, automatically incremented
5.3. Display Data (DDRAM)
DDRAM stores display data maximum bits (Max.
characters). DDRAM address Address Counter (AC)
hexadecimal number.
There only address counter that stores address among
DDRAM/CGRAM/ICONRAM.
COM1 COM8 COM9 COM16 Hidden Line
16th
Hidden Line
SEG1
line mode DDRAM Address
SEG80
COM1 COM8 COM9 COM16 Hidden Line
16th
Hidden Line
SEG1
line mode DDRAM Address
SEG80
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5.4. Character Generator (CGRAM)
CGRAM 8-dot characters. writing font data CGRAM, user-defined character applied. CGRAM written regardless instruction table.
5.4.1. Relationship between character code (DDRAM) character pattern (CGRAM)
Character code (DDRAM data) DD/CGRAM address CGRAM data Pattern Number
(00h)
Pattern
Pattern
(01h)
Pattern
(02h)
Pattern
(03h)
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5.4.2. Relationship between character code (DDRAM) character pattern (CGRAM) (continued)
Character code (DDRAM data) DD/CGRAM address CGRAM data Pattern Pattern Number
(04h)
(05h)
Pattern
(06h)
Pattern
Pattern
(07h)
Note: Don't care
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5.5. Character Generator (CGROM)
CGROM 8-dot characters. instruction table selects characters (00h 07h) CGROM CGRAM.
(Code:
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5.6. Segment Icon (ICONRAM)
ICONRAM contains segment control data segment pattern different. result, icons same displayed
number icons
data.
COMI1 COMI2 same signal name
same time.
COMI
COMI
SEG1 SEG2 SEG3 SEG4 SEG5
Relationship between ICONRAM Icon Display
5.6.1. Relationship between ICONRAM address display pattern
ICONRAM address ICONRAM bits
SEG76 SEG77 SEG78 SEG79 SEG80
Note: Don't care
5.7. Driver Circuit
Driver circuit involves commons segments drive LCD. Data from ICONRAM/ CGRAM/CGROM transferred
5.7.2. data shift direction
Line mode (left) (right) (left) 3-line mode (right) data shift direction COM1 COM2 COM15 COM16
80-bit segment register serially, then they stored 80-bit
shift latch. case 2-line display mode (COM1 COM16),
COMI1 COMI2 1/17 duty. 3-line mode (COM1
2-line mode
COMI1 (COMI2)
COM16 COM15 COM2COM1 COMI1 (COMI2) COM1COM2 COM23 COM24 COMI1 (COMI2) COM24 COM23 COM2 COM1 COMI1 (COMI2)
COM24), COMI1 COMI2 1/25 duty ratio. direction selected function instruction bit.
bi-directional function selected DIRS input pin, shift
5.7.1. data shift direction
DIRS data shift direction
High
SEG1SEG2 SEG3 SEG78SEG79SEG80
SEG80SEG79 SEG78 SEG3SEG2SEG1
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5.8. Power Consumption Mode
SPLC093C provides sleep mode power saving during standby period.
Liquid Crystal Display Output
COM1 COM24, COMI1, COMI2: level SEG1 SEG80: level Data written DDRAM, CGRAM, ICONRAM registers remained previous values. Operation mode retained same prior execution sleep mode. internal circuits stopped.
5.8.1. Sleep mode (Power Save Oscillation OFF)
Entering into sleep mode, power circuit oscillation circuit should turned through power saving command
power controlling command. This mode saves power
consumption reducing current reset level.
Power Circuit Oscillation Circuit built-in power supply circuit oscillation circuit turned power saving command power controlling
command.
5.9. Instruction Description 5.9.1. Instruction table
Instruction Return home returns position. Description DDRAM address from cursor
contents DDRAM changed.
Double height mode
DH2, normal display (default)
COM1 COM16 double height,
Double height
mode
COM17 COM24 normal
2-line mode: normal display 3-line mode: COM1 COM8 normal, COM9 COM24 double height normal display
Power save oscillation circuit oscillator (default)
Power save
oscillator power save (default)
power save Display line mode 2-line display mode (default) 3-line display mode Shifting direction COM.
Function
2-line mode: COM1 COM16 (default) 3-line mode: COM1 COM24 (default) 2-line mode: COM16 COM1
3-line mode: COM24 COM1 Select CGRAM CGROM
CGROM (default)
CGRAM
Cursor blink display Display control cursor (default), cursor blink (default), blink display (default), display
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Instruction Write Data Description Write DDRAM CGRAM ICONRAM Non-operation Instruction Determination DDRAM line which displayed first line
Line shift mode
LS2, DDRAM line shows first line
(default). DDRAM line shows first line LCD. DDRAM line shows first line LCD. DDRAM line shows first line Determination bias
Bias control
bias (default) bias power control
voltage converter (default)
voltage converter
Power control
voltage regulator (default)
voltage regulator voltage follower (default) voltage follower DDRAM CGRAM address
DD/CGRAM address ICONRAM address
Range: DDRAM
CGRAM
ICONRAM address, electronic volume
Range: ICONRAM (electronic volume byte).
Read DDRAM CGRAM ICONRAM registers data
Read Data
Test
Note1: "-": Don't care Note2: "*": Don't
(Note1)
Don't this Instruction.
Note3: Instruction execution time depends internal process time SPLC093C; therefore, needs provide time period larger than interface cycle time(tc) between execution successive instructions.
5.9.2. Return home
5.9.3. Double height mode
Return Home instruction field makes cursor return home. DDRAM address from cursor returns position. contents DDRAM changed.
Double Height mode instruction field selects double height line
type.
DH2, normal display line mode (default) COM1 COM16 double height, COM17 COM24 normal 2-line mode: normal display 3-line mode: COM1-COM8 normal
COM9-COM24 double height
normal display
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Line Normal Mode Display (DH2,
COM1 COM16 Double Height Line, COM17 COM24 Normal (DH2,
COM1 COM8 Normal, COM9 COM24 Double Height Line (DH2,
2-line Normal Mode Display (DH2,
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COM1 COM16 Double Height Line (DH2,
5.9.4. Power save
When "High", right shift When "Low", left shift (default) CGRAM enable Power Save instruction field controls oscillator sets resets power saving mode. When "High", CGRAM accessed this
used eight special characters area.
oscillator control
When "High", oscillator turned
(00h CGRAM font display)
When "Low", CGRAM disabled. saved using this mode (default). (00h CGROM font display) CGROM (00h 07h)
When "Low", oscillator turned (default) power save control When "High", power save mode turned When "Low", power save mode turned (default)
accessed additional current consumption
5.9.5. Function
5.9.6. Line shift mode
display line mode Instruction field selects lines lines
Line Shift mode instruction field selects
displayed first line. LS2, DDRAM line shows first line
display mode
When "High", lines display mode
When "Low", lines display mode (default) data shift direction common sets shift direction common display data
(default). DDRAM line shows first line LCD. DDRAM line shows first line LCD.
DDRAM line shows first line LCD.
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
LS2,
LS2,
LS2,
LS2,
Line Shift Mode Display Line
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Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line3 (20h 2Fh) Line4 (30h 3Fh)
Line4 (30h 3Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line1 (00h 0Fh)
Line2 (10h 1Fh)
Line3 (20h 2Fh)
LS2,
LS2,
LS2,
LS2,
Line Shift Mode Display Line
5.9.7. Bias control
5.9.9. Display control
Bias Control instruction field sets bias voltages generated internally. This used when internal voltage follower bias (default) bias
Display Control instruction field controls cursor blink display OFF. cursor control When "High", cursor turned When "Low", cursor disappeared current display (default).
5.9.8. Power control
cursor blink control When "High" "High", SPL093A makes alternate between inverting display character normal
display character cursor position with approx.
Power Control instruction field sets voltage regulator/ converter/ follower off.
second.
contrast, "Low", only normal character displayed
voltage converter circuit control
regardless flag.
When "Low", blink (default). display control
When "High", voltage converter turned
When "Low", voltage converter turned (default).
voltage regulator circuit control
When "High", voltage regulator turned
When "Low", voltage regulator turned (default). voltage follower circuit control When "High", voltage follower turned
When "Low", voltage follower turned (default).
Note: oscillation circuit must turned voltage converter circuit active.
When "High", entire display turned
When "Low", display turned OFF, display data remained DDRAM (default).
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Display state
(Blinking mode)
Cursor Attributes
5.10. DD/CG Address
5.11. ICONRAM Address
DD/CG Address Instruction field sets DDRAM CGRAM address.
ICONRAM Address instruction field sets ICONRAM Registers address.
Before writing reading data into from RAM, address
Address instruction. Then, when data written
Before writing/reading data into/from ICON RAM, address ICONRAM Address instruction. Next, when data written/read successfully, address automatically increased icons time blink bits display
/read successfully, address automatically incremented
After accessing 7Fh, address 00h. address range 7Fh.
instructions enabled.
blink attributes ICON
DD/CGRAM Address After
same cursor blink.
instruction should before accessing DD/CGRAM.
5.10.1. DD/CG address mapping
Address DDRAM line (00h 0Fh) DDRAM line (10h 1Fh)
accessing 0Fh, address ICONRAM address 00h.
ICONRAM address ranges 00h-0Fh.
5.11.1. ICONRAM address mapping
Address
DDRAM line (20h 2Fh)
DDRAM line (30h 3Fh) CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern CGRAM pattern
ICON (00h 0Fh)
Reserved
CGRAM pattern
CGRAM pattern CGRAM pattern Electronic Volume Register (10h) default (00000)
Test Register use) (11h)
When registers written, address counter
(AC) increased.
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5.12. Write Data
5.13. Read Data
This instruction field makes SPLC093C writing binary 8-bit data
DDRAM CGRAM ICONRAM register. ICONRAM Address instruction. address
DDRAM CGRAM ICONRAM data read instruction. Each selected address instruction. data read. second read transaction. second read transaction. Then,
written determined previous DD/CGRAM Address
After writing operation,
correct data obtained from
address automatically increased
first read data after setting
After reading operation, address
address dummy data; correct data comes from increased automatically.
INITIALIZING POWER SAVE MODE SETUP
6.1. Hardware Reset
When RESET "Low", SPLC093C initialized
following states. Control display instruction cursor blink display
Function instruction line display mode left shift CGRAM used.
Return Home
Address counter Electronic contrast control register:
Power saves instruction
oscillator power save Power control instruction voltage regulator voltage converter voltage follower
case 4-bit interface mode selection
SPLC093C considers first 4-bit data from high
order bits.
Note: initialization done RESETpin, unknown condition
occurred. also initialize instructions.
tRESET
RESET RESET pulse width RESET start time tRESET 10µs 50ns
RESET Timing
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6.2. Initializing Power Save Setup 6.2.1. Initializing instruction 6.2.2. Sleep Mode Release Instruction 6.2.2.1. Sleep mode
Power
Initialization
Keep RESET
Normal Operation Status (Power save Oscillator ON.)
When power stable, release reset state (RESET "H").
Command Input Display Control OFF) Power Save (PS: Power Save OFF) Power Control (VC, OFF)
Waiting 10us more
Command Input Function Electronic Volume Register Setup (ICONRAM 10h) Power Save (PS: Power Save OFF, Power Control (VC,
Enter Sleep Mode
Waiting 20ms more
6.2.2.2. Sleep mode release
Sleep Mode
Command Input Address
Command Input
Command Input Data Writing (RAM Clear) (DDRAM 20h, CG/ICONRAM 00h)
Power Save (PS: Power Save OFF, Power Control (VC,
Command Input Display Control
Waiting 20ms more
Initialization
Command Input Display Control
Note: command internal should cleared. clear DDRAM, address (first DDRAM) then write (space character code) times clear CGRAM, address (first CGRAM) then write (null data) times clear ICONRAM, ICONRAM address (first ICONRAM) then write (null data) times.
Return Normal Operation
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6.2.3. Recommendation power sequence 6.2.3.1. Power sequence 6.2.3.2. Power sequence
Power
Operation Command Input
Voltage Converter [VC,
Display
Waiting for1ms
Voltage Regulator [VC,
Voltage Regulator [VC,
Waiting for1ms
Voltage Follower [VC,
Waiting for50ms
Voltage Follower [VC,
Waiting for1ms
Voltage Converter [VC,
Operation Command Input
Waiting for1ms
Operation Command Input
DRIVING POWER SUPPLY CIRCUIT
Power Supply Circuit produces panel driving voltage power consumption. Driving Power Supply circuit consists Voltage converter, Voltage regulator, Voltage Power Supply Control Mode Voltage converter Enable Disable Disable Voltage regulator Enable Enable Voltage follower Enable Enable Enable Disable VOUT Internal voltage output Used Voltage Adjustment Internal voltage output
follower.
controlled power control instruction.
following table shows Driving Power Supply circuit
works power control instruction sets.
External
voltage input
Used Voltage Adjustment
Open
Open
Internal voltage output
internal voltage output external voltage input
external voltage input
Disable
Disable
Open
Open
Disable
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7.1. Voltage Converter
Voltage Converter circuit generates positive voltage level
internal VREF voltage regulator temperature compensation function, temperature coefficient is±0.03%/
times 1.8V that generated internally.
from voltage converter.
VOUT generated
This conversion voltage used
built-in Voltage regulator circuit.
same 3-times DC/DC converter.
This application circuit
VOUT
VOUT SPLC093A1 CAP1P 1.8V 7.2V 1.8V (Internal) CAP1N CAP2P CAP2N VOUT
VEXT VREF Inside Chip
DC/DC Converter Output Circuit
7.2. Voltage Regulator
Voltage Regulator circuit used obtain appropriate
panel driving voltage. This voltage obtained adjusting
Voltage Regulator Circuit
resistors shown equation (2), setting
electronic contrast control data bits, equation (4).
potential adjusted within VOUT VREF.
7.3. Electronic Contrast Control STEPS)
Electronic Contrast Control data bits (C4, C0). Voltage regulation adjusted 32-contrast steps according value Electronic Contrast Control data bits. driving
VREF internal constant voltage source chip this value 1.8V condition VDD2.4V
voltage, voltage values 5-bit data electronic contrast control register (ICONRAM address 10h).
When using Electronic Contrast Control function, voltage selects which voltage used voltage regulator
between external VEXT internal VREF. Voltage regulation adjusting resistors When "Low" VREF When "Low"
regulators need turned power control instruction.
VREF 2,.,
VREF /150 When "High"
When "High" VEXT
VEXT 2,.,
VEXT /150
Electronic Contrast Control Register Maximum Contrast High
0(default)
Minimum
("-": Don't care)
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VOUT
VEXT VREF
Inside Chip
Electronic Contrast Control Circuit
7.4. Voltage Generator Circuit
SPLC093C CAP1P CAP1N CAP2P CAP2N VOUT
4.7µF 4.7µF
When Built-in Power Supply used (VC,
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CAP1P CAP1N CAP2P External Power Supply CAP2N VOUT CAP1P CAP1N CAP2P CAP2N VOUT CAP1P CAP1N CAP2P CAP2N VOUT
(VC, External Power Supply (VC, capacitor 4.7µF External Power Supply
(VC,
When External Power Supply used
7.5. Interface
IORQ
Decoder
SPLC093C
DB[7:0]
RESET
RESET
Parallel Interfacing with 8080-series Microprocessors
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Decoder
DB[7:0] RESET
SPLC093C
RESET
Parallel Interfacing with 6800-series Microprocessors
PORT4 PORT3
PORT1 PORT2 RESET
SPLC093C
SCL(DB6) SI(DB7)
RESET
Clock Synchronized Serial Interfacing with Microprocessors
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ELECTRICAL SPECIFICATIONS
8.1. Absolute Maximum Ratings
Characteristic Power supply voltage Symbol VOUT, Value Unit
-0.3
-0.3
Power supply voltage
Power supply voltage Input voltage
-0.3
-0.3 VDD+0.3
normal operational
Operating temperature
Storage temperature
conditions AC/DC Electrical Characteristics. Note2: voltage levels based
TOPR
TSTG
+125
Note1: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
Voltage greater than above damage circuit. Voltage level: VOUTV0VDDVSS Voltage level: V0V1V2V3V4VSS
8.2. Characteristics
(VDD 2.4V 5.5V, +75) Item Operating Voltage Symbol Condition Min. Typ. Max. Unit
Display operation
IDD1
Supply Current (VDD 3.0V,
IDD2
VLCD 6.0V without load
access from
Access operation from (FCYC 200KHz)
Sleep operation without load
0.7VDD
1000
0.3VDD
IDDS1
Input Voltage
Oscillator off, Power save
Output Voltage
Input Leakage Current
Output Leakage Current
-1.0mA, 2.4V 1.0mA, 2.4V
VDD-0.4
-1.0
-3.0
RCOM
±50µA ±50µA
Resistance
RSEG
VOUT VREF
Frame frequency (Internal OSC) Voltage
Converter Conversion Efficiency
3.0V,
1.0µF
Output Voltage
Voltage regulator reference Voltage
Driving Voltage
1.70
1.75
1.80
VLCD
VLCD
Note1: RESET schmitt input (0.8VDDVIHVDD, VSSVIL0.2VDD).
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8.3. Characteristics 8.3.1. Parallel write interface Mode)
(VDD 2.4V 5.5V, +75)
Cycle Time Pulse Rise Fall Time Pulse Width High Symbol Min. Typ. Max. Unit
pulse Width
Setup Time
Hold Time
tSU1
tSU2
Setup Time
Hold Time
tSU1 tSU2
Valid Data
Write Timing Diagram Series)
8.3.2. Parallel read interface Mode)
(VDD 2.4V 5.5V, +75) Cycle Time Symbol Min. Typ. Max. Unit
Pulse Rise Fall Time Pulse Width High
pulse Width
Setup Time Hold Time
Output delay Time
Output Hold Time
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Valid Data
Read Timing Diagram Series)
8.3.3. Parallel write interface Mode)
(VDD 2.4V 5.5V, +75) Characteristic Symbol Min. Typ. Max. Unit
Cycle Time
Pulse Rise Fall Time Pulse Width High
Pulse Width
Setup Time
tSU1
tSU2
Hold Time
Setup Time
Hold Time
tSU1
tSU2 Valid Data
Write Timing Diagram Series)
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8.3.4. Parallel read interface Mode)
(VDD 2.4V 5.5V, +75)
Characteristic Cycle Time Pulse Rise Fall Time Symbol Min. Typ. Max. Unit
Pulse Width High Pulse Width Setup Time
Hold Time Output delay Time
Output Hold Time
Valid Data
Read Timing Diagram Series)
8.3.5. Clock synchronized serial mode
(VDD 2.4V 5.5V, +75) Characteristic Clock Cycle Time
Symbol
Min. 1000.0
Typ.
Max.
Unit
25.0
Pulse Rise Fall Time
Clock Width (High, Low)
300.0
150.0
tSU1
Setup Time Hold Time
Data Setup Time
Data Hold Time Data Setup Time
700.0 50.0
300.0 50.0
tSU2
tSU3
Data Hold Time
50.0
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tSU1
tSU2
tSU3
Clock synchronized serial Interface Mode Timing Diagram
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APPLICATION INFORMATION PANEL
9.1. Chip Bottom Lower View "0", DIRS "0")
COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1
SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG80 SEG79 SEG78 SEG77 SEG76
BOTTOM VIEW
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
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9.2. Chip Bottom Upper View "1", DIRS "1")
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM21 COM22 COM23 COM24 COMI2
BOTTOM VIEW
SEG71 SGE72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG1 SEG2 SEG3 SEG4 SEG5
COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20
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9.3. Chip Lower View "0", DIRS "1")
COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
COMI2 COM2 COM2 COM2 COM21
SEG1 SEG2 SEG3 SEG4 SEG5
SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8
COM20 COM1 COM1 COM1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1
VIEW
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9.4. Chip Upper View "1", DIRS "0")
COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM1 COM1 COM1 COM20
VIEW
SEG80 SEG79 SEG78 SEG77 SEG76 SEG1 SGE9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM21 COM2 COM2 COM24 COMI2
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FRAME FREQUENCY
10.1. 1/17 Duty (2-line mode)
1-line Selection Period Clocks Frame
Frame Frequency
36.8 10.0 Clock 36.8 fOSC =27.2KHz) 10.0
10.2. 1/25 Duty (3-line mode)
1-line Selection Period Clocks Frame 10.0 Clock fOSC =40KHz) 10.0
Frame Frequency
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CHARACTER GENERATOR
11.1. SPLC093C
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PACKAGE/PAD LOCATIONS
12.1. Assignment
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMI1 TEST2
SPLC093C
RESET
VEXT
VEXT
CAP2N
CAP2N
CAP1N
CAP1N
CAP2P
CAP2P
CAP1P
CAP1P
12.2. SPLC093C Dimensions
Item Size 6320 75.6 85.5 Unit
Chip Size
2020
75.6
pitch
Bumped size
50.4
85.5
50.4
60.3
85.5
Bumped height
Note1: Chip size included scribe line.
Note2: ensure function properly, please bond pins. Note3: 0.1µF capacitor between should placed close possible.
12.3. Ordering Information
Product Number SPLC093C-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type
Chip Form with Gold Bump
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VOUT
VOUT
DIRS
SPLC093C
12.4. Locations
Name COMI2 -3002 Name -845
COM24
-3002
VOUT
VOUT
-845
COM23
COM22
-3002
-3002
-845
-845
COM21 COM16
-3002
-3002
CAP2N
CAP2N
-845
-845 -845
-845
1008
COM15
COM14
-3002 -3002
-3002 -3002 -3002
-175 -251 -326 -402
CAP2P
CAP2P
COM13 COM12
COM11
CAP1N
CAP1N CAP1P
-845
-845
1093
1179
-845
-845
-845 -845 -845
COM10
-3002
-3002 -2926 -2840 -2623 -2537
CAP1P
VEXT
1264
1370
COM9
-477
-845 -845
VEXT
1451
1536
-845
-845 -845
DIRS
1622
1707
-845 -845
-845 -845 -845 -845 -845 -845 -845
-2347 -2205
-2061 -1918
1912
1999 2084
-845
-845
-845
2170
-1774
-1632
-845
-845
2374
2460
2677 2762 3002 2995
-1487
-1345
-845
-845
RESET
TEST1 TEST2 COMI1 COM1 COM2 COM3
-845
-1214 -1129 -1043
-958 -872
-787 -701
-616 -530
-845 -845
-845 -845 -845
-845
-616
3002
3002
-522
-447 -371
3002
3002
-845
-296
-220
-845
-845 -845 -845
COM4 COM5
COM6 COM7 COM8
3002
3002
-144
3002
3002
-445
-359
-274
-188 -103
-845
-845 -845 -845 -845
3002
COM17 COM18
COM19
3002
3002 3002
COM20
3002
2974 2899
-845
-845
-845
SEG1
SEG2 SEG3
2823
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Name SEG4 2748
Name SEG43 SEG44
-200
-275 -351
SEG5 SEG6
SEG7 SEG8
SEG9
2672 2596
2521
SEG45
SEG46
-427
-502 -578
2445
2370
SEG47
SEG48 SEG49 SEG50
SEG51 SEG52 SEG53
SEG10
SEG11 SEG12
2294
-653 -729
-805
2218
2143 2067 1992
SEG13
SEG14 SEG15
-880 -956
-1031 -1107
1916
1840 1765
1689
SEG54
SEG55
SEG16 SEG17
SEG18
SEG56
SEG57 SEG58 SEG59
-1183
-1258 -1334 -1409
SEG19 SEG20
SEG21 SEG22
1614
1538 1462
SEG60 SEG61
-1485 -1561
1387 1311
1236
SEG23
SEG24 SEG25 SEG26
SEG62
SEG63 SEG64
-1636
-1712
-1787
1160
1084 1009
SEG65
SEG66 SEG67
-1863 -1939
-2014
SEG27 SEG28
SEG29
SEG30
SEG31
SEG68
SEG69 SEG70
-2090
-2165 -2241
SEG32 SEG33
SEG71
SEG72
SEG73
-2317
-2392
SEG34 SEG35
SEG36
-2468
-2543 -2619
SEG74
SEG75 SEG76 SEG77
SEG78
SEG37
SEG38 SEG39
-2695 -2770
-2846 -2921 -2997
-124
SEG40
SEG41
SEG79 SEG80
SEG42
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHER, SUNPLUS MAKES WARRANTY
SUNPLUS reserves right halt production alter specifications
regarding freedom described chip(s) from patent infringement.
MERCHANTABILITY FITNESS PURPOSE.
prices time without notice.
Accordingly, reader cautioned verify that data sheets other information this
publication current before placing orders.
Products described herein intended normal commercial applications.
Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications.
illustrated this document reference purposes only.
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REVISION HISTORY
Date Revision Original Change "Code: "Code: CHARACTER GENERATOR (CGROM)" Delete "CHARACTER GENERATOR (SPLC093C-05)" Description Page
FEB. 2001
MAY. 2001
JUL. 2001
Delete "PRELIMINARY"
"with Gold Bump" "12.3 Ordering Information"
Renew document format
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26COM/80SEG Controller/Driver JUL. 2001 Version SUNPLUS TECH

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