700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
FOUT FOUT/2 differential 3.3V LVPECL outputs Selectable CLK, nCLK pair LVCMOS reference inputs CLK, nCLK pair accept following differential input levels: LVPECL, LVHSTL, LVDS, SSTL, HCSL Maximum FOUT frequency 700MHz Maximum FOUT/2 frequency 350MHz 14MHz 25MHz differential input reference input frequency range: 250MHz 700MHz Parallel serial interface programming counter frequency multiplier dividers 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-111 general purpose, dual output Differential-to-3.3V LVPECL High Frequency HiPerClockSSynthesizer member HiPerClockSfamily High Performance Clocks Solutions from ICS. operates frequency range 250MHz 700MHz. frequency programmed steps equal value input differential single ended reference frequency. Output frequencies 700MHz FOUT 350MHz FOUT/2 programmed using serial parallel interfaces configuration logic. phase noise characteristics multiple frequency outputs ICS8432-111 makes ideal clock source Fiber Channel Infiniband applications.
BLOCK DIAGRAM
VCO_SEL
ASSIGNMENT
VCO_SEL nP_LOAD nCLK
CLK_SEL TEST_CLK nCLK
TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK
ICS8432-111
PHASE DETECTOR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
FOUT nFOUT FOUT/2 nFOUT/2
TEST FOUT/2 nFOUT/2 VCCO FOUT nFOUT
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz clock input. Valid loop divider values different input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-111 features fully integrated therefore requires external component setting loop bandwidth. differential clock input used input ICS8432-111. This input into phase detector. 25MHz clock input provides 25MHz phase detector reference frequency. operates over range 250MHz 700MHz. output loop divider also applied phase detector. phase detector loop filter divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low) will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-111 support input modes programmable loop divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through passed directly ripple counter. LOW-to-HIGH transition nP_LOAD input data latched ripple counter remains loaded until next transition nP_LOAD until serial event occurs. result bits hardwired ripple counter specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, input frequency loop divider defined follows: fVCO count required values through shown Table Programmable Frequency Function. Valid values which will achieve lock defined frequency defined follows: fOUT fVCO Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into ripple counter when S_LOAD transitions from LOW-to-HIGH. ripple counter divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH data S_DATA input passed directly ripple counter each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout/2
S_DATA S_CLOCK
NULL
S_LOAD M0:M8, N0:N1 nP_LOAD
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE:
8432BY-111
NULL timing slot must observed.
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Input Input Input Power Input Input Input Input Input Input Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pullup counter/divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function table. LVCMOS LVTTL interface levels. connect Negative supply pins. Connect ground. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive supply pin. Half frequency differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Connect 3.3V. Differential output synthesizer. 3.3V LVPECL interface levels. Forces outputs LOW, does effect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLK. Shift register serial input. Data sampled rising edge S_CLK. Controls transition data from shift register into ripple counter. LVCMOS LVTTL interface levels. Analog supply pin. Connect 3.3V. Selects between differential clock input test input reference source. LVCMOS LVTTL interface levels. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS LVTTL interface levels. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT/2, nFOUT/2 VCCO FOUT, nFOUT S_CLOCK S_DATA S_LOAD VCCA CLK_SEL TEST_CLK nCLK nP_LOAD VCO_SEL
Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Parallel load input. Determines when data present M8:M0 Pulldown loaded into ripple counter, when data present N1:N0 sets output divide value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol Parameter TEST_CLK, CLK, nCLK M0:M8, N0:N1, Input Capacitance S_LOAD, S_DATA, nP_LOAD, S_CLOCK, VCO_SEL, CLK_SEL Input Pullup Resistor Input Pulldown Resistor
Test Conditions
Minimum Typical
Maximum
Units
RPULLUP RPULLDOWN
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Inputs
TABLE PARALLEL
nP_LOAD
SERIAL MODES FUNCTION TABLE
Data S_LOAD S_CLOCK S_DATA Conditions Reset. counters reset. Data inputs passed directly ripple counter output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed ripple counter output divider. Ripple counter output divide values latched. Parallel serial input affect shift registers.
Data
Data
Data
Data Data Data
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Count
NOTE These count values resulting frequency correspond differential input test clock input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs Divider Value Minimum 62.5 31.25 Output Frequency (MHz) FOUT Maximum 87.5 Minimum 62.5 31.25 15.625 FOUT/2 Maximum 87.5 43.75
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V 0.5V 47.9°C/W -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these condition conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VCCA VCCO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 3.135
70°C
Maximum 3.465 3.465 3.465 Units
Typical
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Voltage VCO_SEL, XTAL_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK Input Voltage VCO_SEL, XTAL_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, XTAL_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, XTAL_SEL, VCO_SEL Output High Voltage TEST Test Conditions 3.465V 3.465V 3.135V 3.135V *VCCx 3.465V *VCCx 3.465V *VCCx 3.465V, *VCCx 3.465V, *VCCx 3.135V, -36mA *VCCx 3.135V, 36mA
70°C
Maximum 3.765 3.765 Units
Minimum -0.3
Typical
Input High Current
Input Current
-150
Output TEST Voltage *NOTE: VCCx denotes VCC, VCCA, VCCO.
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Current Input Current nCLK nCLK Test Conditions 3.465V 3.465V -150 Minimum
70°C
Maximum Units
Typical
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.13 VCMR NOTE NOTE Common mode voltage defined VIH. NOTE single ended applications maximum input voltage nCLK 0.3V.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions
70°C
Typical Maximum VCCO VCCO 0.85 Units
Minimum VCCO VCCO
NOTE Outputs terminated with VCCO
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Test Conditions
70°C
Typical Maximum Units
Minimum
TEST_CLK; NOTE Maximum Input Frequency CLK, nCLK; NOTE S_CLOCK NOTE differential input test clock input frequency range value must operate within 250MHz 700MHz range. Using minimum input frequency 14MHz valid values Using maximum frequency 25MHz valid values
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol FOUT Parameter Maximum Output Frequency Accumulative Period Jitter, RMS; NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Duty Cycle Output Rise Time Output Fall Time Setup Time Hold Time Lock Time
70°C
Minimum 31.25 Typical Maximum Units
Test Conditions
jit(acc) jit(per) sk(o)
tLOCK
Pulse Width parameters measured 500MHz unless noted otherwise. NOTE Jitter performance using TEST_CLK input. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
8432BY-111
REV. AUGUST 2001
ICS8432-111
700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432AY-111 ICS8432AY-111 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432AY-111 ICS8432AY-111T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432BY-111
REV. AUGUST 2001

700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER F

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