700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER FEATURES F

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700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER FEATURES F

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ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
FEATURES
FOUT0 FOUT1 differential 3.3V LVPECL outputs Selectable CLK, nCLK LVCMOS reference inputs CLK, nCLK pair accept following differential input levels: LVPECL, LVHSTL, LVDS, SSTL Maximum output frequency: 31.25MHz 700MHz Differential input reference input frequency: 14MHz 25MHz range: 250MHz 700MHz Accepts single-ended input signal LVCMOS with resistor bias nCLK input Parallel interface programming counter output dividers 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-101 general purpose, dual output high frequency synthesizer member HiPerClockSthe HiPerClockSfamily High Performance Clocks Solutions from ICS. operates frequency range 250MHz 700MHz. frequency programmed steps equal value input differential single ended reference frequency. output frequency programmed using serial parallel interfaces configuration logic. phase noise characteristics ICS8432-101 makes ideal clock source Gigabit Ethernet, Fiber Channel Infiniband Sonet OC12 applications.
BLOCK DIAGRAM
VCO_SEL CLK_SEL TEST_CLK nCLK
ASSIGNMENT
VCO_SEL nP_LOAD nCLK
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK
PHASE DETECTOR
FOUT0 nFOUT0 FOUT1 nFOUT1
ICS8432-101
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm Package Body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz clock input. Valid loop divider values different input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-101 features fully integrated therefore requires external component setting loop bandwidth. differential clock input used input ICS8432-101. This input into phase detector. 25MHz clock input provides 25MHz phase detector reference frequency. operates over range 250MHz 700MHz. output loop divider also applied phase detector. phase detector loop filter divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low) will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-101 support input modes programmable loop divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through passed directly ripple counter. LOW-to-HIGH transition nP_LOAD input data latched ripple counter remains loaded until next transition nP_LOAD until serial event occurs. result bits hardwired ripple counter specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, input frequency loop divider defined follows: fVCO count required values through shown Table Programmable Frequency Function. Valid values which will achieve lock defined frequency defined follows: fOUT fVCO Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into ripple counter when S_LOAD transitions from LOW-to-HIGH. ripple counter divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH data S_DATA input passed directly ripple counter each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout
S_DATA S_CLOCK S_LOAD
*NULL
M0:M8, N0:N2 nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE: NULL timing slot must observed.
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Input Input Input Power Input Input Input Input Input Input Pullup Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pullup counter/divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function table. LVCMOS LVTTL interface levels. connect. Negative supply pin. Connect ground. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Connect 3.3V. Differential output synthesizer. 3.3V LVPECL interface levels. Forces outputs LOW, does effect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLK. Shift register serial input. Data sampled rising edge S_CLK. Controls transition data from shift register into ripple counter. LVCMOS LVTTL interface levels. Analog supply pin. Connect 3.3V. Clock select input. Selects between differential clock input test input reference source. When HIGH, selects CLK, nCLK inputs. When LOW, selects TEST_CLK input. LVCMOS LVTTL interface levels. Test clock input. LVCMOS LVTTL interface levels. Non-inver ting differential clock input. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 S_CLOCK S_DATA S_LOAD VCCA CLK_SEL TEST_CLK nCLK nP_LOAD VCO_SEL
Inver ting differential clock input. Parallel load input. Determines when data present M8:M0 Pulldown loaded into ripple counter, when data present N1:N0 sets output divide value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refers internal input resistors. Table Characterisitics, typical values.
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
Test Conditions TEST_CLK, CLK, nCLK M0:M8, S_LOAD, N0:N1, S_DATA, VCO_SEL, CLK_SEL, nP_LOAD, S_CLOCK Minimum Typical Maximum Units
TABLE CHARACTERISTICS
Symbol Parameter
Input Capacitance
RPULLUP RPULLDOWN
Input Pullup Resistor Input Pulldown Resistor
TABLE PARALLEL
nP_LOAD
SERIAL MODES FUNCTION TABLE
Inputs Data S_LOAD S_CLOCK S_DATA Conditions Reset. counters reset. Data inputs passed directly ripple counter output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed ripple counter output divider. Ripple counter output divide values latched. Parallel serial input affect shift registers.
Data
Data
Data
Data Data Data
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Count
NOTE These count values resulting frequency correspond differential input test clock input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs Divider Value Output Frequency (MHz) Minimum Maximum 62.5 31.25 87.5
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V VCCO 0.5V 46°C/W -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation product these condition conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol VCC, VCCA, VCCO ICCA Parameter Power Supply Voltage Power Supply Current Analog Power Supply Current Test Conditions Minimum 3.135
70°C
Maximum 3.465 Units
Typical
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter Input High Current Input Current nCLK nCLK Test Conditions 3.465V 3.465V -150 Minimum
70°C
Maximum Units
Typical
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage NOTE single ended applications maximum input voltage CLK, nCLK 0.3V. NOTE Common mode voltage defined VIH.
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum -0.3 Typical Maximum 3.765 3.765 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK Input Voltage VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, N0:N1, M0:M8, TEST_CLK M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, CLK_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, S_DATA, S_LOAD, TEST_CLK, nP_LOAD, CLK_SEL, VCO_SEL Output High Voltage Output Voltage TEST TEST
VCCI 3.465V VCCI 3.465V VCCI 3.135V VCCI 3.135V *VCCx 3.465V *VCCx 3.465V *VCCx 3.465V, *VCCx 3.465V, *VCCx 3.135V, -36mA *VCCx 3.135V, 36mA
Input High Current
Input Current
-150
*NOTE VCCx denotes VCC, VCCA, VCCO.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Test Conditions Minimum FOUT0, Output High Voltage; nFOUT0 *VCCx 3.3V NOTE FOUT1, nFOUT1 FOUT0, Output Voltage; nFOUT0 *VCCx 3.3V NOTE FOUT1, nFOUT1 FOUT0, Peak-to-Peak nFOUT0 VSWING 3.135V *VCCx 3.465V Output Voltage Swing FOUT1, nFOUT1 NOTE FOUT0, nFOUT0, FOUT1, nFOUT1 outputs terminated with VCCO power dissipation terminated output pair 32mW. *NOTE VCCx denotes VCC, VCCA, VCCO. Symbol Parameter Typical Maximum Units
0.85
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol Parameter TEST_CLK; NOTE CLK, nCLK; NOTE S_CLOCK TEST_CLK CLK, nCLK TEST_CLK CLK, nCLK TEST_CLK Measured point Measured points Test Conditions
70°C
Typical Maximum Units
Minimum
Maximum Input Frequency
Input Rise Time Input Fall Time Input Reference Duty Cycle
CLK, nCLK NOTE differential input reference frequency range value must operate within 250MHz 700MHz range. Using minimum input frequency 14MHz valid values Using maximum frequency 25MHz valid values
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%,
Symbol FOUT Parameter Maximum Output Frequency Accumulative Period Jitter, RMS; NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Duty Cycle FOUT0, nFOUT0 Output Rise Time FOUT1, nFOUT1 FOUT0, nFOUT0 Output Fall Time FOUT1, nFOUT1 nP_LOAD S_DATA Setup Time S_CLOCK S_CLOCK S_LOAD nP_LOAD S_DATA Hold Time S_CLOCK S_CLOCK S_LOAD Lock Time Pulse Width nP_LOAD Test Conditions
70°C
Minimum 31.25 Typical Maximum Units
tjit(acc) tjit(per) tsk(o)
tLOCK
S_LOAD NOTE Jitter performance using TEST_CLK input. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross point.
8432AY-101
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL
Reference Document: JEDEC Publication MS-026
8432AY-101
MINIMUM
NOMINAL
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0.60 0.75 0.10 1.40 0.37 0.15 1.45 0.45 0.20
REV. JULY 2001
ICS8432-101
700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432AY-101 ICS8432AY-101 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432AY-101 ICS8432AY-101T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432AY-101
REV. JULY 2001

700MHZ, PHASE NOISE, LVPECL FREQUENCY SYNTHESIZER FEATURES F

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