dual UART, Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, Mot

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dual UART, Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, Mot

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SC68C652B
dual UART, Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, Motorola interface
Rev. April 2005 Product data sheet
SC68C652B channel Universal Asynchronous Receiver Transmitter (UART) used serial data communications. principal function convert parallel data into serial data vice versa. UART handle serial data rates Mbit/s. SC68C652B compatible with SC68C2550B. SC68C652B provides enhanced UART functions with 32-byte FIFOs, modem control interface, mode data transfer, infrared (IrDA) encoder/decoder. mode data transfer controlled FIFO trigger levels TXRDY RXRDY signals. On-board status registers provide user with error indications operational status. System interrupts modem control features tailored software meet specific user requirements. internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators provided select transmit receive baud rates. SC68C652B operates industrial temperature range, available plastic LQFP48 package.
Features
channel UART with Motorola® interface operation tolerant inputs Industrial temperature range (-40 Software compatible with industry standard 16C450, 16C550, SC16C650 Mbit/s baud rate Mbit/s 32-byte transmit FIFO reduce bandwidth requirement external 32-byte receive FIFO with error flags reduce bandwidth requirement external Independent transmit receive UART control Four selectable receive transmit FIFO interrupt trigger levels Automatic software (Xon/Xoff) hardware (RTS/CTS) flow control Programmable Xon/Xoff characters Software selectable baud rate generator Standard modem interface infrared IrDA encoder/decoder interface Supports IrDA version 115.2 kbit/s) Sleep mode Standard asynchronous error framing bits (Start, Stop, Parity Overrun Break) Transmit, Receive, Line Status, Data interrupts independently controlled
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Fully programmable character formatting: 8-bit characters Even, odd, parity formats 11/2, stop generation Baud generation Mbit/s) False start detection Complete status reporting capabilities 3-state output drive capabilities bi-directional data control Line break generation detection Internal diagnostic capabilities: Loop-back controls communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR,
Ordering information
Table Ordering information Package Name SC68C652BIB48 LQFP48 Description plastic profile quad flat package; leads; body Version SOT313-2 Type number
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Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Block diagram
SC68C652B
TRANSMIT FIFO REGISTER RESET DATA CONTROL LOGIC FLOW CONTROL LOGIC ENCODER TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
FLOW CONTROL LOGIC
DECODER
DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC
TXRDYA, TXRDYB RXRDYA, RXRDYB
INTERRUPT CONTROL LOGIC
CLOCK BAUD RATE GENERATOR
CTSA, CTSB RIA, CDA, DSRA, DSRB
002aab323
XTAL1
XTAL2
Block diagram SC68C652B
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Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Pinning information
Pinning
TXRDYA
DSRA
CTSA
TXRDYB OP2B
n.c. RESET DTRB DTRA RTSA OP2A RXRDYA n.c. n.c.
002aab324
Koninklijke Philips Electronics N.V. 2005. rights reserved.
SC68C652BIB48
n.c. XTAL1 XTAL2 RXRDYB DSRB RTSB CTSB
configuration LQFP48
description
Table Symbol CDA, description Type Description Address select bit. Internal registers address selection. Address select bit. Internal registers address selection. Address select bit. Internal registers address selection. Address select bit. used select Channel Channel logic selects Channel logic HIGH selects Channel (See Table Carrier Detect (active LOW). These inputs associated with individual UART channels logic these pins indicates that carrier been detected modem that channel. Chip Select (active LOW). This enables data transfers between user SC68C652B channel(s) addressed. Individual UART sections addressed Table Clear Send (active LOW). These inputs associated with individual UART channels logic (LOW) pins indicates modem data ready accept transmit data from SC68C652B. Status tested reading MSR[4]. These pins have effect UART's transmit receive operation.
CTSA, CTSB
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Table Symbol
description .continued Type Description Data (bi-directional). These pins 8-bit, 3-state data transferring information from controlling CPU. least significant first data transmit receive serial data stream. Data Ready (active LOW). These inputs associated with individual UART channels logic (LOW) these pins indicates modem data powered-on ready data exchange with UART. These pins have effect UART's transmit receive operation. Data Terminal Ready (active LOW). These outputs associated with individual UART channels logic (LOW) these pins indicates that SC68C652B powered-on ready. These pins controlled modem control register. Writing logic MCR[0] will output logic (LOW), enabling modem. output these pins will logic after writing logic MCR[0], after reset. These pins have effect UART's transmit receive operation. Signal power ground Interrupt Request. Interrupts from UART channels wire-ORed internally function single interrupt. This transitions logic enabled interrupt enable register) whenever UART channel(s) requires service. Individual channel interrupt status determined addressing each channel through associated internal register, using external pull-up resistor must connected between this VCC. logic this will transfer contents data (D[0:7]) from external internal register that defined address bits A[0:2]. logic HIGH this will load contents internal register defined address bits A[0:2] SC68C652B data (D[0:7]) access external CPU. connected Output (user-defined). This function associated with individual channels state these pins defined user through software settings MCR[3]. OP2A/OP2B logic when MCR[3] logic OP2A/OP2B logic when MCR[3] logic output these pins HIGH after reset. Reset (active LOW). This will reset internal registers outputs. UART transmitter output receiver input will disabled during reset time. Section 7.11 "SC68C652B external reset condition" initialization details. Ring Indicator (active LOW). These inputs associated with individual UART channels logic these pins indicates modem received ringing signal from telephone line. logic transition these input pins generates interrupt. Request Send (active LOW). These outputs associated with individual UART channels, logic indicates transmitter data ready waiting send. Writing logic modem control register MCR[1] will this logic indicating data available. After reset these pins logic These pins have effect UART's transmit receive operation. Receive data input. These inputs associated with individual serial channel data SC68C652B receive input circuits signal will logic during reset, idle data), when transmitter disabled. During local loop-back mode, these input pins disabled data connected UART input internally. Receive Ready (active LOW). RXRDYA RXRDYB goes when trigger level been reached FIFO least character. goes HIGH when FIFO empty.
Koninklijke Philips Electronics N.V. 2005. rights reserved.
DSRA, DSRB
DTRA, DTRB
n.c. OP2A, OP2B
RESET
RIA,
RTSA, RTSB
RXA,
RXRDYA, RXRDYB
9397 14657
Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Table Symbol TXA,
description .continued Type Description Transmit data These outputs associated with individual serial transmit channel data from SC68C652B. signal will logic during reset, idle data), when transmitter disabled. During local loop-back mode, output pins disabled data internally connected UART input. Transmit Ready (active LOW). These outputs provide FIFO/THR status individual transmit channels TXRDYn primarily intended monitoring mode transfers transmit data FIFOs. individual channel's TXRDYA, TXRDYB buffer ready status indicated logic that least location empty available FIFO THR. This goes logic (DMA mode when there more empty locations FIFO THR. This signal also used single mode transfers (DMA mode Power supply input. Crystal external clock input. Functions crystal input external clock input. crystal connected between this XTAL2 form internal oscillator circuit (see Figure This configuration requires external resistor between XTAL1 XTAL2 pins. Alternatively, external clock connected this provide custom data rates. Section "Programmable baud rate generator". Output crystal oscillator buffered clock. (See also XTAL1.) XTAL2 used crystal oscillator output buffered clock output. Should left open external clock connected XTAL1. extended frequency operation, this should tied resistor.
TXRDYA, TXRDYB
XTAL1
XTAL2
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Functional description
SC68C652B UART pin-compatible with SC68C2550B UART. provides more enhanced features. additional features provided through special enhanced feature register. UART will perform serial-to-parallel conversion data characters received from peripheral devices modems, parallel-to-parallel conversion data characters transmitted processor. complete status each channel SC68C652B UART read time during functional operation processor. SC68C652B placed alternate mode (FIFO mode) relieving processor excessive software overhead buffering received/transmitted characters. Both receiver transmitter FIFOs store bytes (including three additional bits error status byte receiver FIFO) have selectable programmable trigger levels. Primary outputs RXRDY TXRDY allow signalling transfers. SC68C652B selectable hardware flow control software flow control. Hardware flow control significantly reduces software overhead increases system efficiency automatically controlling serial data flow using output input signals. Software flow control automatically controls data flow using programmable Xon/Xoff characters. UART includes programmable baud rate generator that divide timing reference clock input divisor between (216
UART functions
UART provides user with capability bi-directionally transfer information between external CPU, SC68C652B package, external serial device. logic chip select (LOW HIGH) allows user configure, send data, and/or receive data UART channels Individual channel select functions shown Table
Table Channel selection using UART channel none Channel Channel
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Internal registers
SC68C652B provides sets internal registers consisting registers each monitoring controlling functions each channel UART. These registers shown Table UART registers function data holding registers (THR/RHR), interrupt status control registers (IER/ISR), FIFO control register (FCR), line status control registers (LCR/LSR), modem status control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), user accessible scratchpad register (SPR), along with advanced feature registers Xon1, Xon2, Xoff1 Xoff2.
Table
Internal registers decoding Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM) Divisor Latch Divisor Latch Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word Divisor Latch Divisor Latch Enhanced Feature Register Xon1 word Xon2 word Xoff1 word Xoff2 word Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register
General register (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
Baud rate register
Enhanced register (EFR, Xon1, Xon2, Xoff1, Xoff2)
These registers accessible only when LCR[7] logic These registers accessible only when LCR[7] logic Enhanced Feature Register, Xon1, Xon2, Xoff1, Xoff2 accessible only when `BFh'.
FIFO operation
32-byte transmit receive data FIFOs enabled FIFO Control Register (FCR[0]). With SC68C2550B devices, user receive trigger level, transmit trigger level. SC68C652B provides independent trigger levels both receiver transmitter. remain compatible with SC68C2550B, transmit interrupt trigger level following reset. should noted that user transmit trigger levels writing register, activation will take place until EFR[4] logic receiver FIFO section includes time-out function ensure data delivered external CPU. interrupt generated whenever Receive Holding Register (RHR) been read following loading character receive trigger level been reached.
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Flow control mechanism activation Negate send Xoff Assert send
Table
Selected trigger level (characters)
Hardware flow control
When automatic hardware flow control enabled, SC68C652B monitors remote buffer overflow indication controls local buffer overflows. Automatic hardware flow control selected setting EFR[6] (RTS) EFR[7] (CTS) logic transitions from logic logic indicating flow control request, ISR[5] will logic enabled IER[6:7]), SC68C652B will suspend transmissions soon stop character process shifted out. Transmission resumed after input returns logic indicating more data sent. With Auto-RTS function enabled, interrupt generated when receive FIFO reaches programmed trigger level. will forced logic (RTS off), until receive FIFO reaches next trigger level. However, will return logic after data buffer (FIFO) unloaded next trigger level below programmed trigger level. However, under above described conditions, SC68C652B will continue accept data until receive FIFO full.
Software flow control
When software flow control enabled, SC68C652B compares sequential receive data characters with programmed Xoff character value(s). received character(s) match programmed Xoff values, SC68C652B will halt transmission (TX) soon current character(s) completed transmission. When match occurs, receive ready enabled Xoff IER[5]) flags will interrupt output receive interrupt enabled) will activated. Following suspension match Xoff characters' values, SC68C652B will monitor receive data stream match Xon1/Xon2 character value(s). match found, SC68C652B will resume operation clear flags (ISR[4]). Reset initially sets contents Xon/Xoff 8-bit flow control registers logic Following reset, user write Xon/Xoff value desired software flow control. Different conditions detect Xon/Xoff characters suspend/resume transmissions. When double 8-bit Xon/Xoff characters selected, SC68C652B compares consecutive receive characters with software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) controls transmissions accordingly. Under above described flow control mechanisms, flow control characters placed (stacked) user accessible data buffer FIFO. When using software flow control, Xon/Xoff characters cannot used data transfer. event that receive buffer overfilling flow control needs executed, SC68C652B automatically sends Xoff message (when enabled) serial output remote modem. SC68C652B sends Xoff1/Xoff2 characters soon
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
received data passes programmed trigger level. clear this condition, SC68C652B will transmit programmed Xon1/Xon2 characters soon receive data drops below programmed trigger level.
Special feature software flow control
special feature provided detect 8-bit character when EFR[5] set. When 8-bit character detected, will placed user-accessible data stack along with normal incoming data. This condition selected conjunction with EFR[3:0]. Note that software flow control should turned when using this special mode setting EFR[3:0] logic SC68C652B compares each incoming receive character with Xoff2 data. match exists, received data will transferred FIFO, ISR[4] will indicate detection special character. Although Table "SC68C652B internal registers" shows each X-register with eight bits character information, actual number bits dependent programmed word length. Line Control Register bits LCR[0:1] define number character bits, that either bits, bits, bits bits. word length selected LCR[0:1] also determine number bits that will used special character comparison. X-registers corresponds with receive character.
Hardware/software time-out interrupts
interrupts enabled IER[0:3]. Care must taken when handling these interrupts. Following reset, Interrupt Enable Register (IER) SC68C652B will issue Transmit Holding Register interrupt. This interrupt must serviced prior continuing operations. register provides current singular highest priority interrupt only. could noted that interrupts have lowest interrupt priority. condition exist where higher priority interrupt mask lower priority CTS/RTS interrupt(s). Only after servicing higher pending interrupt will lower priority CTS/RTS interrupt(s) reflected status register. Servicing interrupt without investigating further interrupt conditions result data errors. When interrupt conditions have same priority, important service these interrupts correctly. Receive Data Ready Receive Time have same interrupt priority (when enabled IER[0]). receiver issues interrupt after number characters have reached programmed trigger level. this case, SC68C652B FIFO hold more characters than programmed trigger level. Following removal data byte, user should re-check LSR[0] additional characters. Receive Time will occur receive FIFO empty. time-out counter reset center each stop received each time receive holding register (RHR) read. actual time-out value character time, including data information length, start bit, parity bit, size stop bit, that times.
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Programmable baud rate generator
SC68C652B supports high speed modem technologies that have increased input data rates employing data compression schemes. example, 33.6 kbit/s modem that employs data compression require 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression need input data rate 460.8 kbit/s. SC68C652B support standard data rate 921.6 kbit/s. single baud rate generator provided transmitter receiver, allowing independent TX/RX channel control. programmable Baud Rate Generator capable operating with frequency MHz. obtain maximum data rate, necessary full rail swing clock input. SC68C652B configured internal external clock operation. internal clock oscillator operation, industry standard microprocessor crystal connected externally between XTAL1 XTAL2 pins. Alternatively, external clock connected XTAL1 clock internal baud rate generator standard custom rates (see Table generator divides input clock divisor from (216 SC68C652B divides basic external clock basic clock provides table rates support standard custom applications using same system design. rate table configured internal register functions. Customized baud rates achieved selecting proper divisor values sections baud rate generator. Programming Baud Rate Generator Registers (MSB) (LSB) provides user capability selecting desired final baud rate. example Table shows selectable baud rate table available when using 1.8432 external clock input.
XTAL1
XTAL2
1.8432
002aab325
Crystal oscillator connection
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Product data sheet
Rev. April 2005
Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Baud rate generator programming table using 1.8432 clock Output clock divisor (decimal) 2304 1536 1047 Output clock divisor (HEX) program value (HEX) program value (HEX)
Table Output baud rate 1200 2400 3600 4800 7200 9600 19.2 38.4 57.6 115.2
operation
SC68C652B FIFO trigger level provides additional flexibility user block mode operation. user optionally operate transmit receive FIFOs mode (FCR[3]). mode affects state RXRDY TXRDY output pins. Table Table show this.
Table Effect mode state RXRDY mode 0-to-1 transition when FIFO empties 1-to-0 transition when FIFO reaches trigger level, time-out occurs
Non-DMA mode FIFO empty least byte FIFO
Table
Effect mode state TXRDY mode 0-to-1 transition when FIFO becomes full 1-to-0 transition when FIFO goes below trigger level
Non-DMA mode least byte FIFO FIFO empty
6.10 Loop-back mode
internal loop-back capability allows on-board diagnostics. loop-back mode, normal modem interface pins disconnected reconfigured loop-back internally (see Figure MCR[0:3] register bits used controlling loop-back diagnostic testing. loop-back mode, transmitter output (TX) receiver input (RX) disconnected from their associated interface pins, instead connected together internally. CTS, DSR, disconnected from their normal modem control inputs pins, instead connected internally RTS, DTR, MCR[3] (OP2)
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
MCR[2] (OP1). Loop-back test data entered into transmit holding register user data interface, transmit UART serializes data passes serial data receive UART internal loop-back connection. receive UART converts serial data back into parallel data that then made available user data interface user optionally compares received data initial transmitted data verifying error-free operation UART TX/RX circuits. this mode, receiver transmitter interrupts fully operational. Modem Control Interrupts also operational.
SC68C652B
TRANSMIT FIFO REGISTERS RESET DATA CONTROL LOGIC FLOW CONTROL LOGIC ENCODER TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTERS
RECEIVE SHIFT REGISTER
MCR[4]
RXA,
REGISTER SELECT LOGIC
FLOW CONTROL LOGIC
DECODER
RTSA, RTSB
CTSA, CTSB DTRA, DTRB MODEM CONTROL LOGIC TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK BAUD RATE GENERATOR
DSRA, DSRB (OP1A, OP1B)
RIA, (OP2A, OP2B)
CDA,
002aab326
XTAL1 XTAL2
Internal loop-back mode diagram
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Register descriptions
Table details assigned functions SC68C652B internal registers. assigned functions more fully defined Section through Section 7.11.
Table SC68C652B internal registers interrupt
Register Default General Register interrupt
Xoff interrupt
Sleep mode
modem status interrupt mode select priority parity enable
receive line status interrupt XMIT FIFO reset priority
transmit holding register interrupt RCVR FIFO reset priority
receive holding register FIFOs enable status word length receive data ready Cont-0 Control
RCVR trigger (MSB) FIFOs enabled divisor latch enable clock select FIFO data error AutoCTS
RCVR trigger (LSB) FIFOs enabled
trigger (MSB) priority
trigger (LSB) priority
break parity even parity IRDA enable
stop bits word length (OP1) parity error Cont-2 Control overrun error Cont-1 Control
loop back control break interrupt framing error
empty empty AutoRTS
Special Register
Enhanced Register
Cont-3 Special Enable character IER[4:7], detect ISR[4:5], Control FCR[4:5], MCR[5:7]
Xon1 Xon2 Xoff1 Xoff2
value shown represents register's initialized value; applicable. Accessible only when LCR[7] logic These bits only accessible when EFR[4] set. Baud rate registers accessible only when LCR[7] logic Enhanced Feature Register, Xon1/Xon2 Xoff1/Xoff2 accessible only when `BFh'.
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Transmit (THR) Receive (RHR) Holding Registers
serial transmitter section consists 8-bit Transmit Hold Register (THR) Transmit Shift Register (TSR). status provided Line Status Register (LSR). Writing transfers contents data (D[7:0]) UART THR, providing that empty. empty flag register will logic when transmitter empty when data transferred TSR. Note that write operation performed when empty flag (logic least byte FIFO/THR, logic FIFO/THR empty). serial receive section also contains 8-bit Receive Holding Register (RHR) Receive Serial Shift Register (RSR). Receive data removed from SC68C652B receive FIFO reading register. receive section provides mechanism prevent false starts. falling edge start false start bit, internal receiver counter starts counting clocks clock rate. After 71/2 clocks, start time should shifted center start bit. this time start sampled, still logic validated. Evaluating start this manner prevents receiver from assembling false character. Receiver status codes will posted LSR.
Interrupt Enable Register (IER)
Interrupt Enable Register (IER) masks interrupts from receiver ready, transmitter empty, line status modem status registers. These interrupts would normally seen output pin.
Table Interrupt Enable Register bits description Symbol IER[7] Description interrupt logic disable interrupt (normal default condition) logic enable interrupt. SC68C652B issues interrupt when transitions from logic logic IER[6] interrupt logic disable interrupt (normal default condition) logic enable interrupt. SC68C652B issues interrupt when transitions from logic logic IER[5] Xoff interrupt logic disable software flow control, receive Xoff interrupt (normal default condition) logic enable software flow control, receive Xoff interrupt IER[4] Sleep mode logic disable Sleep mode (normal default condition) logic enable Sleep mode IER[3] Modem Status Interrupt. This interrupt will issued whenever there modem status change reflected MSR[0:3]. logic disable modem status register interrupt (normal default condition) logic enable modem status register interrupt
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Interrupt Enable Register bits description .continued Symbol IER[2] Description Receive Line Status interrupt. This interrupt will issued whenever receive data error condition exists reflected LSR[1:4]. logic disable receiver line status interrupt (normal default condition) logic enable receiver line status interrupt
Table
IER[1]
Transmit Holding Register interrupt. 16C450 mode, this interrupt will issued whenever empty, associated with LSR[5]. FIFO modes, this interrupt will issued whenever FIFO empty. logic disable Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic enable TXRDY (ISR level interrupt
IER[0]
Receive Holding Register. 68C450 mode, this interrupt will issued when data, cleared when empty. FIFO mode, this interrupt will issued when FIFO reached programmed trigger level cleared when FIFO drops below trigger level. logic disable receiver ready (ISR level RXRDY) interrupt (normal default condition) logic enable RXRDY (ISR level interrupt
7.2.1 versus Transmit/Receive FIFO interrupt mode operation
When receive FIFO (FCR[0] logic receive interrupts (IER[0] logic enabled, receive interrupts register status will reflect following:
receive RXRDY interrupt (Level interrupt) issued external
when receive FIFO reached programmed trigger level. will cleared when receive FIFO drops below programmed trigger level.
Receive FIFO status will also reflected user accessible register when
receive FIFO trigger level reached. Both register receive status interrupt will cleared when FIFO drops below trigger level.
receive data ready (LSR[0]) soon character transferred from
shift register (RSR) receive FIFO. reset when FIFO empty.
When Transmit FIFO interrupts enabled, interrupt generated when
transmit FIFO empty unloading data UART transmission transmission media. interrupt cleared either reading register, loading with data characters.
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Product data sheet
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
7.2.2 versus Receive/Transmit FIFO polled mode operation
When FCR[0] logic resetting IER[0:3] enables SC68C652B FIFO polled mode operation. this mode, interrupts generated user must poll register and/or data status. Since receiver transmitter have separate bits either both used polled mode selecting respective transmit receive control bit(s).
LSR[0] will logic long there byte receive FIFO. LSR[1:4] will provide type receive errors, receive break, encountered. LSR[5] will indicate when transmit FIFO empty. LSR[6] will indicate when both transmit FIFO transmit shift register empty. LSR[7] will show FIFO data errors occurred.
FIFO Control Register (FCR)
This register used enable FIFOs, clear FIFOs, receive FIFO trigger levels, select mode.
7.3.1 mode
7.3.1.1 Mode (FCR enable interrupt each single transmit receive operation, similar 16C450 mode. Transmit Ready (TXRDY) will logic whenever FIFO (THR, FIFO enabled) empty. Receive Ready (RXRDY) will logic whenever Receive Holding Register (RHR) loaded with character. 7.3.1.2 Mode (FCR enable interrupt block mode operation. transmit interrupt when transmit FIFO below programmed trigger level. receive interrupt when receive FIFO fills programmed trigger level. However, FIFO continues fill regardless programmed level until FIFO full. RXRDY remains logic long FIFO fill level above programmed trigger level.
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
7.3.2 FIFO mode
Table FIFO Control Register bits description Description RCVR trigger. These bits used trigger level receive FIFO interrupt. interrupt generated when number characters FIFO equals programmed trigger level. However, FIFO will continue loaded until full. Refer Table FCR[5:4] trigger. Logic cleared default condition; trigger level These bits used trigger level transmit FIFO interrupt. SC68C652B will issue transmit empty interrupt when number characters FIFO drops below selected trigger level. Refer Table FCR[3] mode select logic mode (normal default condition) logic mode Transmit operation mode `0': When SC68C652B 68C450 mode (FIFOs disabled; FCR[0] logic FIFO mode (FIFOs enabled; FCR[0] logic FCR[3] logic when there characters transmit FIFO transmit holding register, TXRDY will logic Once active, TXRDY will logic after first character loaded into transmit holding register. Receive operation mode `0': When SC68C652B 68C450 mode, FIFO mode (FCR[0] logic FCR[3] logic there least character receive FIFO, RXRDY will logic Once active, RXRDY will logic when there more characters receiver. Transmit operation mode `1': When SC68C652B FIFO mode (FCR[0] logic FCR[3] logic TXRDY will logic when transmit FIFO completely full. will logic when trigger level been reached. Receive operation mode `1': When SC68C652B FIFO mode (FCR[0] logic FCR[3] logic trigger level been reached, Receive Time-Out occurred, RXRDY will logic Once activated, will logic after there more characters FIFO. FCR[2] XMIT FIFO reset logic FIFO transmit reset (normal default condition) logic clears contents transmit FIFO resets FIFO counter logic (the transmit shift register cleared altered). This will return logic after clearing FIFO. FCR[1] RCVR FIFO reset logic FIFO receive reset (normal default condition). logic clears contents receive FIFO resets FIFO counter logic (the receive shift register cleared altered). This will return logic after clearing FIFO. FCR[0] FIFO enable logic disable transmit receive FIFO (normal default condition) logic enable transmit receive FIFO. This must when other bits written they will programmed. Symbol FCR[7:6]
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Product data sheet
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Philips Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
RCVR trigger levels FCR[6] FIFO trigger level (bytes)
Table FCR[7] Table FCR[5]
FIFO trigger levels FCR[4] FIFO trigger level (bytes)
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Interrupt Status Register (ISR)
SC68C652B provides levels prioritized interrupts minimize external software interaction. Interrupt Status Register (ISR) provides user with interrupt status bits. Performing read cycle will provide user with highest pending interrupt level serviced. other interrupts acknowledged until pending interrupt serviced. lower level interrupt seen after servicing higher level interrupt re-reading interrupt status bits. Table "Interrupt source" shows data values (bit prioritized interrupt levels interrupt sources associated with each these interrupt levels.
Table Interrupt source
Priority ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source interrupt level Table (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time-out) TXRDY (Transmitter Holding Register Empty) (Modem Status Register) RXRDY (received Xoff signal) special character CTS, change-of-state
Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits logic when FIFOs being used 16C450 mode. They logic when FIFOs enabled SC68C652B mode. logic cleared default condition priority bits 4:3. These bits enabled when EFR[4] logic ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5] indicates that CTS, have been generated. Note that once logic ISR[4] will stay logic until character(s) received. logic cleared default condition priority bits 2:0. These bits indicate source pending interrupt interrupt priority levels (see Table 14). logic cleared default condition status logic interrupt pending contents used pointer appropriate interrupt service routine logic interrupt pending (normal default condition)
ISR[5:4]
ISR[3:1]
ISR[0]
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Line Control Register (LCR)
Line Control Register used specify asynchronous data communication format. word length, number stop bits, parity selected writing appropriate bits this register.
Table Line Control Register bits description Symbol LCR[7] Description Divisor latch enable. internal baud rate counter latch Enhanced Feature mode enable. logic divisor latch disabled (normal default condition) logic divisor latch enabled LCR[6] break. When enabled, Break control causes break condition transmitted (the output forced logic state). This condition exists until disabled setting LCR[6] logic logic break condition (normal default condition) logic forces transmitter output (TX) logic alerting remote receiver line break condition LCR[5:3] LCR[2] parity; even parity; parity enable. Programs parity conditions (see Table 17). Stop bits. length stop specified this conjunction with programmed word length (see Table 18). logic cleared default condition LCR[1:0] Word length bits These bits specify word length transmitted received (see Table 19). logic cleared default condition Table LCR[5] Table LCR[2] Table LCR[1]
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LCR[5:3] parity selection LCR[4] LCR[3] Parity selection parity parity even parity forced parity forced parity
LCR[2] stop length Word length Stop length (bit times) 11/2
LCR[1:0] word length LCR[0] Word length
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Modem Control Register (MCR)
This register controls interface with modem peripheral device.
Table Modem Control Register bits description Symbol MCR[7] Description Clock select logic divide-by-1 clock input logic divide-by-4 clock input MCR[6] enable (see Figure logic enable standard modem receive transmit input/output interface (normal default condition) logic enable infrared IrDA receive transmit inputs/outputs. While this mode, TX/RX output/inputs routed infrared encoder/decoder. data input output levels will conform IrDA infrared interface requirement. such, while this mode, infrared output will logic during idle data conditions. MCR[5] MCR[4] reserved; Loop-back. Enable local loop-back mode (diagnostics). this mode transmitter output (TX) receiver input (RX), CTS, DSR, disconnected from SC68C652B pins. Internally modem data control pins connected into loop-back data configuration (see Figure this mode, receiver transmitter interrupts remain fully operational. Modem Control Interrupts also operational, interrupts' sources switched lower four bits Modem Control. Interrupts continue controlled register. logic disable loop-back mode (normal default condition) logic enable local loop-back mode (diagnostics) MCR[3] control logic forces output HIGH state logic forces output state. loop-back mode, controls MSR[7]. MCR[2] (OP1). OP1A/OP1B available external signal SC68C652B. This instead used loop-back mode only. loop-back mode, this used write state modem interface signal. logic force output logic (normal default condition) logic force output logic MCR[0] logic force output logic (normal default condition) logic force output logic
MCR[1]
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Line Status Register (LSR)
This register provides status data transfers between SC68C652B CPU.
Table Line Status Register bits description Description FIFO data error logic error (normal default condition) logic least parity error, framing error break indication current FIFO data. This cleared when there remaining error flags associated with remaining data FIFO. LSR[6] empty. This Transmit Empty indicator. This logic whenever transmit holding register transmit shift register both empty. reset logic whenever either contains data character. FIFO mode, this whenever transmit FIFO transmit shift register both empty. empty. This Transmit Holding Register Empty indicator. This indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when interrupt enable set. logic when character transferred from transmit holding register into transmitter shift register. reset logic concurrently with loading transmitter holding register CPU. FIFO mode, this when transmit FIFO empty; cleared when least byte written transmit FIFO. Break interrupt logic break condition (normal default condition) logic receiver received break signal logic character frame time). FIFO mode, only break character loaded into FIFO. LSR[3] Framing error logic framing error (normal default condition) logic framing error. receive character have valid stop bit(s). FIFO mode, this error associated with character FIFO. LSR[2] Parity error logic parity error (normal default condition logic parity error. receive character does have correct parity information suspect. FIFO mode, this error associated with character FIFO. LSR[1] Overrun error logic overrun error (normal default condition) logic overrun error. data overrun error occurred receive shift register. This happens when additional data arrives while FIFO full. this case, previous data shift register overwritten. Note that under this condition, data byte receive shift register transferred into FIFO, therefore data FIFO corrupted error. LSR[0] Receive data ready logic data receive holding register FIFO (normal default condition). logic data been received saved receive holding register FIFO.
Symbol LSR[7]
LSR[5]
LSR[4]
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Modem Status Register (MSR)
This register provides current state control interface signals from modem, other peripheral device which SC68C652B connected. Four bits this register used indicate changed information. These bits logic whenever control input from modem changes state. These bits logic whenever reads this register.
Table Modem Status Register bits description Symbol MSR[7] Description During normal operation, this complement input. Reading this loop-back mode produces state MCR[3] (OP2). During normal operation, this complement input. Reading this loop-back mode produces state MCR[2] (OP1). DSR. During normal operation, this complement input. During loop-back mode, this equivalent MCR[0] (DTR). CTS. During normal operation, this complement input. During loop-back mode, this equivalent MCR[1] (RTS).
MSR[6]
MSR[5] MSR[4] MSR[3]
logic change (normal default condition) logic input SC68C652B changed state since last time read. modem Status Interrupt will generated. MSR[2]
logic change (normal default condition) logic input SC68C652B changed from logic logic modem Status Interrupt will generated. MSR[1]
logic change (normal default condition) logic input SC68C652B changed state since last time read. modem Status Interrupt will generated. MSR[0]
logic change (normal default condition) logic input SC68C652B changed state since last time read. modem Status Interrupt will generated.
Whenever logic Modem Status Interrupt will generated.
Scratchpad Register (SPR)
SC68C652B provides temporary data register store bits user information.
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
7.10 Enhanced Feature Register (EFR)
Enhanced features enabled disabled using this register. Bits through provide single dual character software flow control selection. When Xon1 Xon2 and/or Xoff1 Xoff2 modes selected, double 8-bit words concatenated into sequential numbers.
Table Enhanced Feature Register bits description Description Automatic flow control logic automatic flow control disabled (normal default condition) logic enable automatic flow control. Transmission will stop when goes logical Transmission will resume when returns logical EFR[6] Automatic flow control. Automatic used hardware flow control enabling EFR[6]. When Auto-RTS selected, interrupt will generated when receive FIFO filled programmed trigger level will logic next trigger level. will return logic when data unloaded below next lower trigger level (programmed trigger level state this register changes with status hardware flow control. functions normally when hardware flow control disabled. logic automatic flow control disabled (normal default condition) logic enable automatic flow control. EFR[5] Special character detect logic Special character detect disabled (normal default condition) logic Special character detect enabled. SC68C652B compares each incoming receive character with Xoff2 data. match exists, received data will transferred FIFO ISR[4] will indicate detection special character. Bit-0 X-registers corresponds with receive character. When this feature enabled, normal software flow control must disabled (EFR[3:0] must logic EFR[4] Enhanced function control bit. content IER[7:4], ISR[5:4], FCR[5:4], MCR[7:5] modified latched. After modifying bits enhanced registers, EFR[4] logic latch values. This feature prevents existing software from altering overwriting SC68C652B enhanced functions. logic disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4], MCR[7:5] saved retain user settings, then IER[7:4] ISR[5:4], FCR[5:4], MCR[7:5] logic compatible with SC16C554 mode. (Normal default condition.) logic enables enhanced functions. When this logic enhanced features SC68C652B enabled user settings stored during reset will restored. EFR[3:0] Cont-3:0 control. Logic cleared default condition. Combinations software flow control selected programming these bits. Table
Symbol EFR[7]
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Software flow control functions Cont-2 Cont-1 Cont-0 software flow controls transmit flow control transmit Xon1/Xoff1 transmit Xon2/Xoff2 transmit Xon1 Xon2/Xoff1 Xoff2 receive flow control receiver compares Xon1/Xoff1 receiver compares Xon2/Xoff2 transmit Xon1/Xoff1 receiver compares Xon1 Xon2, Xoff1 Xoff2 transmit Xon2/Xoff2 receiver compares Xon1 Xon2/Xoff1 Xoff2 transmit Xon1 Xon2/Xoff1 Xoff2 receiver compares Xon1 Xon2/Xoff1 Xoff2
Table Cont-3
When using software flow control Xon/Xoff characters cannot used data transfer.
7.11 SC68C652B external reset condition
Table Register Table Output TXA, OP2A, OP2B RTSA, RTSB DTRA, DTRB Reset state registers Reset state IER[7:0] FCR[7:0] ISR[7:1] ISR[0] LCR[7:0] MCR[7:0] LSR[7] LSR[6:5] LSR[4:0] MSR[7:4] input signals; MSR[3:0] SFR[7:0] DLL[7:0] DLM[7:0] Reset state outputs Reset state logic logic logic logic 3-state condition
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Tamb Tstg Ptot(pack) Parameter supply voltage voltage operating temperature storage temperature total power dissipation package Conditions +150 Unit
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Static characteristics
Table Static characteristics Tamb unless otherwise specified. Symbol VIL(CK) VIH(CK) Parameter LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage (except clock) HIGH-level input voltage (except clock) LOW-level output voltage outputs (data bus) (other outputs) (data bus) (other outputs) HIGH-level output voltage (data bus) (other outputs) -800 (data bus) -400 (other outputs) ILIL ICC(sleep)
Conditions
-0.3 -0.3 1.85 1.85 0.45 0.65
-0.3 -0.3
-0.5 -0.5
Unit
LOW-level input leakage current clock leakage current supply current sleep current input capacitance
Except XTAL2; typical.
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Dynamic characteristics
Table Dynamic characteristics Tamb unless specified otherwise. Symbol td10 td11 td12 td13 td14 td15 td16 td17 td18 t1w, fXTAL t(RESET) tsu1 tsu2
Parameter chip select read cycle delay delay from data data disable time write cycle delay delay from write output delay interrupt from modem input delay reset interrupt from read delay from stop interrupt delay from read reset interrupt delay from start interrupt delay from write transmit start delay from write reset interrupt delay from stop RXRDY delay from read reset RXRDY delay from write TXRDY delay from start reset TXRDY hold time from data hold time address hold time clock cycle period clock speed RESET pulse width address setup time data setup time strobe width
Conditions
1TRCLK
Unit
1TRCLK
load load load load load load load
8TRCLK
24TRCLK 1TRCLK
8TRCLK
24TRCLK 1TRCLK
16TRCLK
16TRCLK
RCLK internal signal derived from Divisor Latch (DLL) Divisor Latch (DLM) divisor latches. Applies external clock; crystal oscillator MHz.
XTAL
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
10.1 Timing diagrams
tsu1
valid address
valid address
valid data
valid data
002aab087
General read timing
tsu1
valid address
valid address
tsu2
valid data
valid data
002aab088
General write timing
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
(write)(1)
active
RTSA, RTSB DTRA, DTRB
change state
change state
CDA, CTSA, CTSB DSRA, DSRB
change state
change state
active
active
active
(read)(2)
active
active
active
RIA,
change state
002aab089
timing during write cycle. Figure timing during read cycle. Figure
Modem input/output timing
EXTERNAL CLOCK
002aaa112
XTAL External clock timing
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
Start
data bits data bits data bits data bits
parity
Stop
next data Start
RXA,
td10 active td11
(read)
active
baud rate clock
002aab090
Receive timing
Start
data bits
parity
Stop
next data Start
RXA,
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab091
Receive ready timing non-FIFO mode
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Start
data bits
parity
Stop
RXA,
first byte that reaches trigger level
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab092
Receive ready timing FIFO mode
Start
data bits data bits data bits data bits active ready
parity
Stop
next data Start
TXA,
td12 td13
td14 active
(write)
active
baud rate clock
002aab093
Transmit timing
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SC68C652B
Dual UART with 32-byte FIFOs IrDA encoder/decoder
Start TXA,
data bits
parity
Stop
next data Start
(write)
active
byte
td18
td17 TXRDYA, TXRDYB active transmitter ready transmitter ready
002aab094
Transmit ready timing non-FIFO mode
Start
data bits
parity
Stop
TXA,
data bits data bits data bits (write) active td18 byte
td17 TXRDYA, TXRDYB trigger lead
002aab095
Transmit ready timing FIFO mode
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
UART frame start data bits stop
data
IrDA data
time time
time
002aaa212
Infrared transmit timing
IrDA data
time data
clock delay
start
data bits
stop
UART frame
002aaa213
Infrared receive timing
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
Soldering
12.1 Introduction soldering surface mount packages
This text gives very brief insight complex technology. more in-depth account soldering found Data Handbook IC26; Integrated Circuit Packages (document order number 9398 90011). There soldering method that ideal surface mount packages. Wave soldering still used certain surface mount ICs, suitable fine pitch SMDs. these situations reflow soldering recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Driven legislation environmental forces worldwide lead-free solder pastes increasing. Several methods exist reflowing; example, convection convection/infrared heating conveyor type oven. Throughput times (preheating, soldering cooling) vary between seconds seconds depending heating method. Typical reflow peak temperatures range from depending solder paste material. top-surface temperature packages should preferably kept:
below (SnPb process) below (Pb-free process)
BGA, HTSSON.T SSOP.T packages packages with thickness packages with thickness volume called thick/large packages.
below (SnPb process) below (Pb-free process) packages with
thickness volume called small/thin packages. Moisture sensitivity precautions, indicated packing, must respected times.
12.3 Wave soldering
Conventional single wave soldering recommended surface mount devices (SMDs) printed-circuit boards with high component density, solder bridging non-wetting present major problems. overcome these problems double-wave soldering method specifically developed. wave soldering used following conditions must observed optimal results:
double-wave soldering method comprising turbulent wave with high upward
pressure followed smooth laminar wave.
packages with leads sides pitch (e):
larger than equal 1.27 footprint longitudinal axis preferred parallel transport direction printed-circuit board;
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
smaller than 1.27 footprint longitudinal axis must parallel transport direction printed-circuit board. footprint must incorporate solder thieves downstream end.
packages with leads four sides, footprint must placed angle
transport direction printed-circuit board. footprint must incorporate solder thieves downstream side corners. During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Typical dwell time leads wave ranges from seconds seconds depending solder material applied, SnPb Pb-free respectively. mildly-activated flux will eliminate need removal corrosive residues most applications.
12.4 Manual soldering
component first soldering diagonally-opposite leads. voltage less) soldering iron applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds seconds between
12.5 Package related soldering information
Table Package BGA, HTSSON.T [3], LBGA, LFBGA, SQFP, SSOP.T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, PLCC [5], LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN.L [8], PMFP [9], WQCCN.L
Suitability surface mount packages wave reflow soldering methods Soldering method Wave suitable suitable Reflow suitable suitable
suitable recommended recommended
suitable suitable suitable suitable
suitable
more detailed information packages refer (LF)BGA Application Note (AN01026); order copy from your Philips Semiconductors sales office. surface mount (SMD) packages moisture sensitive. Depending upon moisture content, maximum temperature (with respect time) body size package, there risk that internal external package cracks occur vaporization moisture them (the called popcorn effect). details, refer Drypack information Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages extremely sensitive reflow soldering conditions must account processed through more than soldering cycle subjected infrared reflow soldering with peak temperature exceeding measured atmosphere reflow oven. package body peak temperature must kept possible.
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
These packages suitable wave soldering. versions with heatsink bottom side, solder cannot penetrate between printed-circuit board heatsink. versions with heatsink side, solder might deposited heatsink surface. wave soldering considered, then package must placed angle solder wave direction. package footprint must incorporate solder thieves downstream side corners. Wave soldering suitable LQFP, TQFP packages with pitch larger than definitely suitable packages with pitch equal smaller than 0.65 Wave soldering suitable SSOP, TSSOP, VSSOP packages with pitch equal larger than 0.65 definitely suitable packages with pitch equal smaller than Image sensor packages principle should soldered. They mounted sockets delivered pre-mounted flex foil. However, image sensor package mounted client flex foil using soldering process. appropriate soldering profile provided request. soldering manual soldering suitable PMFP packages.
Abbreviations
Table Acronym FIFO ISDN UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Integrated Service Digital Network Least Significant Most Significant Universal Asynchronous Receiver Transmitter
Revision history
Table Revision history Release date 20050425 Data sheet status Product data sheet Change notice Doc. number 9397 14657 Supersedes Document SC68C652B_1
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
Data sheet status
Level Data sheet status Objective data Preliminary data Product status Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Trademarks
Motorola registered trademark Motorola, Inc.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors
Contact information
additional information, please visit: sales office addresses, send email
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Dual UART with 32-byte FIFOs IrDA encoder/decoder
Contents
6.10 General description Features Ordering information Block diagram Pinning information Pinning description Functional description UART functions Internal registers. FIFO operation Hardware flow control Software flow control Special feature software flow control Hardware/software time-out interrupts. Programmable baud rate generator operation Loop-back mode Register descriptions Transmit (THR) Receive (RHR) Holding Registers. Interrupt Enable Register (IER) 7.2.1 versus Transmit/Receive FIFO interrupt mode operation. 7.2.2 versus Receive/Transmit FIFO polled mode operation FIFO Control Register (FCR) 7.3.1 mode 7.3.1.1 Mode (FCR 7.3.1.2 Mode (FCR 7.3.2 FIFO mode Interrupt Status Register (ISR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR). Scratchpad Register (SPR) 7.10 Enhanced Feature Register (EFR) 7.11 SC68C652B external reset condition Limiting values. Static characteristics. Dynamic characteristics 10.1 Timing diagrams Package outline Soldering 12.1 12.2 12.3 12.4 12.5 Introduction soldering surface mount packages Reflow soldering. Wave soldering. Manual soldering Package related soldering information Abbreviations Revision history Data sheet status. Definitions Disclaimers Trademarks Contact information
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dual UART, Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, Mot

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