DOUBLE DATA RATE (DDR) SDRAM Bidirectional data strobe (DQS) tran
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64Mb: SDRAM
DOUBLE DATA RATE (DDR) SDRAM
Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture Internal, pipelined double-data-rate (DDR) architecture; data accesses clock cycle Reduced output drive option Differential clock inputs CK#) Commands entered each positive edge edge-aligned with data READs; centeraligned with data WRITEs align transitions with Four internal banks concurrent operation Data mask (DM) masking write data Programmable burst lengths: full page 32ms, 4,096-cycle auto refresh (7.8µs/cycle) Auto precharge option Auto Refresh Self Refresh Modes Programmable (SSTL_2 compatible) reduced impedance matched
MT46V2M32V1- 512K banks MT46V2M32 512K banks
latest data sheet revisions, please refer Micron site: www.micron.com/dramds
ASSIGNMENT (TOP VIEW) 100-Pin TQFP (Normal Bend Shown)
VSSQ VDDQ VSSQ VDDQ DQ31 DQ30 VSSQ DQ29
OPTIONS
Configuration (512K banks) Power Supply 2.5V VDD/VDDQ 2.65V VDD/VDDQ Plastic Package 100-pin TQFP (0.65mm lead pitch) Timing Cycle Time
Part Number Example:
MARKING
2M32 none
VDDQ VSSQ VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ CAS# RAS#
10099 9291 8584 3940 4647
DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ VDDQ VREF NC/MCL A8/AP
Configuration Refresh Count Addressing Bank Addressing Column Addressing
MT46V2M32V1LG-5
TIMING PARAMETERS
SPEED GRADE CLOCK RATE DATA-OUT 1.5ns 1.8ns 1.9ns 2.1ns ACCESS ±0.75ns ±0.75ns ±0.75ns ±0.75ns DQS-DQ SKEW +0.5ns +0.5ns +0.5ns +0.5ns WINDOW* WINDOW
64Mb (x32) SDRAM PART NUMBER
PART NUMBER MT46V2M32LG ARCHITECTURE
*Minimum clock rate **CL (Read) Latency
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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512K banks (A0-A10) (BA0, BA1) (A0-A7)
64Mb: SDRAM
GENERAL DESCRIPTION
64Mb (x32) SDRAM high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. internally configured quadbank DRAM. 64Mb SDRAM uses double data rate architecture achieve high-speed operation. double data rate architecture essentially 2nprefetch architecture with interface designed transfer data words clock cycle pins. single read write access 64Mb SDRAM effectively consists single 2n-bit wide, one-clockcycle data transfer internal DRAM core corresponding n-bit wide, one-half-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. strobe transmitted SDRAM during READs memory controller during WRITEs. edge-aligned with data READs center-aligned with data WRITEs. 64Mb SDRAM operates from differential clock CK#); crossing going HIGH going will referred positive edge Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed. address bits registered coincident with READ WRITE command used select bank starting column location burst access. SDRAM provides programmable READ WRITE burst lengths full page locations. auto precharge function enabled provide self-timed precharge that initiated burst access. with standard SDRAMs, pipelined, multibank architecture SDRAMs allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided, along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2.
NOTE: functionality timing specifications discussed this data sheet DLL-enabled mode operation. Throughout data sheet, various figures text refer "DQ." term interpreted collectively, unless specifically stated otherwise.
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
TABLE CONTENTS
Functional Block Diagram Descriptions Random Writes Write Read Uninterrupting Write Read Interrupting Write Read Odd, Interrupting Write Precharge Uninterrupting Write Precharge Interrupting Write Precharge Odd, Interrupting Precharge Power-Down Truth Table (CKE) Truth Table (Current State, Same Bank) Truth Table (Current State, Different Bank) Operating Conditions Absolute Maximum Ratings Electrical Operating Conditions Input Operating Conditions Clock Input Operating Conditions Capacitance Specifications Conditions Electrical Characteristics (Timing Table) Data Valid Window Derating Voltage Timing Waveforms Nominal Output Drive Curves Reduced Output Drive Curves Output Timing tDQSQ Output Timing tDQSCK Input Timing Input Voltage Initialize Load Mode Registers Power-Down Mode Auto Refresh Mode Self Refresh Mode Reads Bank Read Without Auto Precharge Bank Read With Auto Precharge Writes Bank Write Without Auto Precharge Bank Write With Auto Precharge Write Operation 100-pin TQFP dimensions
Functional Description Initialization Register Definition Mode Register Burst Length Burst Type Read Latency Operating Mode Extended Mode Register Enable/Disable Commands Truth Table (Commands) Truth Table Operation) Deselect Operation (NOP) Load Mode Register Active Read Write Precharge Auto Precharge Burst Terminate Auto Refresh Self Refresh Operation Bank/Row Activation Reads Read Burst Consecutive Read Bursts Nonconsecutive Read Bursts Random Read Accesses Terminating Read Burst Read Write Read Precharge Writes Write Burst Consecutive Write Write Non-consecutive Write Write
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
FUNCTIONAL BLOCK DIAGRAM
CLK# CAS# RAS#
COMMAND DECODE
CONTROL LOGIC BANK3 BANK2 BANK1
MODE REGISTERS
REFRESH COUNTER
ROWADDRESS
BANK0 ROWADDRESS LATCH DECODER
2048
BANK0 MEMORY ARRAY (2048
READ LATCH GENERATOR
DATA
SENSE AMPLIFIERS 2048
DRVRS DQ31, MASK RCVRS
GATING MASK LOGIC
BANK CONTROL LOGIC
A0-A10, BA0,
ADDRESS REGISTER
(x32)
WRITE FIFO DRIVERS
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
DATA
INPUT REGISTERS
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
DESCRIPTIONS
TQFP NUMBERS SYMBOL TYPE Input DESCRIPTION Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge CK#. Output data (DQs DQS) referenced crossings CK#. Clock Enable: HIGH activates deactivates internal clock, input buffers output drivers. Taking provides PRECHARGE POWER-DOWN SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE bank). synchronous POWER-DOWN entry exit, SELF REFRESH entry. asynchronous SELF REFRESH exit disabling outputs. must maintained HIGH throughout read write accesses. Input buffers (excluding CKE) disabled during POWERDOWN. Input buffers (excluding CKE) disabled during SELF REFRESH. SSTL_2 input will detect LVCMOS level after applied. Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. provides external bank selection systems with multiple banks. considered part command code. Command Inputs: RAS#, CAS#, (along with CS#) define command being entered. Input Data Mask: input mask signal write data. Input data masked when sampled HIGH along with that input data during WRITE access. sampled both edges DQS. Although pins input-only, loading designed match that pins. Bank Address Inputs: define which bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address Inputs: Provide address ACTIVE commands, column address auto precharge (A8) READ/ WRITE commands, select location memory array respective bank. sampled during PRECHARGE command determines whether PRECHARGE applies bank LOW, bank selected BA0, BA1) banks HIGH). address inputs also provide op-code during MODE REGISTER command. define which mode register (mode register extended mode register) loaded during LOAD MODE REGISTER command. Data Input/Output:
Input
Input
RAS#, CAS#, Input DM0-DM3 Input
31-34, 47-51,
BA0, Input A0-A10 Input
100,
DQ0-31
(continued next page)
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
DESCRIPTIONS (continued)
TQFP NUMBERS SYMBOL TYPE DESCRIPTION Data Strobe: Output with read data, input with write data. edge-aligned with read data, centered write data. used capture data. Connect: These pins should left unconnected.
37-44 87-90
VDDQ VREF
Use: Must float minimize noise. Reserved Future Supply Power Supply: Isolated improved noise immunity. Supply Ground. Isolated improved noise immunity. Supply Power Supply Supply Ground. Supply SSTL_2 reference voltage.
RESERVED PINS1
TQFP NUMBERS SYMBOL (MCL) TYPE DESCRIPTION Address input 128Mb 256Mb devices. Address input 256Mb devices. Finalized Connect: internally connected. Must Connect (for compatibility with SGRAM devices).
NOTE: pins listed also reserved other uses future. This table simply defines specific pins deemed importance.
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
FUNCTIONAL DESCRIPTION
64Mb SDRAM high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. 64Mb SDRAM internally configured quad-bank DRAM. 64Mb SDRAM uses double data rate architecture achieve high-speed operation. double data rate architecture essentially 2nprefetch architecture, with interface designed transfer data words clock cycle pins. single read write access 64Mb SDRAM consists single 2n-bit wide, one-clock-cycle data transfer internal DRAM core corresponding n-bit wide, one-half-clock-cycle data transfers pins. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0, select bank; A0-A10 select row). address bits registered coincident with READ WRITE command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation. should brought HIGH. Following command, PRECHARGE command should applied. Next LOAD MODE REGISTER command should issued extended mode register (BA1 HIGH) enable DLL, followed another LOAD MODE REGISTER command mode register, BA0/BA1 must reset program operating parameters. Two-hundred clock cycles required between reset READ command. PRECHARGE command should then applied, placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. (tRFC must satisfied.) Additionally, LOAD MODE REGISTER command mode register with reset deactivated (i.e., program operating parameters without resetting DLL) requirement. Following these requirements, SDRAM ready normal operation.
Register Definition
MODE REGISTER mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency operating mode, shown Figure mode register programmed MODE REGISTER command (with will retain stored information until programmed again device loses power (except which self-clearing). Reprogramming mode register will alter contents memory, provided performed correctly. mode register must loaded (reloaded) when banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Mode register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A10 specify operating mode. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved modes. Full page burst only available sequential mode.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Power must first applied VDDQ simultaneously, then VREF (and system VTT). must applied after VDDQ avoid device latch-up, which cause permanent damage device. VREF applied time after VDDQ expected nominally coincident with VTT. Except CKE, inputs recognized valid until after VREF applied. SSTL_2 input will detect LVCMOS level after applied. Maintaining LVCMOS level during power-up required ensure that outputs will High-Z state, where they will remain until driven normal operation read access). After power supply reference voltages stable, clock stable, SDRAM requires 200µs delay prior applying executable command. Once 200µs delay been satisfied, DESELECT command should applied,
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both READ WRITE bursts.
Address
Table Burst Definition
Order Accesses Within Burst Burst Length Starting Column Address A0-A7, Type Sequential Type Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn+1, Cn+2 Cn+3, Cn+4. .Cn-1, Cn-1, Cn-2 Cn-3, Cn-4. .Cn+1, 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
Operating Mode Latency Burst Length Mode Register (Mx)
(BA0 BA1) must select base mode register (vs. extended mode register).
Burst Length Reserved Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved Full Page
Full Page (256)
A0-A7,
supported
NOTE:
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved
M6-M0 Valid Valid
Operating Mode Normal Operation Normal Operation/Reset other states reserved
burst length two, A1-A7 select block burst; selects starting column within block. burst length four, A2-A7 select block four burst; A0-A1 select starting column within block. burst length eight, A3-A7 select block eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-A7 select starting column. also selects direction burst (incrementing decrementing Whenever boundary block reached within given sequence above, following access wraps within block.
Figure Mode Register Definition
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table Read Latency READ latency delay, clock cycles, between registration READ command availability first output data. latency clocks, shown Figure READ command registered clock edge latency clocks, data will available nominally coincident with clock edge Table indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
COMMAND
Table Latency
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED
READ
Operating Mode normal operating mode selected issuing MODE REGISTER command with bits A7-A10 each zero, bits A0-A6 desired values. reset initiated issuing MODE REGISTER command with bits each zero, one, bits A0-A6 desired values. Although required Micron device, JEDEC specifications recommend when LOAD MODE REGISTER command issued reset DLL, should always followed LOAD MODE REGISTER command select normal operating mode. other combinations values A7-A10 reserved future and/or test modes. Test modes reserved states should used because unknown operation incompatibility with future versions result.
COMMAND
READ
Burst Length cases shown Shown with nominal nominal tDSDQ TRANSITIONING DATA DON'T CARE
Figure Latency
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
EXTENDED MODE REGISTER extended mode register controls functions beyond those controlled mode register; these additional functions enable/disable. These functions controlled bits shown Figure extended mode register programmed LOAD MODE REGISTER command mode register (with will retain stored information until programmed again device loses power. Although required Micron device, enabling should always followed LOAD MODE REGISTER command mode register (BA0/BA1 both LOW) reset DLL. extended mode register must loaded when banks idle bursts progress, controller must wait specified time before initiating subsequent operation. Violating either these requirements could result unspecified operation.
Address
Operating Mode
Extended Mode Register (Ex)
Enable Disable Drive Strength
Impedance Match Reduced
Operating Mode Valid Normal Operation other states reserved
Output Drive Strength reduced drive strength outputs specified SSTL_2. supports option impedance matched drive. This option intended support lighter load and/or point-to-point environments. selection impedance drive strength will alter DQSs from SSTL_2, Class drive strength reduced drive strength, which approximately percent SSTL_2 Class drive strength. Enable/Disable must enabled normal operation. enable required during power-up initialization upon returning normal operation after having disabled purpose debug evaluation. (When device exits self refresh mode, enabled automatically.) time enabled, clock cycles must occur before READ command issued.
NOTE: (BA0 BA1) must select Extended Mode Register (vs. base Mode Register).
Figure Extended Mode Register Definition
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
Commands
Truth Table provides quick reference available commands. This followed verbal description each command. additional Truth Tables appear following Operation section; these tables provide current state/next state information.
TRUTH TABLE COMMANDS
(Note: NAME (FUNCTION) DESELECT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER RAS# CAS# ADDR Bank/Row Bank/Col Bank/Col Code Op-Code NOTES
TRUTH TABLE OPERATION
NAME (FUNCTION) Write Enable Write Inhibit Valid NOTES
NOTE: HIGH commands shown except SELF REFRESH. BA0-BA1 select either mode register extended mode register (BA0 select mode register; select extended mode register; other combinations BA0-BA1 reserved). A0-A11 provide opcode written selected mode register. BA0-BA1 provide bank address A0-A10 provide address. BA0-BA1 provide bank address; A0-A7 provide column address; HIGH enables auto precharge feature (nonpersistent), disables auto precharge feature. LOW: BA0-BA1 determine which bank precharged. HIGH: banks precharged BA0-BA1 "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except during self refresh. Applies only read bursts with auto precharge disabled; this command undefined (and should used) READ bursts with auto precharge enabled WRITE bursts. DESELECT functionally interchangeable. Used mask write data; provided coincident with corresponding data.
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
DESELECT DESELECT function (CS# HIGH) prevents commands from being executed SDRAM. SDRAM effectively deselected. Operations already progress affected. OPERATION (NOP) OPERATION (NOP) command used instruct selected SDRAM perform (CS# LOW). This prevents unwanted commands from being registered during idle wait states. Operations already progress affected. LOAD MODE REGISTER mode registers loaded inputs A0-A10. mode register descriptions Register Definition section. LOAD MODE REGISTER command only issued when banks idle, subsequent executable command cannot issued until tMRD met. ACTIVE ACTIVE command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A10 selects row. This remains active open) accesses until PRECHARGE command issued that bank. PRECHARGE command must issued before opening different same bank. READ READ command used initiate burst read access active row. value BA0, inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged READ burst; auto precharge selected, will remain open subsequent accesses. WRITE WRITE command used initiate burst write access active row. value BA0, inputs selects bank, address provided inputs A0-A7 selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged WRITE burst; auto precharge selected, will remain open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered LOW, corresponding data will written memory; signal registered HIGH, corresponding data inputs will ignored, WRITE will executed that byte/column location. PRECHARGE PRECHARGE command used deactivate open particular bank open banks. bank(s) will available subsequent access specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank. PRECHARGE command will treated there open that bank (idle state), previously open already process precharging. AUTO PRECHARGE Auto precharge feature which performs same individual-bank precharge function described above, without requiring explicit command. This accomplished using enable auto precharge conjunction with specific READ WRITE command. precharge bank/row that addressed with READ WRITE command automatically performed upon completion READ WRITE burst. Auto precharge nonpersistent that either enabled disabled each individual READ WRITE command. Auto precharge ensures that precharge initiated earliest valid stage within burst. This "earliest valid stage" determined explicit PRECHARGE command issued earliest possible time, described each burst type Operation section this data sheet. user must issue another command same bank until precharge time (tRP) completed. BURST TERMINATE BURST TERMINATE command used truncate READ bursts (with auto precharge disabled). most recently registered READ command prior BURST TERMINATE command will truncated, shown Operation section this data sheet.The BURST TERMINATE does precharge row.
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
AUTO REFRESH AUTO REFRESH used during normal operation SDRAM analogous CAS#-BEFORERAS# (CBR) REFRESH FPM/EDO DRAMs. This command nonpersistent, must issued each time refresh required. addressing generated internal refresh controller. This makes address bits "Don't Care" during AUTO REFRESH command. 64Mb SDRAM requires AUTO REFRESH cycles average interval 7.8µs (maximum). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight AUTO REFRESH commands posted given SDRAM, meaning that maximum absolute interval between AUTO REFRESH command next AUTO REFRESH command 7.8µs (70.2µs). This maximum absolute interval allow future support updates internal SDRAM restricted AUTO REFRESH cycles, without allowing excessive drift between updates. SELF REFRESH SELF REFRESH command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. SELF REFRESH command initiated like AUTO REFRESH command except disabled (LOW). automatically disabled upon entering SELF REFRESH automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before READ command issued). Input signals except "Don't Care" during SELF REFRESH. procedure exiting self refresh requires sequence commands. First, must stable prior going back HIGH. Once HIGH, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command.
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Operations
BANK/ROW ACTIVATION Before READ WRITE commands issued bank within SDRAM, that bank must "opened." This accomplished ACTIVE command, which selects both bank activated, shown Figure After opened with ACTIVE command, READ WRITE command issued that row, subject tRCD specification. tRCD (MIN) should divided clock period rounded next whole number determine earliest clock edge after ACTIVE command which READ WRITE command entered. example, tRCD specification 20ns with clock (8ns period) results clocks rounded This reflected Figure which covers case where tRCD (MIN)/tCK (Figure also shows same case tRCD; same procedure used convert other specification limits from time units clock cycles). subsequent ACTIVE command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive ACTIVE commands same bank defined tRC. subsequent ACTIVE command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive ACTIVE commands different banks defined tRRD.
HIGH
RAS#
CAS#
A0-A10
BA0,1
Address Bank Address
Figure Activating Specific Specific Bank
COMMAND
RD/WR
A0-A10
BA0,
Bank
Bank
Bank
tRRD
tRCD
DON'T CARE
Example: Meeting
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
tRCD (tRRD)
Figure When tRCD (tRRD) MIN/tCK
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64Mb: SDRAM
READs READ bursts initiated with READ command, shown Figure starting column bank addresses provided with READ command auto precharge either enabled disabled that burst access. auto precharge enabled, being accessed precharged completion burst. generic READ commands used following illustrations, auto precharge disabled. During READ bursts, valid data-out element from starting column address will available following latency after READ command. Each subsequent data-out element will valid nominally next positive negative clock edge (i.e., next crossing CK#). Figure shows general timing each possible latency setting. driven SDRAM along with output data. initial state known read preamble; state coincident with last dataout element known read postamble. Upon completion burst, assuming other commands have been initiated, will High-Z. detailed explanation tDQSQ (valid dataout skew), (data-out window hold), valid data window depicted Figure detailed explanation tDQSCK (DQS transition skew (data-out transition skew depicted Figure Data from READ burst concatenated with truncated with data from subsequent READ command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst which being truncated. READ command should issued cycles after first READ command, where equals number desired data element pairs (pairs required 2n-prefetch architecture). This shown Figure READ command initiated clock cycle following previous READ command. Nonconsecutive read data shown illustration Figure Full-speed random read accesses within page pages) performed shown Figure
HIGH
RAS# CAS#
A0-A7
BA0,1
Column Address Bank Address Enable Auto Precharge Disable Auto Precharge DON'T CARE
Figure READ Command
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64Mb: SDRAM
COMMAND
READ
ADDRESS
Bank
COMMAND
READ
ADDRESS
Bank
DON'T CARE
TRANSITIONING DATA
NOTE: data-out from column Burst length Three subsequent elements data-out appear programmed order following Shown with nominal tAC, tDQSCK, tDQSQ.
Figure READ Burst
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COMMAND
READ
READ
ADDRESS
Bank,
Bank,
COMMAND
READ
READ
ADDRESS
Bank,
Bank,
DON'T CARE NOTE:
TRANSITIONING DATA
data-out from column column Burst length bursts concatenated; second burst interrupts first). Three subsequent elements data-out appear programmed order following Three seven) subsequent elements data-out appear programmed order following Shown with nominal tAC, tDQSCK, tDQSQ. Example applies only when READ commands issued same device.
Figure Consecutive READ Bursts
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COMMAND
READ
READ
ADDRESS
Bank,
Bank,
COMMAND
READ
READ
ADDRESS
Bank,
Bank,
DON'T CARE NOTE:
TRANSITIONING DATA
data-out from column column Burst length bursts concatenated; second burst interrupts first). Three subsequent elements data-out appear programmed order following Three seven) subsequent elements data-out appear programmed order following Shown with nominal tAC, tDQSCK, tDQSQ. Example applies when READ commands issued different devices nonconsecutive READs.
Figure Nonconsecutive READ Bursts
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COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Bank,
Bank,
Bank,
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Bank,
Bank,
Bank,
DON'T CARE NOTE:
TRANSITIONING DATA
data-out from column column column column Burst length following burst interrupts previous). indicates next data-out following respectively. READs active bank. Shown with nominal tAC, tDQSCK, tDQSQ.
Figure Random READ Accesses
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READs (continued) Data from READ burst truncated with BURST TERMINATE command, shown Figure BURST TERMINATE latency equal READ (CAS) latency, i.e., BURST TERMINATE command should issued cycles after READ command, where equals number desired data element pairs (pairs required 2n-prefetch architecture). Data from READ burst must completed truncated before subsequent WRITE command issued. truncation necessary, BURST TERMINATE command must used, shown Figure tDQSS (MIN) case shown; tDQSS (MAX) case longer idle time. (tDQSS [MIN]
tDQSS
[MAX] defined section WRITEs.) READ burst followed truncated with, PRECHARGE command same bank provided that auto precharge activated. PRECHARGE command should issued cycles after READ command, where equals number desired data element pairs (pairs required 2n-prefetch architecture). This shown Figure Following PRECHARGE command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data elements.
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COMMAND
BST5
READ
ADDRESS
Bank
COMMAND
READ
BST5
ADDRESS
Bank
DON'T CARE NOTE:
TRANSITIONING DATA
data-out from column Burst length Subsequent element data-out appears programmed order following Shown with nominal tAC, tDQSCK, tDQSQ. BURST TERMINATE command.
Figure Terminating READ Burst
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COMMAND
BST7
READ
WRITE
ADDRESS
Bank,
Bank,
tDQSS
(MIN)
COMMAND
READ
BST7
WRITE
ADDRESS
Bank
Bank,
tDQSS
(MIN)
DON'T CARE
TRANSITIONING DATA
NOTE: data-out from column data-in from column Burst length cases shown (applies bursts full page well; burst length command shown NOP). subsequent element data-out appears programmed order following Data-in elements applied following programmed order. Shown with nominal tAC, tDQSCK, tDQSQ. BURST TERMINATE command.
Figure READ WRITE
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COMMAND6
READ
ADDRESS
Bank
Bank all)
Bank
COMMAND6
READ
ADDRESS
Bank
Bank all)
Bank
DON'T CARE NOTE:
TRANSITIONING DATA
data-out from column Burst length interrupted burst full page. Three subsequent elements data-out appear programmed order following Shown with nominal tAC, tDQSCK, tDQSQ. READ PRECHARGE equals clocks, which allows data pairs data-out. PRECHARGE command; ACTIVE command.
Figure READ PRECHARGE
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WRITEs WRITE bursts initiated with WRITE command, shown Figure starting column bank addresses provided with WRITE command, auto precharge either enabled disabled that access. auto precharge enabled, being accessed precharged completion burst. generic WRITE commands used following illustrations, auto precharge disabled. During WRITE bursts, first valid data-in element will registered first rising edge following WRITE command, subsequent data elements will registered successive edges DQS. state between WRITE command first rising edge known write preamble; state following last data-in element known write postamble. time between WRITE command first corresponding rising edge (tDQSS) specified with relatively wide range (from percent percent clock cycle). WRITE diagrams show nominal case, where extreme cases (i.e., tDQSS [MIN] tDQSS [MAX]) might intuitive, they have also been included. Figure shows nominal case extremes tDQSS burst Upon completion burst, assuming other commands have been initiated, will remain High-Z additional input data will ignored. Data WRITE burst concatenated with truncated with subsequent WRITE command. either case, continuous flow input data maintained. WRITE command issued positive edge clock following previous WRITE command. first data element from burst applied after either last element completed burst last desired data element longer burst which being truncated. WRITE command should issued cycles after first WRITE command, where equals number desired data element pairs (pairs required 2n-prefetch architecture). Figure shows concatenated bursts example nonconsecutive WRITEs shown Figure Full-speed random write accesses within page pages performed shown Figure Data WRITE burst followed subsequent READ command. follow WRITE without truncating WRITE burst, tWTR should shown Figure Data WRITE burst truncated subsequent READ command, shown Figure Note that only data-in pairs that registered
RAS# CAS# HIGH
A0-A7
BA0,1
Column Address Bank Address Enable Auto Precharge Disable Auto Precharge DON'T CARE
Figure WRITE Command
prior tWTR period written internal array, subsequent data-in should masked with shown Figure Data WRITE burst followed subsequent PRECHARGE command. follow WRITE without truncating WRITE burst, should shown Figure Data WRITE burst truncated subsequent PRECHARGE command, shown Figures Note that only data-in pairs that registered prior period written internal array, subsequent data-in should masked with shown Figures After PRECHARGE command, subsequent command same bank cannot issued until met.
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COMMAND
WRITE
ADDRESS
tDQSS (NOM)
Bank
tDQSS
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
CARE
TRANSITIONING DATA
NOTE: data-in column Three subsequent elements data-in applied programmed order following uninterrupted burst shown. with WRITE command (auto precharge disabled).
Figure WRITE Burst
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COMMAND
WRITE
WRITE
ADDRESS
Bank, tDQSS (NOM)
Bank,
CARE NOTE:
TRANSITIONING DATA
etc. data-in column etc. Three subsequent elements data-in applied programmed order following Three subsequent elements data-in applied programmed order following uninterrupted burst shown. Each WRITE command bank.
Figure Consecutive WRITE WRITE
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COMMAND
WRITE
WRITE
ADDRESS
Bank, tDQSS (NOM)
Bank,
CARE NOTE:
TRANSITIONING DATA
etc. data-in column etc. Three subsequent elements data-in applied programmed order following Three subsequent elements data-in applied programmed order following uninterrupted burst shown. Each WRITE command bank.
Figure Nonconsecutive WRITE WRITE
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COMMAND
WRITE
WRITE
WRITE
WRITE
WRITE
ADDRESS
Bank,
Bank,
Bank,
Bank,
Bank,
tDQSS (NOM)
CARE NOTE:
TRANSITIONING DATA
etc. data-in column etc. etc. next data-in following etc., according programmed burst order. Programmed burst length cases shown. Each WRITE command bank.
Figure Random WRITE Cycles
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COMMAND
WRITE
tWTR
READ
ADDRESS
tDQSS (NOM)
Bank tDQSS
Bank
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column Three subsequent elements data-in applied programmed order following uninterrupted burst shown. tWTR referenced from first positive edge after last data-in pair. READ WRITE commands same bank. However, READ WRITE commands different devices, which case tWTR required READ command could applied earlier. with WRITE command (auto precharge disabled).
Figure WRITE READ Uninterrupting
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COMMAND
WRITE
tWTR
READ
ADDRESS
tDQSS (NOM)
Bank tDQSS
Bank
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column interrupted burst shown; data elements written. subsequent element data-in applied programmed order following tWTR referenced from first positive edge after last data-in pair. with WRITE command (auto precharge disabled). required (nominal case) register burst used, would required T3-T4n because READ command would mask last data elements.
Figure WRITE READ Interrupting
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COMMAND
WRITE
tWTR
READ
ADDRESS
tDQSS (NOM)
Bank tDQSS
Bank
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column interrupted burst shown; data element written. tWTR referenced from first positive edge after last desired data-in pair (not last data elements). with WRITE command (auto precharge disabled). required T1n, (nominal case) register burst used, would required T3-T4n because READ command would mask last four data elements.
Figure WRITE READ Number Data, Interrupting
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COMMAND
PRE7 Bank, all)
WRITE
ADDRESS
tDQSS (NOM)
Bank tDQSS
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column Three subsequent elements data-in applied programmed order following uninterrupted burst shown. referenced from first positive edge after last data-in pair. PRECHARGE WRITE commands same bank. However, PRECHARGE WRITE commands different devices, which case required PRECHARGE command could applied earlier. with WRITE command (auto precharge disabled). PRECHARGE command.
Figure WRITE PRECHARGE Uninterrupting
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COMMAND
PRE9
WRITE
ADDRESS
tDQSS (NOM)
Bank tDQSS
Bank, all)
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column Subsequent element data-in applied programmed order following interrupted burst shown; data elements written. referenced from first positive edge after last data-in pair. PRECHARGE WRITE commands same bank. with WRITE command (auto precharge disabled). required (nominal case) register burst used, would required because PRECHARGE command would mask last data elements. PRECHARGE command.
Figure WRITE Precharge Interrupting
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COMMAND
PRE9
WRITE
ADDRESS
tDQSS (NOM)
Bank tDQSS
Bank, all)
tDQSS (MIN)
tDQSS
tDQSS (MAX)
tDQSS
DON'T CARE NOTE:
TRANSITIONING DATA
data-in column Subsequent element data-in applied programmed order following interrupted burst shown; data elements written. referenced from first positive edge after last data-in pair. PRECHARGE WRITE commands same bank. with WRITE command (auto precharge disabled). required T1n, (nominal case) register burst used, would required because PRECHARGE command would mask last data elements. PRECHARGE command.
Figure WRITE PRECHARGE Number Data, Interrupting
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PRECHARGE PRECHARGE command (Figure used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after PRECHARGE command issued. Input deCK# HIGH
termines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank. POWER-DOWN (CKE ACTIVE) Unlike SDRAMs, SDRAMs require active times access progress: from issuing READ WRITE command until completion burst. READs, burst completion defined when Read Postamble satisfied; WRITEs, burst completion defined when Write Postamble satisfied. Power-down (Figure entered when registered LOW. power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE. maximum power savings, frozen. Exiting power-down requires device same voltage frequancy when entered power-down. However, power-down duration limited refresh requirements device, most applications, selfrefresh mode preferred over DLL-disabled powerdown mode. While power-down, stable clock signal must maintained inputs SDRAM, while other input signals "Don't Care." power-down state synchronously exited when registered HIGH conjunction with DESELECT command). valid executable command applied clock cycle later.
RAS#
CAS#
A0-A7,
BANKS
BANK
BA0,BA1
Bank Address LOW; otherwise Care
Figure PRECHARGE Command
COMMAND
VALID
VALID
READ/WRITE access progress
Enter power-down mode
Exit power-down mode CARE
Figure Power-Down
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TRUTH TABLE
(Notes: 1-4) CKEn-1 CKEn CURRENT STATE Power-Down Self Refresh Power-Down Self Refresh Banks Idle Bank(s) Active Banks Idle
NOTE:
COMMAND DESELECT DESELECT DESELECT DESELECT AUTO REFRESH Truth Table
ACTION Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry
NOTES
CKEn logic state clock edge CKEn-1 state previous clock edge. Current state state SDRAM immediately prior clock edge COMMANDn command registered clock edge ACTIONn result COMMANDn. states sequences shown illegal reserved. DESELECT commands should issued clock edges occurring during tXSR period. minimum clock cycles needed before applying READ command lock.
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TRUTH TABLE CURRENT STATE BANK COMMAND BANK
(Notes: 1-6; notes appear below next page) CURRENT STATE RAS# CAS# Idle Active Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled)
NOTE: This table applies when CKEn-1 HIGH CKEn HIGH (see Truth Table after tXSNR been previous state self refresh). This table bank-specific, except where noted (i.e., current state specific bank commands shown those allowed issued that bank when that state). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. following states must interrupted command issued same bank. COMMAND INHIBIT commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state Truth Table according Truth Table Precharging: Starts with registration PRECHARGE command ends when met. Once met, bank will idle state. Activating: Starts with registration ACTIVE command ends when tRCD met. Once tRCD met, bank will "row active" state. Read w/AutoPrecharge Enabled: Starts with registration READ command with auto precharge enabled ends when been met. Once met, bank will idle state. Write w/AutoPrecharge Enabled: Starts with registration WRITE command with auto precharge enabled ends when been met. Once met, bank will idle state.
COMMAND/ACTION DESELECT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) ACTIVE (select activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE (deactivate bank banks) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE)
NOTES
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NOTE (continued): following states must interrupted executable command; COMMAND INHIBIT commands must applied each positive clock edge during these states. Refreshing: Starts with registration AUTO REFRESH command ends when met. Once met, SDRAM will banks idle state. Accessing Mode Register: Starts with registration LOAD MODE REGISTER command ends when tMRD been met. Once tMRD met, SDRAM will banks idle state. Precharging All: Starts with registration PRECHARGE command ends when met. Once met, banks will idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle, bursts progress. bank-specific; multiple banks precharged, each must valid state precharging. bank-specific; BURST TERMINATE affects most recent READ burst, regardless bank. READs WRITEs listed Command/Action column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Requires appropriate masking. WRITE command applied after completion READ burst; otherwise, BURST TERMINATE must used READ burst prior asserting WRITE command.
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TRUTH TABLE CURRENT STATE BANK COMMAND BANK
(Notes: 1-9; notes appear below next page) CURRENT STATE RAS# CAS# Idle Activating, Active, Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (With AutoPrecharge) Write (With AutoPrecharge) COMMAND/ACTION DESELECT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) Command Otherwise Allowed Bank ACTIVE (select activate row) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE ACTIVE (select activate row) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE ACTIVE (select activate row) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE ACTIVE (select activate row) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE ACTIVE (select activate row) READ (select column start READ burst) WRITE (select column start WRITE burst) PRECHARGE NOTES
NOTE: This table applies when CKEn-1 HIGH CKEn HIGH (see Truth Table after tXSNR been previous state self refresh). This table describes alternate bank operation, except where noted (i.e., current state bank commands shown those allowed issued bank assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: following text Write with Auto Precharge Enabled: following text
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NOTES (continued):
read with auto precharge enabled write with auto precharge enabled states each broken into parts: access period precharge period. read with auto precharge, precharge period defined same burst executed with auto precharge disabled then followed with earliest possible PRECHARGE command that still accesses data burst. write with auto precharge, precharge period begins when ends, with measured auto precharge disabled. access period starts with registration command ends where precharge period tRP) begins. During precharge period read with auto precharge enabled write with auto precharge enabled states, ACTIVE, PRECHARGE, READ, WRITE commands other bank applied; during access period, only ACTIVE PRECHARGE commands other bank applied. either case, other related limitations apply (e.g., contention between read data write data must avoided). AUTO REFRESH LOAD MODE REGISTER commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. READs WRITEs listed Command/Action column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Requires appropriate masking. WRITE command applied after completion READ burst; otherwise, BURST TERMINATE must used READ burst prior asserting WRITE command.
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ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative +3.6V Voltage VDDQ Supply Relative +3.6V Voltage VREF Inputs Relative +3.6V Voltage Pins Relative -0.5V VDDQ +0.5V Operating Temperature, (ambient) +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation Short Circuit Output Current 50mA *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(Notes: 1-5, notes appear pages 47-50) (0°C +70°C;) PARAMETER/CONDITION Supply Voltage, Part Type 2.5V/2.65V Supply Voltage, Part Type 2.5V/2.65V Reference Voltage Termination Voltage (system) Input High (Logic Voltage Input (Logic Voltage Clock Input Voltage Level; Clock Input Differential Voltage; Clock Input Crossing Point Voltage; Input Leakage Current: input (All other pins under test Output Leakage Current: (DQs disabled; VOUT VDDQ) Output Levels: Impedance Match High Current (VOUT VDDQ-0.373V, minimum VREF, minimum VTT) Current (VOUT 0.373V, maximum VREF,maximum VTT) Output Levels: Reduced drive option High Current (VOUT VDDQ-0.763V, minimum VREF, minimum VTT) Current (VOUT 0.763V, maximum VREF,maximum VTT) SYMBOL VDDQ VREF VIH(DC) VIL(DC) 2.4/2.55 2.4/2.55 0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 0.36 2.6/2.75 2.6/2.75 0.51 VDDQ VREF 0.04 VREF 0.15 VDDQ VDDQ UNITS NOTES 9,43 6,44 7,44
IOHR IOLR
INPUT OPERATING CONDITIONS
(Notes: 1-5, notes appear pages 47-50) (0°C +70°C;) PARAMETER/CONDITION Input High (Logic Voltage; Input (Logic Voltage; Clock Input Differential Voltage; Clock Input Crossing Point Voltage;
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
SYMBOL VIH(AC) VIL(AC) VID(AC) VIX(AC)
VREF 0.310 VDDQ-0.2
VREF 0.310 VDDQ VDDQ+0.2
UNITS
NOTES
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CLOCK INPUT OPERATING CONDITIONS
(Notes: 1-5, notes appear pages 47-50) (0°C 70°C; +2.5V ±0.1V, VDDQ +2.5V ±0.1V) PARAMETER/CONDITION Clock Input Mid-Point Voltage; Clock Input Voltage Level; Clock Input Differential Voltage; Clock Input Differential Voltage; Clock Input Crossing Point Voltage; SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) 1.05 -0.3 0.36 VDDQ 1.45 VDDQ VDDQ VDDQ VDDQ UNITS NOTES
2.6v
Maximum Clock Level
1.45v 1.25v 1.05v
(DC)
(AC)
(DC) (AC)
0.30v
Minimum Clock Level
NOTE:
This provides minimum 1.225v maximum 1.425v, always half VDDQ. must cross this region. must meet least VID(DC) when static centered around VMP(DC) must have minimum 700mv peak peak swing. more positive than VDDQ 0.5v more negative than 0.5v. operation, clock requirements must also satisfied. Numbers diagram reflect nominal values.
FIGURE SSTL_2 CLOCK INPUT
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CLOCK INPUT OPERATING CONDITIONS
(Notes: 1-5, notes appear pages 47-50) (0°C 70°C; +2.65V ±0.1V, VDDQ +2.65V ±0.1V) PARAMETER/CONDITION Clock Input Mid-Point Voltage; Clock Input Voltage Level; Clock Input Differential Voltage; Clock Input Differential Voltage; Clock Input Crossing Point Voltage; SYMBOL VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) 1.05 -0.3 0.36 VDDQ 1.45 VDDQ VDDQ VDDQ VDDQ UNITS NOTES
2.80v
Maximum Clock Level
1.525v 1.325v 1.125v
(DC)
(AC)
(DC) (AC)
0.30v
Minimum Clock Level
NOTE:
This provides minimum 1.225v maximum 1.425v, always half VDDQ. must cross this region. must meet least VID(DC) when static centered around VMP(DC) must have minimum 700mv peak peak swing. more positive than VDDQ 0.5v more negative than 0.5v. operation, clock requirements must also satisfied. Numbers diagram reflect nominal values.
FIGURE SSTL_2 CLOCK INPUT
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CAPACITANCE
(Note: PARAMETER Delta Input/Output Capacitance: DQs, DQS, Delta Input Capacitance: Command Address Delta Input Capacitance: Input/Output Capacitance: DQs, DQS, Input Capacitance: Command Address Input Capacitance: Input Capacitance: SYMBOL DCIO DCI1 DCI2 0.50 0.50 0.25 UNITS NOTES
SPECIFICATIONS CONDITIONS
(Notes: 1-5, notes appear pages 47-50) (0°C +70°C; VDDQ 2.5V/+2.65V, VDD=2.5V/+2.65V) PARAMETER/CONDITION Operating Current: bank; Active-Precharge; MIN; MIN; inputs changing twice clock cyle; Address control inputs changing once clock cycle Operating Current: bank; Active-Read-Precharge; Burst (MIN); (MIN); IOUT 0mA; Address control inputs changing once clock cycle Precharge Power-Down Standby Current: banks idle; Power-down mode; (MIN); Idle Standby Current: HIGH; banks idle; (MIN); HIGH; Address other control inputs changing once clock cycle Active Power-Down Standby Current: bank active; Power-down mode; (MIN); Active Standby Current: HIGH; HIGH; bank; Active-Precharge; tRAS (MAX); (MIN); inputs changing twice clock cycle; Address other control inputs changing once clock cycle Operating Current: Burst Reads; Continuous burst; bank active; Address control inputs changing once clock cycle; (MIN); IOUT Operating Current: Burst Writes; Continuous burst; bank active; Address control inputs changing once clock cycle; (MIN); inputs changing twice clock cycle Auto Refresh Current Self Refresh Current: 0.2V
SYMBOL IDD0
UNITS NOTES
IDD1
IDD2P IDD2N
IDD3P IDD3N
IDD4R
IDD4W
tRFC (MIN) 7.8µs
IDD5 IDD6 IDD7
Standard
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ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: 1-5, 14-17, notes appear pages 47-50) (0°C +70°C; VDDQ +2.5V/+2.65V, VDD=+2.5V+2.65V)
CHARACTERISTICS PARAMETER Access window from CK/CK# high-level width low-level width Clock cycle time input hold time relative input setup time relative input pulse width (for each input) Access window from CK/CK# input high pulse width input pulse width DQS-DQ skew, last valid, group, access Write command first latching transition falling edge rising setup time falling edge from rising hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address control input hold time Address control input setup time Address control input pulse width LOAD MODE REGISTER command cycle time DQ-DQS hold, first non-valid, access ACTIVE PRECHARGE command ACTIVE READ with Auto precharge command ACTIVE ACTIVE/AUTO REFRESH command period AUTO REFRESH command period REFRESH REFRESH command interval` Average periodic refresh interval ACTIVE READ WRITE delay PRECHARGE command period Read preamble Read postamble ACTIVE bank ACTIVE bank command Terminating voltage delay Write preamble Write preamble setup time Write postamble Write recovery time Internal WRITE READ command delay Exit SELF REFRESH non-READ command Exit SELF REFRESH READ command Data valid output window SYMBOL tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tIPW tMRD
tRAS tRAP tRFC tREFC tREFI tRCD tRPRE tRPST tRRD tVTD tWPRE tWPRES tWPST tWTR tXSNR tXSRD
-0.75 0.45 0.45 1.25 -0.75 0.75 0.25 0.25 tCH,tCL -0.5 -0.5 -0.55ns
+0.75 0.55 0.55
+0.75
-0.75 0.45 0.45 -0.75
+0.75 0.55 0.55
+0.75
1.25
0.75 0.25 0.25 tCH,tCL -0.55 -0.55 -0.6ns 56.5
1.25
UNITS
NOTES
120K
120K
tRAS(MIN)-(burstlength *tCK/2)
0.25 tQH-tDQSQ
0.25 tQH-tDQSQ
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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64Mb: SDRAM
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Notes: 1-5, 14-17, notes appear pages 47-50 (0°C +70°C; VDDQ +2.65V, +2.65V)
CHARACTERISTICS PARAMETER Access window from CK/CK# high-level width low-level width Clock cycle time input hold time relative input setup time relative input pulse width (for each input) Access window from CK/CK# input high pulse width input pulse width DQS-DQ skew, last valid, group, access Write command first latching transition falling edge rising setup time falling edge from rising hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address control input hold time Address control input setup time Address control input pulse width LOAD MODE REGISTER command cycle time DQ-DQS hold, first non-valid, access ACTIVE PRECHARGE command ACTIVE READ with Auto precharge command ACTIVE ACTIVE/AUTO REFRESH command period AUTO REFRESH command period REFRESH REFRESH command interval Average periodic refresh interval ACTIVE READ WRITE delay PRECHARGE command period Read preamble Read postamble ACTIVE bank ACTIVE bank command Terminating voltage delay Write preamble Write preamble setup time Write postamble Write recovery time Internal WRITE READ command delay Exit SELF REFRESH non-READ command Exit SELF REFRESH READ command Data valid output window SYMBOL tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tIPW tMRD
tRAS tRAP tRFC tREFC tREFI tRCD tRPRE tRPST tRRD tVTD tWPRE tWPRES tWPST tWTR tXSNR tXSRD
-0.75 0.45 0.45 -0.75 0.75 0.25 tCH,tCL -0.6 -0.6 -0.65ns
+0.75 0.55 0.55
+0.75
1.25
-0.75 +0.75 0.45 0.55 0.45 0.55 -0.75 +0.75 0.75 1.25 0.25 tCH,tCL -0.65 -0.65 -0.7ns
UNITS
NOTES
tRAS(MIN)
120K 120K (burst length tCK/2) 59.5 19.5 19.5 0.25 tQH-tDQSQ
0.25 tQH-tDQSQ
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
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NOTES
voltages referenced VSS. Tests timing, IDD, electrical characteristics conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. Outputs measured with equivalent load:
Output (VOUT), Reduced Drive) Reference Point 20pF Output (VOUT), Impedance Match
Reference Point 20pF
timing tests VIL-to-VIH swing 1.5V test environment, input timing still referenced VREF crossing point CK/CK#), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals used test device 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e., receiver will effectively switch result signal crossing input level, will remain that state long signal does ring back above [below] input [HIGH] level). VREF expected equal VDDQ/2 transmitting device track variations level same. Peak-to-peak noise VREF exceed percent value. Thus, from VDDQ/2, VREF allowed ±25mV error additional ±25mV noise. applied directly device. system supply signal termination resistors, expected equal VREF must track variations level VREF. magnitude difference between input level input level CK#. value expected equal VDDQ/2 transmitting device must track variations level same. dependent output loading cycle rates. Specified values obtained with minimum cycle time Outputs open during measurements. Enables on-chip refresh address counters. specifications tested after device properly initialized.
This parameter sampled. +2.5V/+2.65V +0.1V/-0.1V, VDDQ +2.5V/+2.65V +0.1V -0.1, VREF VSS, MHz, 25°C, VOUT(DC) VDDQ/2, VOUT (peak peak) 0.2V. input grouped with pins, reflecting fact that they matched loading. Command/Address input slew rate 0.5V/ns. slew rates 1V/ns faster,tIS reduced 900ps. slew rate less than 0.5V/ns, timing must derated:tIS additional 100ps 100mV/ns reduction slew rate from 500mV/ns. slew rate exceeds 4.5V/ns, functionality uncertain. CK/CK# input reference level (for timing referenced CK/CK#) point which cross; input reference level signals other than CK/CK# VREF. Inputs recognized valid until VREF stabilizes. Exception: during period before VREF stabilizes, VDDQ recognized LOW. output timing reference level, measured timing reference point indicated Note VTT. transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ) begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, system performance (bus turnaround) will degrade accordingly. This device limit. device will operate with negative value, system performance could degraded turnaround. recommended that valid (HIGH LOW) before WRITE command. case shown (DQS going from High-Z logic LOW) applies when WRITEs were previously progress bus. previous WRITE progress, could HIGH during this time, depending tDQSS. (tRC tRFC) measurements smallest multiple that meets minimum absolute value respective parameter. tRAS (MAX) measurements largest multiple that meets maximum absolute value tRAS.
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NOTES (continued)
refresh period 32ms. This equates average refresh rate 7.8µs. However, AUTO REFRESH command must asserted least once every 70.2µs; burst refreshing posting DRAM controller greater than eight refresh cycles allowed. capacitance byte/group will differ more than this maximum amount given device. valid data window derived achieving other specifications (tCK/2), tDQSQ, [tHP 0.5ns (-5), 0.55ns (-55),tHP 0.6ns (-6) 0.65ns (-65)]. data valid window derates directly porportional with clock duty cycle practical data valid window derived. clock allowed maximum duty cycle variation 45/55. Functionality uncertain when operating beyond 45/55 ratio. data valid window derating curves provided below duty cycles ranging between 50/50 45/55. Referenced each output group: with DQ0DQ31 This limit actually nominal value does result fail value. HIGH during REFRESH command period (tRFC [MIN]) else (i.e., during standby). maintain valid level, transitioning edge input must: Sustain constant slew rate from current level through target level, VIL(AC) VIH(AC). Reach least target level. After target level reached, continue maintain least target level, VIL(DC) VIH(DC). Input capacitance group will differ more than this maximum amount given device. input slew rate must 1V/ns. input slew rates must deviate from more than 10%. DQ/DM/DQS slew rate less than 0.5V/ns, timing longer referenced mid-point VIL(AC) maximum VIH(DC) minimum points. must vary more than active while bank active.
DERATING DATA VALID WINDOW (tQH tDQSQ)
-5.5 ttCK= 5.5ns 5.5ns
1.900 1.800 1.870 1.773 1.840 1.745
1.810 1.718
1.780 1.690
1.750 1.663
1.720 1.635
1.690 1.608
1.660 1.580
1.630 1.553
1.500 1.475 1.450 1.425
1.600 1.525
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.900 1.870 1.840 1.810 1.780 1.750 1.720 1.690 1.660 1.630 1.600
Clock Duty Cycle
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NOTES (continued)
clock allowed ±175ps clock clock jitter with ±80ps cumulative jitter. Each timing parameter also allowed vary same amount. (MIN) lesser minimum minimum actually applied device inputs, collectively during bank active. READs WRITEs with autoprecharge allowed issued until tRAS (MIN) satisfied prior internal precharge command being issued. Impedance match output drive curves: full variation driver pull-down current from minimum maximum process, temperature voltage will within outer bounding lines curve Figures b)The variation driver pull-down current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figures
full variation driver pull-up current from minimum maximum process, temperature voltage will within outer bounding lines curve Figures d)The variation driver pull-up current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figures full variation ratio maximum minimum pull-up pull-down current will exceed 1.7, device drain-to-source voltages from VDDQ/2. full variation ratio nominal pull-up pull-down current should unity ±30%, device drain-to-source voltages from VDDQ/2. Reduced Output Drive Curves: full variation driver pull-down current from minimum maximum process, temperature voltage will within outer bounding lines curve Figures
Figure Pull-Down Characteristics
axim
Figure Pull-Down Characteristics
ominal
IOUT (mA)
inal
high
IOUT (mA)
inal imum
Nominal
Minimum
VOUT
VOUT
Figure Pull-Up Characteristics
Figure Pull-Up Characteristics
Maximum
Nominal high
IOUT (mA)
IOUT (mA)
-100 -120 -140 -160 -180 -200
Minimum
Nomina
inal
high
inal
VDDQ VOUT
VDDQ VOUT
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NOTES (continued)
b)The variation driver pull-down current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figures full variation driver pull-up current from minimum maximum process, temperature voltage will within outer bounding lines curve Figures d)The variation driver pull-up current within nominal limits voltage temperature expected, guaranteed, within inner bounding lines curve Figures full variation ratio maximum minimum pull-up pull-down current will exceed 1.7, device drain-to-source voltages from VDDQ/2. full variation ratio nominal pull-up pull-down current should unity ±10%, device drain-to-source voltages from 0.1V 1.0V.
Figure Pull-Down Characteristics
voltage levels used derived from referenced test load. practice, voltage levels obtained from properly terminated will provide significantly different voltage values. overshoot: (MAX) VDDQ+1.5V pulse width pulse width greater than cycle rate. undershoot: (MIN) -1.5V pulse width pulse width greater than cycle rate. must active (high) during entire time refresh command executed. That from time AUTO REFRESH command registered, must active each rising clock edge, until tREF later. When ever operating frequency altered, including jitter, required reset followed clock cycle delay. VDDQ must track each other. Will slightly adjust with VDD/VDDQ level. During initialization, VDDQ, VTT, VREF must equal less than 0.3V. Alternatively, 1.35V maximum during power even VDD/VDDQ volts, provided minimum ohms series resistance used between supply input pin. tRCD tRAP
Nominal high
IOUT (mA)
Nominal
Minimum
VOUT
Figure Pull-Down Characteristics
Figure Pull-Up Characteristics
Minimum
Nominal
IOUT (mA)
IOUT (mA)
high inal
Nomin Mini
inal
high
-100
-120
VOUT
VDDQ VOUT
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IMPEDANCE-MATCHED OUTPUT DRIVE CHARACTERISTICS
VOLTAGE PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) NOMINAL NOMINAL NOMINAL NOMINAL HIGH MINIMUM MAXIMUM HIGH MINIMUM MAXIMUM -6.1 -7.6 -4.6 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.8 63.3 63.8 64.1 64.6 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 18.2 26.9 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6
88.3 TBD-49.2 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5
NOTE: above characteristics specified under best, worst, nominal process variation/conditions.
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REDUCED OUTPUT DRIVE CHARACTERISTICS
VOLTAGE PULL-DOWN CURRENT (mA) PULL-UP CURRENT (mA) NOMINAL NOMINAL NOMINAL NOMINAL HIGH MINIMUM MAXIMUM HIGH MINIMUM MAXIMUM -3.3 -4.1 -2.5 -4.9 13.0 16.1 18.7 21.3 23.6 25.6 27.7 29.2 30.3 31.3 32.0 32.5 32.7 32.9 33.2 33.5 33.8 33.9 34.2 34.5 34.6 34.9 10.9 14.4 17.8 21.1 23.9 26.9 29.8 32.6 35.2 37.7 40.1 42.4 44.4 46.4 48.1 49.8 51.5 52.5 53.5 54.5 55.0 55.5 56.0 10.0 12.4 14.9 17.4 19.9 21.4 23.0 24.2 25.0 25.4 25.6 25.8 25.9 26.2 26.4 26.5 26.7 26.8 26.9 27.0 27.0 27.1 14.0 18.3 22.6 26.7 30.7 34.1 37.7 41.2 44.5 47.7 50.7 53.5 56.0 58.6 60.6 62.6 64.6 66.6 68.3 69.9 71.5 72.9 74.1 -6.6 -9.8 -12.9 -16.1 -18.5 -20.5 -22.2 -23.6 -24.8 -25.8 -26.6 -27.0 -27.2 -27.4 -27.5 -27.6 -27.7 -27.8 -27.9 -28.0 -28.1 -28.2 -28.2 -28.3 -7.8 -11.4 -14.9 -18.4 -21.9 -25.3 -28.7 -32.1 -35.4 -38.6 -41.9 -45.2 -48.4 -51.6 -54.7 -57.8 -60.7 -64.1 -67.0 -69.8 -72.7 -75.6 -78.4 -81.3 -5.0 -7.4 -10.0 -12.4 -14.9 -17.4 -19.5 -20.6 -20.9 -21.1 -21.2 -21.3 -21.4 -21.5 -21.6 -21.7 -21.8 -21.8 -21.9 -21.9 -22.0 -22.0 -22.1 -22.2 -9.7 -14.5 -19.2 -23.9 -28.4 -32.9 -37.3 -41.7 -46.0 -50.2 -54.3 -58.4 -62.4 -66.4 -70.4 -73.8 -77.8 -81.3 -84.7 -88.1 -91.6 -95.0 -97.9 -101.3
NOTE: above characteristics specified under best, worst, nominal process variation/conditions.
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tHP4 tHP4 tDQSQ2 tHP4 tDQSQ2 tHP4 tHP4 tDQSQ2 tHP4 tDQSQ2
DQS1
(Last data valid) (First data longer valid)
tQH3 tQH3 tQH3 tQH3
(Last data valid) (First data longer valid)
DQS, collectively5 Earliest signal transition Latest signal transition
Data Valid window
Data Valid window
Data Valid window
Data Valid window
NOTE: transitioning after transition define tDQSQ window. transitions early DQS, nominal DQS, late DQS. tDQSQ derived each clock edge cumulative over time begins with transition ends with last valid transition derived from tHP: lesser clock transition collectively when bank active. data valid window derived each transitions defined minus tDQSQ.
Figure Data Output Timing tDQSQ, tQH, Data Valid Window
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tLZ(MAX) tLZ(MIN) tRPRE (Last data valid) (First data valid) collectively3 tLZ(MIN) NOTE: tDQSCK1(MAX) tDQSCK1(MIN) tDQSCK1(MAX) tDQSCK1(MIN) tRPST tHZ(MAX) tHZ(MIN)
tLZ(MAX) tAC4(MIN)
tAC4(MAX)
tHZ(MIN) tHZ(MAX)
tDQSCK output window relative the"long term" component skew. transitioning after transition define tDQSQ window. must transition tDQSQ after transitions, regardless tAC. output window relative the"long term" component skew. tLZ(MIN), tAC(MIN) tHZ(MIN) first valid signal transition. tLZ(MAX), tAC(MAX) tHZ(MAX) latest valid signal transition. READ command with issued
Figure Data Output Timing tDQSCK
tDQSS tWPRES tWPRE tDQSL tDQSH tWPST tDSH1 tDSS2 tDSH1 tDSS2
NOTE: tDSH(MIN) generally occurs during tDQSS(MIN). tDSS(MIN) generally occurs during tDQSS(MAX). WRITE command issued
TRANSITIONING DATA DON'T CARE
Figure Data Input Timing
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VDDQ (2.3V minimum)
VOH(MIN) (1.670V SSTL2 termination) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V VIHAC
1.400V
VIHDC
1.300V 1.275V 1.250V 1.225V 1.200V
VREF VREF VREF VREF
Noise Error Error Noise
1.100V
VILDC
0.940V VINAC Provides margin between (MAX) VILAC (MAX) (0.83V2 SSTL2 termination)
VILAC
VSSQ
NOTE: (MIN) with test load 1.927V (MAX) with test load 0.373V Numbers diagram reflect nomimal values utilizing circuit below.
Reference Point
Figure Input Voltage Waveform
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INITIALIZE LOAD MODE REGISTERS
VDDQ VTT1 VREF
tVTD
LVCMOS LEVEL
COMMAND66
ACT5
A0-A7,
CODE
CODE
BANKS
BANKS
CODE
CODE
BA0,
High-Z High-Z
200µs
Power-up: stable
tMRD Load Extended Mode Register
tMRD
tRFC
tRFC5
cycles Load Mode Register2 DON'T CARE
NOTE:
applied directly device; however, tVTD must greater than equal zero avoid device latch-up. JEDEC specifies resetting with tMRD required before command applied, cycles required before READ command issued. AUTO REFRESH commands applied after LOAD MODE REGISTER (LMR) command Ta0. Although required Micron device, JEDEC specifies issuing another command prior activating bank. PRECHARGE command, LOAD MODE REGISTER command, AUTO REFRESH command, ACTIVE command, Address, Bank Address
TIMING PARAMETERS
SYMBOL
0.55 0.55 0.45 0.45 0.55 0.55 0.45 0.45
0.55 0.55 UNITS
SYMBOL
tMRD tRFC tVTD
19.5
UNITS
0.45 0.45
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POWER-DOWN MODE
tPDIX
COMMAND
VALID1
VALID
ADDR
VALID
VALID
Enter Power-Down Mode
Exit Power-Down Mode DON'T CARE
NOTE: this command PRECHARGE device already idle state), then power-down mode shown precharge power-down. this command ACTIVE least already active), then power-down mode shown active power-down. column accesses allowed progress time power-down entered.
TIMING PARAMETERS
SYMBOL
0.55 0.55 0.45 0.45 0.55 0.55 0.45 0.45
0.55 0.55 UNITS
SYMBOL
UNITS
0.45 0.45
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AUTO REFRESH MODE
VALID
VALID
COMMAND1
NOP2
NOP2
A0-A7,
BANKS
BANK
BA0, BA11
Bank(s)
DQS4
tRFC
tRFC
DON'T CARE NOTE: PRECHARGE, ACTIVE, AUTO REFRESH, Address, Bank Address. commands shown ease illustration; other valid commands possible these times. "Don't Care" HIGH this point; must HIGH more than bank active (i.e., must precharge active banks). signals "Don't Care"/High-Z operations shown. second AUTO REFRESH required only shown example back-to-back AUTO REFRESH commands.
TIMING PARAMETERS
SYMBOL
0.55 0.55 0.45 0.45 0.55 0.55 0.45 0.45
0.55 0.55 UNITS
SYMBOL
tRFC
19.5
UNITS
0.45 0.45
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SELF REFRESH MODE
CKE1
COMMAND
VALID
ADDR
VALID
tXSNR/ tXSRD
Enter Self Refresh Mode
Exit Self Refresh Mode
DON'T CARE
NOTE:
Clock must stable before exiting self refresh mode. Device must banks idle state prior entering self refresh mode. tXSNR required before non-READ command applied, tXSRD (200 cycles required before READ command applied. AUTO REFRESH command.
TIMING PARAMETERS
SYMBOL
0.55 0.55 0.45 0.45 0.55 0.55 0.45 0.45
0.55 0.55 UNITS
SYMBOL
tXSNR tXSRD
19.5
UNITS
0.45 0.45
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BANK READ WITHOUT AUTO PRECHARGE
NOP6 READ2 NOP6 PRE7 NOP6 NOP6
COMMAND5
NOP6
A0-A7
BANKS
BANK
BA0,
Bank tRCD tRAS7
Bank
Bank
Bank
Case tAC(MIN) tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
tLZ(MIN)
tLZ(MIN) tAC(MIN) tHZ(MIN)
Case tAC(MAX) tDQSCK(MAX)
tRPRE
tDQSCK(MAX) tRPST
tL(MAX)
tLZ(MAX)
tAC(MAX) tHZ(MAX)
DON'T CARE NOTE: data-out from column subsequent elements provided programmed order. Burst length case shown. Disable auto precharge. "Don't Care" HIGH PRECHARGE, ACTIVE, Address, Bank Address. commands shown ease illustration; other commands valid these times. PRECHARGE command only applied tRAS(MIN) met.
TRANSITIONING DATA
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BANK READ WITH AUTO PRECHARGE
NOP5 READ2,6 NOP5 NOP5 NOP5 NOP5
COMMAND4
NOP5
A0-A7
BA0,
Bank tRCD tRAS6 Bank
Bank
Case tAC(MIN) tDQSCK(MIN)
tRPRE
tDQSCK(MIN) tRPST
tLZ(MIN)
tLZ(MIN) tAC(MIN) tHZ(MIN)
Case tAC(MAX) tDQSC(MAX)
tRPRE
tDQSCK(MAX) tRPST
tLZ(MAX)
tLZ(MAX)
tAC(MAX) tHZ(MAX)
DON'T CARE NOTE: data-out from column subsequent elements provided programmed order. Burst length case shown. Enable auto precharge. ACTIVE, Address, Bank Address. commands shown ease illustration; other commands valid these times. READ command only applied tRAS(MIN)
TRANSITIONING DATA
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BANK WRITE WITHOUT AUTO PRECHARGE
NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6
COMMAND5
NOP6
A0-A7
BANKS
BANK
BA0,
Bank tRCD tRAS
Bank
Bank
tDQSS (NOM) tDSH7 tDSS8 tDSH7 tDSS8
tWPRES tWPRE tDQSL tDQSH tWPST
DON'T CARE TRANSITIONING DATA
NOTE: data-out from column subsequent elements provided programmed order. Burst length case shown. Disable auto precharge. "Don't Care" HIGH PRECHARGE, ACTIVE, Address, Bank Address. commands shown ease illustration; other commands valid these times. tDSH applicable during tDQSS (MIN) referenced from tDSS applicable during tDQSS (MAX) referenced from
TIMING PARAMETERS
SYMBOL
tDQSH tDQSL tDQSS tDSS
0.55 0.55 0.45 0.45 1.25 0.75 0.25 1.25 0.55 0.55 0.45 0.45 0.75 0.25
0.55 0.55 UNITS
SYMBOL tDSH
tRAS tRCD tWPRE tWPRES tWPST
0.25 0.25 120,000 19.5 19.5 0.25
UNITS 120,000
0.45 0.45 0.75 0.25
0.25 0.25
120,000
0.25
1.25
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64Mb: SDRAM
BANK WRITE WITH AUTO PRECHARGE
NOP5 WRITE2 NOP5 NOP5 NOP5 NOP5 NOP5
COMMAND4
NOP5
A0-A7
BA0,
Bank tRCD tRAS
Bank tDQSS (NOM) tDSH6 tDSS7 tDSH6 tDSS7
tWPRES tWPRE tDQSL tDQSH tWPST
DON'T CARE NOTE: data-out from column subsequent elements provided programmed order. Burst length case shown. Enable auto precharge. ACTIVE, Address, Bank Address. commands shown ease illustration; other commands valid these times. tDSH applicable during tDQSS(MIN) referenced from tDSS applicable during tDQSS (MAX) referenced from
TRANSITIONING DATA
TIMING PARAMETERS
SYMBOL
tDQSH tDQSL tDQSS tDSS
0.55 0.55 0.45 0.45 1.25 0.75 0.25 1.25 0.55 0.55 0.45 0.45 0.75 0.25
0.55 0.55 UNITS
SYMBOL tDSH
tRAS tRCD tWPRE tWPRES tWPST
0.25 0.25 120,000 19.5 19.5
UNITS 120,000
0.45 0.45 0.75 0.25
0.25 0.25
120,000
0.25
1.25
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64Mb: SDRAM
WRITE OPERATION
NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6
COMMAND5
NOP6
A0-A7
BANKS
BANK
BA0,
Bank tRCD tRAS
Bank
Bank
tDQSS (NOM) tDSH7 tDSS8 tDSH7 tDSS8
tWPRES tWPRE tDQSL tDQSH tWPST
DON'T CARE NOTE: data-out from column subsequent elements provided programmed order. Burst length case shown. Disable auto precharge. "Don't Care" HIGH PRECHARGE, ACTIVE, Address, Bank Address. commands shown ease illustration; other commands valid these times. tDSH applicable during tDQSS (MIN) referenced from tDSS applicable during tDQSS (MAX) referenced from
TRANSITIONING DATA
TIMING PARAMETERS
SYMBOL
tDQSH tDQSL tDQSS tDSS
0.55 0.55 0.45 0.45 1.25 0.75 0.25 1.25 0.55 0.55 0.45 0.45 0.75 0.25
0.55 0.55 UNITS
SYMBOL tDSH
tRAS tRCD tWPRE tWPRES tWPST
0.25 0.25 120,000 19.5 19.5 0.25
UNITS 120,000
0.45 0.45 0.75 0.25
0.25 0.25
120,000
0.25
1.25
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64Mb: SDRAM
100-PIN PLASTIC TQFP
+0.10 -0.20 22.10 ±0.10 22.10 0.65 0.32 +0.06 -0.10 0.62 DETAIL
14.00 ±0.10 16.00 ±0.20
0.15
+0.03 -0.02
1.40 ±0.05 GAGE PLANE
1.60 0.10 0.10 +0.10 -0.05 0.10 DETAIL 1.00 0.60 ±0.15 0.60 ±0.15
NOTE: Package width length include mold protrusion; allowable mold protrusion 0.25mm side.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron registered trademark Micorn logo logo trademarks Micron Technology, Inc.
64Mb: SDRAM 2M32DDR-07.p65 Rev. 9/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
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