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ACEX 1K

Programmable Logic Device Family

ACEX 1K
Programmable Logic Device Family
Data Sheet
September 2001, ver. 3.3
Features..
Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device - Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions - Dual-port capability with up to 16-bit width per embedded array block (EAB) - Logic array for general logic functions High density - 10, 000 to 100, 000 typical gates (see Table 1) - Up to 49, 152 RAM bits (4, 096 bits per EAB, all of which can be used without reducing logic capacity) Cost-efficient programmable architecture for high-volume applications - Cost-optimized process - Low cost solution for high-performance communications applications System-level features - MultiVolt I / O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices - Low power consumption - Bidirectional I / O performance (setup time tSU and clock-tooutput delay tCO) up to 250 MHz - Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Tools
Table 1. ACEX 1K Device Features Feature
Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I / O pins
EP1K10
EP1K30
EP1K50
EP1K100
Altera Corporation
A-DS-ACEX-3.3
ACEX 1K Programmable Logic Device Family Data Sheet
..and More Features
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet s
Software design support and automatic place-and-route provided by Altera development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700 / 800 workstations Flexible package options are available in 100 to 484 pins, including the innovative FineLine BGA packages (see Tables 2 and 3) Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic Notes (1), (2) 208-Pin PQFP
Table 2. ACEX 1K Package Options & I / O Pin Count Device
EP1K10 EP1K30 EP1K50 EP1K100 Notes:
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine BGA
484-Pin FineLine BGA
Tools
ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine BGA packages. Devices in the same package are pin-compatible, although some devices have more I / O pins than others. When planning device migration, use the I / O pins that are common to all devices. This option is supported with a 256-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine BGA packages.
Table 3. ACEX 1K Package Sizes Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
256-Pin FineLine BGA
484-Pin FineLine BGA
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
General Description
Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance and efficiency for data-path, register intensive, mathematical, or digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. These elements make ACEX 1K suitable for complex logic functions and memory functions such as digital signal processing, wide data-path manipulation, data transformation and microcontrollers, as required in high-performance communications applications. Based on reconfigurable CMOS SRAM elements, the ACEX 1K architecture incorporates all features necessary to implement common gate array megafunctions, along with a high pin count to enable an effective interface with system components. The advanced process and the low voltage requirement of the 2.5-V core allow ACEX 1K devices to meet the requirements of low-cost, high-volume applications ranging from DSL modems to low-cost switches. The ability to reconfigure ACEX 1K devices enables complete testing prior to shipment and allows the designer to focus on simulation and design verification. ACEX 1K device reconfigurability eliminates inventory management for gate array designs and test vector generation for fault coverage. Table 4 shows ACEX 1K device performance for some common designs. All performance results were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.
Table 4. ACEX 1K Device Performance Application Resources Used LEs EABs -1
(1) (2) This application uses combinatorial inputs and outputs. This application uses registered inputs and outputs.
Performance Speed Grade -2
Units -3
185 185 6.6 93 143 111 MHz MHz ns MHz MHz MHz
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 5 shows ACEX 1K device performance for more complex designs. These designs are available as Altera MegaCore functions. Table 5. ACEX 1K Device Performance for Complex Designs Application LEs Used -1
16-bit, 8-tap parallel finite impulse response (FIR) filter 8-bit, 512-point Fast Fourier transform (FFT) function a16450 universal asynchronous receiver / transmitter (UART) 597 1, 854 342 192 23.4 113 36
Performance Speed Grade -2
Units -3
116 38.9 68 20.5 MSPS
MHz MHz
Each ACEX 1K device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), wide data-path manipulation, microcontroller applications, and datatransformation functions. The logic array performs the same function as the sea-of-gates in the gate array and is used to implement general logic such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device. ACEX 1K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices, which configure ACEX 1K devices via a serial data stream. Configuration data can also be downloaded from system RAM or via the Altera MasterBlasterTM, ByteBlasterMVTM, or BitBlaster download cables. After an ACEX 1K device has been configured, it can be reconfigured incircuit by resetting the device and loading new data. Because reconfiguration requires less than 40 ms, real-time changes can be made during system operation. ACEX 1K devices contain an interface that permits microprocessors to configure ACEX 1K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat an ACEX 1K device as memory and configure it by writing to a virtual memory location, simplifying device reconfiguration.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
For more information on the configuration of ACEX 1K devices, see the following documents:
Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data Sheet MasterBlaster Serial / USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by Altera development systems, which are integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use devicespecific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development system includes DesignWare functions that are optimized for the ACEX 1K device architecture. The Altera development systems run on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700 / 800 workstations.
f Functional Description
For more information, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Each ACEX 1K device contains an enhanced embedded array that implements memory and specialized logic functions, and a logic array that implements general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 4, 096 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a 4-input LUT, a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic-such as 8-bit counters, address decoders, or state machines-or combined across LABs to create larger logic blocks. Each LAB represents about 96 usable logic gates. Signal interconnections within ACEX 1K devices (as well as to and from device pins) are provided by the FastTrack Interconnect routing structure, which is a series of fast, continuous row and column channels that run the entire length and width of the device. Each I / O pin is fed by an I / O element (IOE) located at the end of each row and column of the FastTrack Interconnect routing structure. Each IOE contains a bidirectional I / O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 1.1 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. Figure 1 shows a block diagram of the ACEX 1K device architecture. Each group of LEs is combined into an LAB groups of LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect routing structure. IOEs are located at the end of each row and column of the FastTrack Interconnect routing structure.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
Embedded Array Block (EAB) I / O Element (IOE)
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
Column Interconnect
Logic Array
Logic Array Block (LAB)
Row Interconnect
Logic Element (LE)
Local Interconnect Logic Array
Embedded Array
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Embedded Array Block
The EAB is a flexible block of RAM, with registers on the input and output ports, that is used to implement common gate array megafunctions. Because it is large and flexible, the EAB is suitable for functions such as multipliers, vector scalars, and error correction circuits. These functions can be combined in applications such as digital filters and microcontrollers. Logic functions are implemented by programming the EAB with a readonly pattern during configuration, thereby creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results rather than by computing them. This implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of EABs. The large capacity of EABs enables designers to implement complex functions in a single logic level without the routing delays associated with linked LEs or field-programmable gate array (FPGA) RAM blocks. For example, a single EAB can implement any function with 8 inputs and 16 outputs. Parameterized functions, such as LPM functions, can take advantage of the EAB automatically. The ACEX 1K enhanced EAB supports dual-port RAM. The dual-port structure is ideal for FIFO buffers with one or two clocks. The ACEX 1K EAB can also support up to 16-bit-wide RAM blocks. The ACEX 1K EAB can act in dual-port or single-port mode. When in dual-port mode, separate clocks may be used for EAB read and write sections, allowing the EAB to be written and read at different rates. It also has separate synchronous clock enable signals for the EAB read and write sections, which allow independent control of these sections. The EAB can also be used for bidirectional, dual-port memory applications where two ports read or write simultaneously. To implement this type of dual-port memory, two EABs are used to support two simultaneous reads or writes. Alternatively, one clock and clock enable can be used to control the input registers of the EAB, while a different clock and clock enable control the output registers (see Figure 2).
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Dedicated Inputs & Global Signals Dedicated Clocks
Note (1)
Row Interconnect
Data Out
rdaddress EAB Local Interconnect (2) wraddress
Read Address
Write Address
rden wren outclocken
Read Enable
Write Enable
inclocken
inclock outclock
Write Pulse Generator
Multiplexers allow read address and read enable registers to be clocked by inclock or outclock signals. Column Interconnect
Notes:
(1) (2) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset. EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels EP1K100 devices have 104 EAB local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in Figure 3. The ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Figure 4. ACEX 1K Device in Single-Port RAM Mode
Dedicated Clocks Dedicated Inputs & Global Signals Chip-Wide Reset
Row Interconnect
Data Out
Tools
EAB Local Interconnect (1)
Address 8, 9, 10, 11 4, 8, 16, 32
Write Enable
Column Interconnect
Note:
(1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels EP1K100 devices have 104 EAB local interconnect channels.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tools
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure to the ACEX 1K architecture, facilitating efficient routing with optimum device utilization and high performance. Figure 7 shows the ACEX 1K LAB.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 7. ACEX 1K LAB
Dedicated Inputs & Global Signals
Row Interconnect
(1) LAB Local Interconnect (2)
6 16 Carry-In & Cascade-In 2 LE1 LE2 LE3 8 4 4 4 4 4 LE4 LE5 LE6 LE7 LE8 16 6
See Figure 13 for details.
LAB Control Signals
Column-to-Row Interconnect
Column Interconnect
Carry-Out & Cascade-Out
Notes:
(1) (2) EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row EP1K100 devices have 26. EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels EP1K100 devices have 34.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can be used for clear / preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I / O signals, or internal signals via the LAB local interconnect. The LAB preset and clear control signals can be driven by the global signals, I / O signals, or internal signals via the LAB local interconnect. The global control signals are typically used for global clock, clear, or preset signals because they provide asynchronous control with very low skew across the device. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. In addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a compact size that provides efficient logic utilization. Each LE contains a 4-input LUT, which is a function generator that can quickly compute any function of four variables. In addition, each LE contains a programmable flipflop with a synchronous clock enable, a carry chain, and a cascade chain. Each LE drives both the local and the FastTrack Interconnect routing structure. Figure 8 shows the ACEX 1K LE.
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
Carry-In Cascade-In
Register Bypass
Programmable Register
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
To FastTrack Interconnect
ENA CLRN To LAB Local Interconnect
labctrl1 labctrl2
Chip-Wide Reset
Clear / Preset Logic
Clock Select
labctrl3 labctrl4
Carry-Out Cascade-Out
16 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the ACEX 1K architecture to efficiently implement high-speed counters, adders, and comparators of arbitrary width. Carry chain logic can be created automatically by the compiler during design processing, or manually by the designer during design entry. Parameterized functions, such as LPM and DesignWare functions, automatically take advantage of carry chains. Carry chains longer than eight LEs are automatically implemented by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB, or from oddnumbered LAB to odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the first LE of the third LAB in the row. The carry chain does not cross the EAB at the middle of the row. For instance, in the EP1K50 device, the carry chain stops at the eighteenth LAB, and a new carry chain begins at the nineteenth LAB. Figure 9 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for an accumulator function. Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it can be used as a general-purpose signal.
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder)
Carry-In
Register
Carry Chain LE1
Register
Carry Chain LE2
Register
Carry Chain LEn
Register
Carry-Out
Carry Chain LEn + 1
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Cascade Chain
AND Cascade Chain OR Cascade Chain
Tools
LUT LE1
LUT LE2
d(4n - 1).(4n - 4)
LUT LEn
d(4n - 1).(4n - 4)
LUT LEn
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
LE Operating Modes
The ACEX 1K LE can operate in the following four modes:
Normal mode Arithmetic mode Up / down counter mode Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE-the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE-are directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The Altera software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that use a specific LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. Figure 11 shows the ACEX 1K LE operating modes.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 11. ACEX 1K LE Operating Modes
Normal Mode
Carry-In data1 data2 data3 4-Input LUT D PRN Q LE-Out to Local Interconnect Cascade-In LE-Out to FastTrack Interconnect
ENA CLRN data4 Cascade-Out
Arithmetic Mode
Carry-In Cascade-In LE-Out data1 data2 3-Input LUT PRN D Q ENA CLRN
Tools
3-Input LUT Carry-Out Cascade-Out
Up / Down Counter Mode
Carry-In Cascade-In
data1 (ena) data2 (u / d) data3 (data)
3-Input LUT
LE-Out
3-Input LUT data4 (nload) Carry-Out Cascade-Out
ENA CLRN
Clearable Counter Mode
Carry-In
data1 (ena) data2 (nclr) data3 (data)
3-Input LUT
LE-Out
3-Input LUT data4 (nload) Carry-Out Cascade-Out
ENA CLRN
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Clearable Counter Mode The clearable counter mode is similar to the up / down counter mode, but it supports a synchronous clear instead of the up / down control. The clear function is substituted for the cascade-in signal in the up / down counter mode. Two 3-input LUTs are used one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer. The output of this multiplexer is AND ed with a synchronous clear signal.
Internal Tri-State Emulation
Tools
Clear & Preset Logic Control
Asynchronous clear Asynchronous preset Asynchronous clear and preset Asynchronous load with clear Asynchronous load with preset Asynchronous load without clear or preset
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
In addition to the six clear and preset modes, ACEX 1K devices provide a chip-wide reset pin that can reset all registers in the device. Use of this feature is set during design entry. In any of the clear and preset modes, the chip-wide reset overrides all other signals. Registers with asynchronous presets may be preset when the chip-wide reset is asserted. Inversion can be used to implement the asynchronous preset. Figure 12 shows examples of how to setup the preset and clear inputs for the desired functionality. Figure 12. ACEX 1K LE Clear & Preset Modes
Asynchronous Clear
VCC Chip-Wide Reset labctrl1 or labctrl2 PRN Q labctrl2 Chip-Wide Reset
Asynchronous Preset
Asynchronous Preset & Clear
labctrl1 PRN Q
D labctrl1 or labctrl2 Chip-Wide Reset CLRN
CLRN VCC
Asynchronous Load with Clear
NOT labctrl1 (Asynchronous Load) data3 (Data) NOT labctrl2 (Clear) Chip-Wide Reset D PRN Q
Asynchronous Load without Clear or Preset
NOT labctrl1 (Asynchronous Load) data3 (Data) D PRN Q
CLRN NOT
Asynchronous Load with Preset
NOT labctrl1 (Asynchronous Load) labctrl2 (Preset) D data3 (Data) CLRN NOT
Chip-Wide Reset
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
FastTrack Interconnect Routing Structure
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 13. ACEX 1K LAB Connections to Row & Column Interconnect
Column Channels
Row Channels
To Other Columns
At each intersection, six row channels can drive column channels.
Tools
Each LE can drive two row channels.
From Adjacent LAB To Adjacent LAB LE 1
Each LE can switch interconnect access with an LE in the adjacent LAB.
To LAB Local Interconnect
To Other Rows
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
For improved routing, the row interconnect consists of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels. The EAB drives out to the fulllength channels. In addition to providing a predictable, row-wide interconnect, this architecture provides increased routing resources. Two neighboring LABs can be connected using a half-row channel, thereby saving the other half of the channel for the other half of the row. Table 6 summarizes the FastTrack Interconnect routing structure resources available in each ACEX 1K device. Table 6. ACEX 1K FastTrack Interconnect Resources Device
EP1K10 EP1K30 EP1K50 EP1K100
Channels per Row
Columns
Channels per Column
In addition to general-purpose I / O pins, ACEX 1K devices have six dedicated input pins that provide low-skew signal distribution across the device. These six inputs can be used for global clock, clear, preset, and peripheral output-enable and clock-enable control signals. These signals are available as control signals for all LABs and IOEs in the device. The dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each LAB in the device. Figure 14 shows the interconnection of adjacent LABs and EABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. Each LAB is labeled according to its location: a letter represents the row and a number represents the column. For example, LAB B3 is in row B, column 3.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 14. ACEX 1K Interconnect Resources
See Figure 17 for details. I / O Element (IOE)
IOE IOE IOE IOE IOE IOE
Row Interconnect
LAB A1
LAB A2
LAB A3
See Figure 16 for details.
Column Interconnect
To LAB A5 To LAB A4
Tools
LAB B1
LAB B2
LAB B3
Cascade & Carry Chains
To LAB B5 To LAB B4
I / O Element
An IOE contains a bidirectional I / O buffer and a register that can be used either as an input register for external data that requires a fast setup time or as an output register for data that requires fast clock-to-output performance. In some cases, using an LE register for an input register will result in a faster setup time than using an IOE register. IOEs can be used as input, output, or bidirectional pins. The compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. For bidirectional registered I / O implementation, the output register should be in the IOE and the data input and output enable registers should be LE registers placed adjacent to the bidirectional pin. Figure 15 shows the bidirectional I / O registers.
Altera Corporation 29
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 15. ACEX 1K Bidirectional I / O Registers
Row and Column Interconnect
2 Dedicated Clock Inputs
4 Dedicated Inputs
Peripheral Control Bus
OE Register D Q
ENA CLRN
Chip-Wide Reset
VCC OE7.0
Chip-Wide Output Enable
Programmable Delay VCC
Output Register D Q
CLK1.0 CLK3.2 VCC ENA5.0 VCC CLRN1.0 ENA CLRN
Open-Drain Output Slew-Rate Control
Chip-Wide Reset Input Register
D VCC ENA CLRN Q
Chip-Wide Reset
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
On all ACEX 1K devices, the input path from the I / O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time or turn it off to minimize setup time. This feature is used to reduce setup time for complex pin-toregister paths (e.g., PCI designs). Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I / O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices and provides up to 12 peripheral control signals that can be allocated as follows:
Up to eight output enable signals Up to six clock enable signals Up to two clock signals Up to two clear signals
If more than six clock-enable or eight output-enable signals are required, each IOE on the device can be controlled by clock enable and output enable signals driven by specific LEs. In addition to the two clock signals available on the peripheral control bus, each IOE can use one of two dedicated clock pins. Each peripheral control signal can be driven by any of the dedicated input pins or the first LE of each LAB in a particular row. In addition, a LE in a different row can drive a column interconnect, which causes a row interconnect to drive the peripheral control signal. The chipwide reset signal resets all IOE registers, overriding any other control signals. When a dedicated clock pin drives IOE registers, it can be inverted for all IOEs in the device. All IOEs must use the same sense of the clock. For example, if any IOE uses the inverted clock, all IOEs must use the inverted clock, and no IOE can use the non-inverted clock. However, LEs can still use the true or complement of the clock on an LAB-by-LAB basis. The incoming signal may be inverted at the dedicated clock pin and will drive all IOEs. For the true and complement of a clock to be used to drive IOEs, drive it into both global clock pins. One global clock pin will supply the true, and the other will supply the complement. When the true and complement of a dedicated input drives IOE clocks, two signals on the peripheral control bus are consumed, one for each sense of the clock.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears, clock enables, and output enables, two signals on the peripheral control bus will be used. Table 7 lists the sources for each peripheral control signal and shows how the output enable, clock enable, clock, and clear signals share 12 peripheral control signals. Table 7 also shows the rows that can drive global signals. Table 7. Peripheral Bus Sources for ACEX Devices Peripheral Control Signal
OE0 OE1 OE2 OE3 OE4 OE5 CLKENA0 / CLK0 / GLOBAL0 CLKENA1 / OE6 / GLOBAL1 CLKENA2 / CLR0 CLKENA3 / OE7 / GLOBAL2 CLKENA4 / CLR1 CLKENA5 / CLK1 / GLOBAL3
EP1K10
EP1K30
EP1K50
EP1K100
Signals on the peripheral control bus can also drive the four global signals, referred to as GLOBAL0 through GLOBAL3. An internally generated signal can drive a global signal, providing the same low-skew, low-delay characteristics as a signal driven by an input pin. An LE drives the global signal by driving a row line that drives the peripheral bus which then drives the global signal. This feature is ideal for internally generated clear or clock signals with high fan-out. However, internally driven global signals offer no advantage over the general-purpose interconnect for routing data signals. The chip-wide output enable pin is an active-high pin that can be used to tri-state all pins on the device. This option can be set in the Altera software. The built-in I / O pin pull-up resistors (which are active during configuration) are active when the chip-wide output enable pin is asserted. The registers in the IOE can also be reset by the chip-wide reset pin.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels. Up to eight IOEs connect to each side of each row channel (see Figure 16). Figure 16. ACEX 1K Row-to-IOE Connections Note (1)
Row FastTrack Interconnect
Each IOE is driven by an m-to-1 multiplexer.
Tools
Each IOE can drive two row channels.
Note:
(1) The values for m and n are shown in Table 8.
Table 8 lists the ACEX 1K row-to-IOE interconnect resources. Table 8. ACEX 1K Row-to-IOE Interconnect Resources Device
EP1K10 EP1K30 EP1K50 EP1K100
Channels per Row (n)
Row Channels per Pin (m)
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column channels. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the column channels. Two IOEs connect to each side of the column channels. Each IOE can be driven by column channels via a multiplexer. The set of column channels is different for each IOE (see Figure 17). Figure 17. ACEX 1K Column-to-IOE Connections Note (1)
Each IOE is driven by a m-to-1 multiplexer
Column Interconnect
Each IOE can drive two column channels.
Note:
(1) The values for m and n are shown in Table 9.
Table 9 lists the ACEX 1K column-to-IOE interconnect resources. Table 9. ACEX 1K Column-to-IOE Interconnect Resources Device
EP1K10 EP1K30 EP1K50 EP1K100
Channels per Column (n)
Column Channels per Pin (m)
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
SameFrame Pin-Outs
ACEX 1K devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ballcount packages form a subset of the higher-ball-count packages. SameFrame pin-outs provide the flexibility to migrate not only from device to device within the same package, but also from one package to another. A given printed circuit board (PCB) layout can support multiple device density / package combinations. For example, a single board layout can support a range of devices from an EP1K10 device in a 256-pin FineLine BGA package to an EP1K100 device in a 484-pin FineLine BGA package. The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to lay out a board that takes advantage of this migration. Figure 18 shows an example of SameFrame pin-out. Figure 18. SameFrame Pin-Out Example
Tools
Printed Circuit Board Designed for 484-Pin FineLine BGA Package
256-Pin FineLine BGA
484-Pin FineLine BGA
256-Pin FineLine BGA Package (Reduced I / O Count or Logic Requirements)
484-Pin FineLine BGA Package (Increased I / O Count or Logic Requirements)
Table 10 shows the ACEX 1K device / package combinations that support SameFrame pin-outs for ACEX 1K devices. All FineLine BGA packages support SameFrame pin-outs, providing the flexibility to migrate not only from device to device within the same package, but also from one package to another. The I / O count will vary from device to device.
Altera Corporation 35
ACEX 1K Programmable Logic Device Family Data Sheet
For more information, search for "SameFrame" in MAX+PLUS II Help. Table 10. ACEX 1K SameFrame Pin-Out Support Device 256-Pin FineLine BGA v v v v 484-Pin FineLine BGA
EP1K10 EP1K30 EP1K50 EP1K100 Note:
This option is supported with a 256-pin FineLine BGA package and SameFrame migration.
ClockLock & ClockBoost Features
To support high-speed designs, -1 and -2 speed grade ACEX 1K devices offer ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL) that is used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-tooutput and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by sharing resources within the device. The ClockBoost feature allows the designer to distribute a lowspeed clock and multiply that clock on-device. Combined, the ClockLock and ClockBoost features provide significant improvements in system performance and bandwidth. The ClockLock and ClockBoost features in ACEX 1K devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. The ClockLock and ClockBoost circuitry lock onto the rising edge of the incoming clock. The circuit output can drive the clock inputs of registers only the generated clock cannot be gated or inverted. The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the ACEX 1K device. However, when both circuits are used, the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. Figure 19 shows the incoming and generated clock specifications. Figure 19. Specifications for the Incoming & Generated Clocks
t CLK1 t INDUTY
Note (1)
Tools
Input Clock
tF t OUTDUTY
t I + t INCLKSTB
ClockLock Generated Clock tO t O + t JITTER t O t JITTER
Note:
(1) The tI parameter refers to the nominal input clock period the tO parameter refers to the nominal output clock period.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters for -1 and -2 speed-grade devices, respectively. Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices Symbol
tR tF tINDUTY fCLK1 fCLK2 fCLKDEV Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals 1) Input clock frequency (ClockBoost clock multiplication factor equals 2) Input deviation from user specification in the Altera software (1) 40 25 16
Parameter
Condition
tOUTDUTY Duty cycle for ClockLock or ClockBoostgenerated clock
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices Symbol
tR tF tINDUTY fCLK1 fCLK2 fCLKDEV Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals 1) Input clock frequency (ClockBoost clock multiplication factor equals 2) Input deviation from user specification in the software (1) 40 25 16
Parameter
Condition
Tools
tOUTDUTY Duty cycle for ClockLock or ClockBoostgenerated clock Notes to tables:
I / O Configuration
This section discusses the PCI pull-up clamping diode option, slew-rate control, open-drain output option, and MultiVolt I / O interface for ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and open-drain output options are controlled pin-by-pin via Altera software logic options. The MultiVolt I / O interface is controlled by connecting VCCIO to a different voltage than VCCINT. Its effect can be simulated in the Altera software via the Global Project Device Options dialog box (Assign menu).
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
PCI Pull-Up Clamping Diode Option
ACEX 1K devices have a pull-up clamping diode on every I / O, dedicated input, and dedicated clock pin. PCI clamping diodes clamp the signal to the VCCIO value and are required for 3.3-V PCI compliance. Clamping diodes can also be used to limit overshoot in other systems. Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is 3.3 V, a pin that has the clamping diode option turned on can be driven by a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When VCCIO is 2.5 V, a pin that has the clamping diode option turned on can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can be activated for a subset of pins, which allows a device to bridge between a 3.3-V PCI bus and a 5.0-V device.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of 4.3 ns. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate pin-by-pin or assign a default slew rate to all pins on a device-wide basis. The slow slew rate setting affects only the falling edge of the output.
Open-Drain Output Option
ACEX 1K devices provide an optional open-drain output (electrically equivalent to open-collector output) for each I / O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane.
MultiVolt I / O Interface
The ACEX 1K device architecture supports the MultiVolt I / O interface feature, which allows ACEX 1K devices in all packages to interface with systems of differing supply voltages. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I / O output drivers (VCCIO).
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power supply, depending on the output requirements. When the VCCIO pins are connected to a 2.5-V power supply, the output levels are compatible with 2.5-V systems. When the VCCIO pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1. Table 13 summarizes ACEX 1K MultiVolt I / O support. Table 13. ACEX 1K MultiVolt I / O Support VCCIO (V) 2.5
2.5 3.3 Notes:
Input Signal (V) 3.3 v (1) v 5.0 v (1) v (1) v v
Output Signal (V) 2.5 v v (2) v v 3.3 5.0
Tools
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a higher VIH than LVTTL. When the open-drain pin is active, it will drive low. When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby meeting the CMOS VOH requirement. The open-drain pin will only drive low or tri-state it will never drive high. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor.
Power Sequencing & Hot-Socketing
Because ACEX 1K devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. The VCCIO and VCCINT power planes can be powered in any order. Signals can be driven into ACEX 1K devices before and during power up without damaging the device. Additionally, ACEX 1K devices do not drive out during power up. Once operating conditions are reached, ACEX 1K devices operate as specified by the user.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
All ACEX 1K devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be configured using the JTAG pins through the ByteBlasterMV or BitBlaster download cable, or via hardware that uses the Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD-71. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration. ACEX 1K devices support the JTAG instructions shown in Table 14.
Table 14. ACEX 1K JTAG Instructions JTAG Instruction
SAMPLE / PRELOAD
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, allowing the BST data to pass synchronously through a selected device to adjacent devices during normal operation. Selects the user electronic signature (USERCODE) register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. These instructions are used when configuring an ACEX 1K device via JTAG ports using a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or Jam Byte-Code File (.jbc) via an embedded processor.
EXTEST BYPASS
USERCODE IDCODE ICR Instructions
The instruction register length of ACEX 1K devices is 10 bits. The USERCODE register length in ACEX 1K devices is 32 bits 7 bits are determined by the user, and 25 bits are pre-determined. Tables 15 and 16 show the boundary-scan register length and device IDCODE information for ACEX 1K devices. Table 15. ACEX 1K Boundary-Scan Register Length Device
EP1K10 EP1K30 EP1K50 EP1K100
Boundary-Scan Register Length
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 16. 32-Bit IDCODE for ACEX 1K Devices Device Version (4 Bits)
EP1K10 EP1K30 EP1K50 EP1K100 Notes to tables:
Note (1) IDCODE (32 Bits)
Part Number (16 Bits)
1 (1 Bit) (2)
The most significant bit (MSB) is on the left. The least significant bit (LSB) for all JTAG IDCODEs is 1.
ACEX 1K devices include weak pull-up resistors on the JTAG pins.
For more information, see the following documents:
Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet Jam Programming & Test Language Specification
Tools
Figure 20 shows the timing requirements for the JTAG signals.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 20. ACEX 1K JTAG Waveforms
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Table 17 shows the timing parameters and values for ACEX 1K devices. Table 17. ACEX 1K JTAG Timing Parameters & Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance 20 45 35 35 35
Parameter
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Generic Testing
Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in brackets are for 2.5-V devices or outputs. Numbers without brackets are for 3.3-V devices or outputs.
VCCIO 703 481 Device Output To Test System
C1 (includes JIG capacitance)
Tools
Operating Conditions
Tables 18 through 21 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 2.5-V ACEX 1K devices. Note (1) Min
-0.5 -0.5 -2.0 -25 No bias Under bias PQFP, TQFP, and BGA packages, under bias -65 -65
Table 18. ACEX 1K Device Absolute Maximum Ratings Symbol
VCCINT VCCIO VI IOUT TSTG TAMB TJ DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature
Parameter
Supply voltage
Conditions
With respect to ground (2)
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 19. ACEX 1K Device Recommended Operating Conditions Symbol
VCCINT VCCIO
Parameter
Supply voltage for internal logic and input buffers (3), (4)
Conditions
2.625 (2.625) 3.60 (3.60) 2.625 (2.625) 5.75 VCCIO 70 85 85 100 40 40
Supply voltage for output buffers, (3), (4) 3.3-V operation Supply voltage for output buffers, (3), (4) 2.5-V operation
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
(2), (5) For commercial use For industrial use For commercial use For industrial use
Table 20. ACEX 1K Device DC Operating Conditions (Part 1 of 2) Symbol
VIH VIL VOH
Notes (6), (7) Min Typ Max
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage
Conditions
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 20. ACEX 1K Device DC Operating Conditions (Part 2 of 2) Symbol
Notes (6), (7) Min Typ Max
Parameter
3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage 3.3-V low-level PCI output voltage
Conditions
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 21. ACEX 1K Device Capacitance Symbol
CIN CINCLK COUT
Note (14) Conditions Min Max
Parameter
Input capacitance Input capacitance on dedicated clock pin Output capacitance
Notes to tables:
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 22 shows the required relationship between VCCIO and VCCINT to satisfy 3.3-V PCI compliance. Figure 22. Relationship between VCCIO & VCCINT for 3.3-V PCI Compliance
V CCINT (V) II
PCI-Compliant Region
Tools
VCCIO (V) IO
Figure 23 shows the typical output drive characteristics of ACEX 1K devices with 3.3-V and 2.5-V VCCIO. The output driver is compliant to the 3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIO pins are connected to 3.3 V). ACEX 1K devices with a -1 speed grade also comply with the drive strength requirements of the PCI Local Bus Specification, Revision 2.2 (when VCCINT pins are powered with a minimum supply of 2.375 V, and VCCIO pins are connected to 3.3 V). Therefore, these devices can be used in open 5.0-V PCI systems.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics of ACEX 1K Devices
Typical IO Output Current (mA)
VO Output Voltage (V)
Timing Model
The continuous, high-performance FastTrack Interconnect routing resources ensure accurate simulation and timing analysis as well as predictable performance. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and, therefore, have an unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters:
LE register clock-to-output delay (tCO) Interconnect delay (tSAMEROW) LE look-up table delay (tLUT) LE register setup time (tSU)
The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the ACEX 1K device. Figure 24. ACEX 1K Device Timing Model
Dedicated Clock / Input Interconnect I / O Element
Logic Element
Embedded Array Block
Figures 25 through 28 show the delays that correspond to various paths and functions within the LE, IOE, EAB, and bidirectional timing models. Figure 25. ACEX 1K Device LE Timing Model
Tools
Carry-In
Cascade-In
LUT Delay Data-In
Register Delays
tLUT tRLUT tCLUT
Packed Register Delay tPACKED Register Control Delay
t CO tCOMB t SU tH tPRE tCLR
Data-Out
Control-In
tC tEN
Carry Chain Delay tCGENR
tCGEN tCICO tLABCARRY
tCASC
tLABCASC
Carry-Out
Cascade-Out
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 26. ACEX 1K Device IOE Timing Model
Output Data Delay Data-In I / O Register Delays Output Delays
I / O Element Contol Delay Clock Enable Clear Clock Output Enable
tIOCO tIOCOMB tIOSU tIOH tIOCLR
tIOC tINREG
Input Register Delay I / O Register Feedback Delay
tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3
Data Feedback into FastTrack Interconnect
tIOFD
Input Delay
tINCOMB
Figure 27. ACEX 1K Device EAB Timing Model
EAB Data Input Delays Data-In Address Input Register Delays RAM / ROM Block Delays Output Register Delays EAB Output Delay
tEABDATA1 tEABDATA2
Write Enable Input Delays
tEABWE1 tEABWE2
EAB Clock Delay
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
Input Register Clock Output Register Clock
tAA tDD tWP tWDSU tWDH tWASU tWAH tWO tRP tRASU tRAH
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
tEABOUT
Data-Out
tEABCLK
Read Enable Input Delays RE
tEABRE1 tEABRE2
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
OE Register D PRN Q
Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
CLRN Output Register D PRN Q Bidirectional Pin
tINSUBIDIR tINHBIDIR
Input Register PRN D Q
Tables 29 and 30 show the asynchronous and synchronous timing waveforms, respectively, for the EAB macroparameters in Table 24. Figure 29. EAB Asynchronous Timing Waveforms
EAB Asynchronous Read
WE Address a0
tEABAA
Tools
tEABRCCOMB
Data-Out
EAB Asynchronous Write
tEABWP tEABWDSU tEABWDH
Data-In
tEABWASU tEABWCCOMB
tEABWAH
Address
tEABDD
Data-Out
dout2
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
EAB Synchronous Read
Address
tEABDATASU
tEABDATAH
tEABRCREG
tEABDATACO
Data-Out
EAB Synchronous Write (EAB Output Registers Used)
Data-In
Address
tEABWESU tEABDATASU
tEABDATAH
tEABWEH
tEABWCREG tEABDATACO
Data-Out
dout0
dout1
Tables 22 through 26 describe the ACEX 1K device internal timing parameters. Table 22. LE Timing Microparameters (Part 1 of 2) Symbol
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR LUT delay for data-in LUT delay for carry-in LUT delay for LE register feedback Data-in to packed register delay LE register enable delay Carry-in to carry-out delay Data-in to carry-out delay LE register feedback to carry-out delay
Note (1) Conditions
Parameter
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 22. LE Timing Microparameters (Part 2 of 2) Symbol
tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL LE register control signal delay LE register clock-to-output delay Combinatorial delay
Note (1) Conditions
Parameter
Cascade-in to cascade-out delay
LE register setup time for data and enable signals before clock LE register recovery time after asynchronous clear, preset, or load LE register hold time for data and enable signals after clock LE register preset delay LE register clear delay Minimum clock high time from clock pin Minimum clock low time from clock pin
Table 23. IOE Timing Microparameters Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB IOE data delay
Note (1) Parameter Conditions
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 24. EAB Timing Microparameters Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tAA tWP tRP tWDSU tWDH tWASU tWAH tRASU tRAH tWO tDD tEABOUT tEABCH tEABCL
Note (1) Parameter Conditions
Data or address delay to EAB for combinatorial input Data or address delay to EAB for registered input Write enable delay to EAB for combinatorial input Write enable delay to EAB for registered input Read enable delay to EAB for combinatorial input Read enable delay to EAB for registered input EAB register clock delay EAB register clock-to-output delay Bypass register delay EAB register setup time before clock EAB register hold time after clock EAB register asynchronous clear time to output delay Address access delay (including the read enable to output delay) Write pulse width Read pulse width Data setup time before falling edge of write pulse Data hold time after falling edge of write pulse Address setup time before rising edge of write pulse Address hold time after falling edge of write pulse Address setup time before rising edge of read pulse Address hold time after falling edge of read pulse Write enable to data output valid delay Data-in to data-out valid delay Data-out delay Clock high time Clock low time (5) (5) (5) (5)
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 25. EAB Timing Macroparameters Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO EAB address access delay
Notes (1), (6) Parameter Conditions
EAB asynchronous read cycle time EAB synchronous read cycle time EAB write pulse width EAB asynchronous write cycle time EAB synchronous write cycle time EAB data-in to data-out valid delay EAB clock-to-output delay when using output registers EAB data / address setup time before clock when using input register EAB data / address hold time after clock when using input register EAB WE setup time before clock when using input register EAB WE hold time after clock when using input register EAB data setup time before falling edge of write pulse when not using input registers EAB data hold time after falling edge of write pulse when not using input registers EAB address setup time before rising edge of write pulse when not using input registers EAB address hold time after falling edge of write pulse when not using input registers EAB write enable to data output valid delay
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 26. Interconnect Timing Microparameters Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC Notes to tables:
Note (1) Conditions
Parameter
Delay from dedicated input pin to IOE control input Delay from dedicated input pin to LE or EAB control input Delay from dedicated input or clock to LE or EAB data Delay from dedicated clock pin to IOE clock Delay from dedicated clock pin to LE or EAB clock Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7) same row Routing delay for an LE driving an IOE in the same column (7) Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7) row Routing delay for a row IOE or EAB driving an LE or EAB in a different row Routing delay for an LE driving a control signal of an IOE via the peripheral control bus Routing delay for the carry-out signal of an LE driving the carry-in signal of a different LE in a different LAB Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB (7) (7)
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 27 through 29 describe the ACEX 1K external timing parameters and their symbols. Table 27. External Reference Timing Parameters Symbol
Note (1) Conditions
Parameter
Register-to-register delay via four LEs, three row interconnects, and four local (2) interconnects
Table 28. External Timing Parameters Symbol
tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Parameter
Setup time with global clock at IOE register Hold time with global clock at IOE register Clock-to-output delay with global clock at IOE register Setup time with global clock for registers used in PCI designs Hold time with global clock for registers used in PCI designs Clock-to-output delay with global clock for registers used in PCI designs (3) (3) (3)
Conditions
Tools
Table 29. External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes to tables:
Note (3) Conditions
Parameter
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. Contact Altera Applications for test circuit specifications and test conditions. These timing parameters are sample-tested only. This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local Bus Specification, Revision 2.2.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 30 through 36 show EP1K10 device internal and external timing parameters. Table 30. EP1K10 Device LE Timing Microparameters Symbol -1 Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL 2.0 2.0 0.7 0.9 0.8 0.9 2.5 2.5
Note (1) Unit -3 Max
Speed Grade -2 Max
1.1 0.8 1.0 0.5 1.3 0.2 0.7 0.2 1.1 1.7 0.9 0.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.4 1.4 ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 31. EP1K10 Device IOE Timing Microparameters Symbol -1 Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB 1.3 0.9 1.1 3.1 2.6 5.8 3.8 3.8 3.3 6.5 3.7 0.9 1.9
Note (1) Unit -3 Max
Speed Grade -2 Max
4.0 0.5 1.4 0.0 ns ns ns ns ns ns 1.7 4.1 3.9 8.3 5.9 5.9 5.7 10.1 5.7 1.4 3.0 ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 32. EP1K10 Device EAB Internal Microparameters Symbol -1 Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tAA tWP tRP tWDSU tWDH tWASU tWAH tRASU tRAH tWO tDD tEABOUT tEABCH tEABCL 1.5 2.7 2.7 1.0 1.0 0.1 1.8 1.9 3.1 0.2 2.7 2.7 0.5 2.0 2.8 1.0 0.5 0.3 3.4 2.8 1.0 1.0 0.1 1.9 2.0 3.5 0.2
Note (1) Unit -3 Max
Speed Grade -2 Max
1.9 0.7 1.2 0.4 0.9 0.4 0.0 0.3 0.6 ns ns ns ns ns ns ns ns ns ns ns ns 3.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 33. EP1K10 Device EAB Internal Timing Macroparameters Symbol -1 Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO 1.6 0.0 1.4 0.1 1.6 0.0 3.1 0.6 5.4 6.7 4.7 2.7 6.4 7.4 6.0 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.4 0.5 5.8
Note (1) Unit -3
Speed Grade -2 Max
7.3 ns ns ns ns ns ns 6.5 0.9 ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 34. EP1K10 Device Interconnect Timing Microparameters Symbol -1 Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1) Unit -3
Speed Grade -2 Max
3.6 1.4 1.8 3.6 1.4 0.2 2.9 0.7 3.6 6.5 4.8 0.5 1.4 ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 35. EP1K10 External Timing Parameters Symbol -1 Min
tDRR tINSU (2), (3) tINH (2), (3) tOUTCO (2), (3) tINSU (4), (3) tINH (4), (3) tOUTCO (4), (3) tPCISU (3) tPCIH (3) tPCICO (3) 2.4 0.0 2.0 1.4 0.5 0.0 3.0 0.0 2.0 6.0 5.1 6.6
Note (1) Speed Grade -2 -3 Max
12.5 ns ns ns 9.6 - ns ns ns ns ns ns 10.2 ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 36. EP1K10 External Bidirectional Timing Parameters Symbol -1 Min
tINSUBIDIR (2) tINHBIDIR (2) tOUTCOBIDIR (2) tXZBIDIR (2) tZXBIDIR (2) tINSUBIDIR (4) tINHBIDIR (4) tOUTCOBIDIR (4) tXZBIDIR(4) tZXBIDIR (4) Notes to tables:
Notes (1), (3) Unit -3
Speed Grade -2 Max Min
ns ns 9.6 14.0 14.0 - ns ns ns ns ns ns
All timing parameters are described in Tables 22 through 29 in this data sheet. This parameter is measured without the use of the ClockLock or ClockBoost circuits. These parameters are specified by characterization. This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tools
Tables 37 through 43 show EP1K30 device internal and external timing parameters. Table 37. EP1K30 Device LE Timing Microparameters (Part 1 of 2) Symbol -1 Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO Altera Corporation
Note (1) Unit -3
Speed Grade -2 Max
1.1 0.8 1.0 0.5 1.0 0.2 0.7 0.2 1.0 0.0 0.5 ns ns ns ns ns ns ns ns ns ns ns
ACEX 1K Programmable Logic Device Family Data Sheet
Table 37. EP1K30 Device LE Timing Microparameters (Part 2 of 2) Symbol -1 Min
tCOMB tSU tH tPRE tCLR tCH tCL 2.0 2.0 0.4 0.7 0.8 0.8 2.5 2.5
Note (1) Unit -3
Speed Grade -2 Max
0.6 ns ns ns 1.2 1.2 ns ns ns ns
Table 38. EP1K30 Device IOE Timing Microparameters Symbol -1 Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB 1.2 0.3 1.0 1.9 1.4 4.4 2.7 2.7 2.2 5.2 3.4 0.8 0.8
Note (1) Unit -3 Max
Speed Grade -2 Max
3.8 0.5 1.6 0.0 ns ns ns ns ns ns 1.6 3.0 2.5 7.0 4.3 4.3 3.8 8.3 5.5 2.4 2.4 ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 39. EP1K30 Device EAB Internal Microparameters Symbol -1 Min
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tAA tWP tRP tWDSU tWDH tWASU tWAH tRASU tRAH tWO tDD tEABOUT tEABCH tEABCL 1.5 2.5 2.5 0.9 0.9 0.1 1.7 1.8 3.1 0.2 2.5 2.5 0.5 2.0 2.9 0.9 0.4 0.3 3.2 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2
Note (1) Unit -3 Max
Speed Grade -2 Max
2.3 0.8 1.4 0.5 1.0 0.5 0.0 0.4 0.7 ns ns ns ns ns ns ns ns ns ns ns ns 4.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 40. EP1K30 Device EAB Internal Timing Macroparameters Symbol -1 Min
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO 1.5 0.0 1.3 0.0 1.5 0.0 3.0 0.5 5.1 6.4 4.4 2.5 6.0 6.8 5.7 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 6.0
Note (1) Unit -3
Speed Grade -2 Max
8.8 ns ns ns ns ns ns 7.7 1.1 ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 41. EP1K30 Device Interconnect Timing Microparameters Symbol -1 Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1) Unit -3
Speed Grade -2 Max
2.9 2.4 2.2 3.0 2.4 0.3 2.7 0.8 3.5 6.2 3.8 0.5 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns
Tools
Table 42. EP1K30 External Timing Parameters Symbol -1 Min
tDRR tINSU (3) tINH (3) tOUTCO (3) tINSU (4) tINH (4) tOUTCO (4) tPCISU tPCIH tPCICO 2.1 0.0 2.0 1.1 0.0 0.5 3.0 0.0 2.0 6.0 3.9 4.9
Notes (1), (2) Speed Grade -2 -3 Max
12.5 ns ns ns 7.6 ns ns ns - ns ns ns - ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 43. EP1K30 External Bidirectional Timing Parameters Symbol -1 Min
tINSUBIDIR (3) tINHBIDIR (3) tINSUBIDIR (4) tINHBIDIR (4) tOUTCOBIDIR (3) tXZBIDIR (3) tZXBIDIR (3) tOUTCOBIDIR (4) tXZBIDIR (4) tZXBIDIR (4) Notes to tables:
Notes (1), (2) Unit -3
Speed Grade -2 Max Min
All timing parameters are described in Tables 22 through 29 in this data sheet. These parameters are specified by characterization. This parameter is measured without the use of the ClockLock or ClockBoost circuits. This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 44 through 50 show EP1K50 device external timing parameters.
Table 44. EP1K50 Device LE Timing Microparameters (Part 1 of 2) Symbol -1 Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC
Note (1) Unit -3
Speed Grade -2 Max
1.1 0.8 0.9 0.4 0.9 0.1 0.6 0.1 1.0 0.8 ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 44. EP1K50 Device LE Timing Microparameters (Part 2 of 2) Symbol -1 Min
tCO tCOMB tSU tH tPRE tCLR tCH tCL 2.0 2.0 0.5 0.5 0.4 0.8 2.5 2.5
Note (1) Unit -3
Speed Grade -2 Max
0.7 0.5 ns ns ns ns 0.7 1.2 ns ns ns ns
Table 45. EP1K50 Device IOE Timing Microparameters Symbol -1 Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB 0.8 0.4 0.2 1.2 0.7 2.7 4.7 4.7 4.2 6.2 3.5 1.1 1.1
Note (1) Unit -3
Speed Grade -2 Max
Tools
1.9 0.4 2.6 0.8 ns ns ns ns ns ns 0.4 1.9 1.7 4.3 7.5 7.5 7.3 9.9 5.6 1.8 1.8 ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 46. EP1K50 Device EAB Internal Microparameters Symbol -1 Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tAA tWP tRP tWDSU tWDH tWASU tWAH tRASU tRAH tWO tDD tEABOUT tEABCH tEABCL 1.5 1.5 2.0 1.0 0.5 0.1 1.0 1.5 1.5 0.1 2.1 2.1 0.0 2.0 2.0 0.7 0.4 0.8 2.0 2.8 1.4 0.7 0.1 1.4 2.1 2.1 0.1
Note (1) Unit -3 Max
Speed Grade -2 Max
3.2 0.8 1.9 0.0 0.0 0.8 0.0 1.5 0.0 ns ns ns ns ns 3.8 ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 47. EP1K50 Device EAB Internal Timing Macroparameters Symbol -1 Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO 1.1 0.0 0.7 0.4 1.2 0.0 1.6 0.9 3.1 3.7 3.5 2.0 4.5 5.6 3.8 0.8 1.6 0.0 1.0 0.6 1.7 0.0 2.3 1.2 4.3
Note (1) Unit -3
Speed Grade -2 Max
7.0 ns ns ns ns ns ns 7.2 1.5 ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 48. EP1K50 Device Interconnect Timing Microparameters Symbol -1 Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1) Unit -3
Speed Grade -2 Max
4.6 2.7 5.1 2.6 2.7 0.2 2.4 2.1 4.5 6.9 3.4 0.2 1.3 ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 49. EP1K50 External Timing Parameters Symbol -1 Min
tDRR tINSU (2) tINH (2) tOUTCO (2) tINSU (3) tINH (3) tOUTCO (3) tPCISU tPCIH tPCICO 2.4 0.0 2.0 2.4 0.0 0.5 2.4 0.0 2.0 6.0 3.3 4.3
Note (1) Speed Grade -2 -3 Max
12.5 ns ns ns 7.3 ns ns ns - ns ns ns - ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 50. EP1K50 External Bidirectional Timing Parameters Symbol -1 Min
tINSUBIDIR (2) tINHBIDIR (2) tINSUBIDIR (3) tINHBIDIR (3) tOUTCOBIDIR (2) tXZBIDIR (2) tZXBIDIR (2) tOUTCOBIDIR (3) tXZBIDIR (3) tZXBIDIR (3) Notes to tables:
Note (1) Unit -3
Speed Grade -2 Max Min
ns ns ns ns 7.3 10.1 10.1 - - - ns ns ns ns ns
All timing parameters are described in Tables 22 through 29. This parameter is measured without use of the ClockLock or ClockBoost circuits. This parameter is measured with use of the ClockLock or ClockBoost circuits
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 51 through 57 show EP1K100 device internal and external timing parameters. Table 51. EP1K100 Device LE Timing Microparameters Symbol -1 Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL 1.5 1.5 0.4 0.5 0.8 0.8 2.0 2.0
Note (1) Unit -3 Max
Speed Grade -2 Max
1.5 0.9 1.1 0.5 0.3 0.2 0.7 0.2 1.2 1.4 1.1 0.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.4 1.4 ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 52. EP1K100 Device IOE Timing Microparameters Symbol -1 Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB 0.8 0.7 0.5 3.0 3.0 4.0 3.5 3.5 3.5 4.5 2.0 0.5 0.5
Note (1) Unit -3 Max
Speed Grade -2 Max
2.6 0.0 2.1 0.9 ns ns ns ns ns ns 0.9 5.6 5.6 7.3 6.1 6.1 6.1 7.8 3.5 1.2 1.2 ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 53. EP1K100 Device EAB Internal Microparameters Symbol -1 Min
tEABDATA1 tEABDATA1 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tAA tWP tRP tWDSU tWDH tWASU tWAH tRASU tRAH tWO tDD tEABOUT tEABCH tEABCL 1.5 2.7 2.7 1.0 1.0 0.2 1.6 1.6 3.0 0.1 1.5 1.5 0.2 2.0 3.5 0.8 0.1 0.3 4.0 3.5 1.3 1.3 0.2 2.1 2.1 3.9 0.1 2.0 2.0 0.3
Note (1) Unit -3 Max
Speed Grade -2 Max
2.6 0.0 2.6 0.5 0.5 0.0 0.0 0.5 0.2 ns ns ns ns ns ns ns ns ns ns ns ns 6.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 54. EP1K100 Device EAB Internal Timing Macroparameters Symbol -1 Min
tEABAA tEABRCOMB tEABRCREG tEABWP tEABWCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO 0.8 0.1 1.1 0.0 1.0 0.2 4.1 0.0 3.4 5.9 5.1 2.7 5.9 5.4 3.4 0.5 1.0 0.1 1.4 0.0 1.3 0.2 5.2 0.0 4.5
Note (1) Unit -3
Speed Grade -2 Max
9.9 ns ns ns ns ns ns 5.9 0.8 ns ns ns ns ns ns ns ns ns ns ns
Tools
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 55. EP1K100 Device Interconnect Timing Microparameters Symbol -1 Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1) Unit -3
Speed Grade -2 Max
4.4 0.5 2.0 1.4 0.5 0.2 3.4 1.6 5.0 8.4 6.5 0.9 1.4 ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 56. EP1K100 External Timing Parameters Symbol -1 Min
tDRR tINSU (3) tINH (3) tOUTCO (3) tINSU (4) tINH (4) tOUTCO (4) tPCISU tPCIH tPCICO 2.0 0.0 2.0 2.0 0.0 0.5 3.0 0.0 2.0 6.0 3.0 5.2
Notes (1), (2) Unit -3 Max
Speed Grade -2 Max
16.0 ns ns ns 9.1 ns ns ns