V830 Application Note Features Complete Application Note des

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V830 Application Note Features Complete Application Note des

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9080/V830
V830 Application
Note Features
Complete Application Note designing adapter embedded system based V830 processor including: Detailed Design Description OrCad Schematics Verilog Source Code Superior performance based 9080 master interface chip which supports: burst master, slave cycles configuration cycles Asynchronous PCI/ V830 operation I2OMessaging Unit Combined with PLX's I2OSDK® provides powerful tool developing V830-based
General Description
This application note describes interface V830 using 9080 "PCI Local Bridge" information used build either adapter embedded system. 9080 Direct Master, Direct Slave data transfer capabilities. Direct Master mode allows device (V830) Local perform memory, I/O, configuration cycles bus. Direct Slave gives master device ability access memory Local Bus. 9080 allows Local asynchronously through bi-directional FIFOs.
9080
AD[31:0] CBE[3:0] FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# RST# LA[31:2] LBE[3:0] LD[31:0] LHOLD LHOLDA ADS# LW/R# READY# READYo# LINTi# LINTo# BLAST# BTERM# EOT[1:0]# WAITi# LSERR# DREQ[1:0]# DACK[1:0]# DIOEND# LLOCKo# LLOCKi# BREQ DMPAF# USERi# USERo# BREQo# WAITo# LRESETo# +VDD LCLK ASEL CMODE SIZ1CD DCLK GLUE LOGIC (PLD) HLDRQ# HLDAK# DCYST# R/W# READY# NMI# INTV[3:0]# ST[3:0]
V830
Figure V830 Interface. V830 subsystem
V830
Application Note
Technology, Inc.
V830
Application Note
Technology, Inc.
Table Contents: 9080 OVERVIEW.4 FEATURES.4 GENERAL DESCRIPTION APPLICATIONS 9080 Adapter Cards.5 Embedded Systems MAJOR FEATURES V830 OVERVIEW V830 FEATURES INTRODUCTION V830 INTERFACE 9080 LOCAL ARBITRATION.8 CLOCKS INTERRUPTS.9 DIRECT MASTER MODE DIRECT SLAVE MODE CONTROLLER. GLUE LOGIC. SRAM. DRAM. UART. SQUALL CONNECTOR MEMORY PCI9080 CONFIGURATION REGISTERS. Extra Long EEPROM Load. VERILOG SOURCE CODE GLUE LOGIC
V830
Application Note
Internal Registers
Config. Local Config. Run-Time Messaging
Technology, Inc.
EEPROM Initialization
State Machines
Initiator (for Direct Master Xfers) Target (for Direct Slave Xfers) Initiator (For Xfers) Initiator (For Xfers)
FIFOs
Dir. Master Write Dir. Master Read Dir. Slave Write Dir. Slave Read DMA1 PCI/Loc DMA1 Loc/PCI DMA0 PCI/Loc DMA0 Loc/PCI
Local State Machines
Local Slave (for Direct Master Xfers) Local Master (for Direct Slave Xfers) Local Master (For Xfers)
Local Interface: Select Width 8,16 Endian Conversion Select Muxed non-Muxed Addr/Data
Interface Arbiter
Local Master (For Xfers)
Control Logic
Messaging
Chaining
Unaligned Xfer
Figure 9080 Internal Block Diagram
9080 Overview
Features
Version compliant Master Interface chip adapters embedded systems Compatible Messaging Unit Volt signaling, volt core, low-power CMOS 208-pin PQFP independent channels local memory to/from host data transfers Eight programmable FIFOs zero wait state burst operation Local data transfers MB/sec Programmable local supports nonmultiplexed 32-bit address/data, multiplexed bit, slave accesses local devices Local runs asynchronously Eight mailbox doorbell registers Performs Endian/Little Endian conversion Upward compatibility with 9060/9060ES/9060SD (See compatibility notes)
General Description
9080 provides compact, high performance master interface adapter boards embedded systems. programmable local chip configured directly connect wide variety processors, controllers memory subsystems. 9080 contains Intelligent (I2O) messaging unit that allows high performance compatible software implementations protocol specification. Users 9060, 9060ES 9060SD chips upgrade their products support I2O, Volts other features with little change existing hardware software. 9080 provides independent chaining channels with bi-directional FIFOs supporting zero wait state burst transfers between host local memory. Slave transfers performed through third FIFO. fourth FIFO allows local processor other controllers perform direct master transfers bus. 9080 also allows local processor configure other devices system
V830
Application Note
Applications 9080
Adapter Cards
Major adapter card applications 9080 include high performance communications, networking, disk control, multimedia video adapters. 9080 moves data between host adapter local several ways. First, local host processor program controller 9080 move data between adapter memory host bus. Second, 9080 perform "Direct Master Transfers," whereby local controller accesses directly through master transfer. 9080 also supports slave transfers which another device master. Finally, 9080 contains complete messaging unit with mailbox registers, doorbell registers queue management pointers that used message passing under protocol custom protocol.
Technology, Inc. both Read- Write-enable high-performance bursting local buses. Direct Slave. 9080 supports both memory mapped mapped burst accesses local from bus. Bi-directional FIFOs both Read- Write-enable high-performance bursting local buses. Host Capability. direct master mode, 9080 generate Type Type configuration cycles. Programmable Local Modes. 9080 master interface chip that connects three local types, selected through mode pins. 9080 connected local with similar design with little glue logic. Table lists three modes: Table 0-1. Programmable Local Modes
Mode Description 32-bit address/32-bit data, non-multiplexed 32-bit address/32-bit data, multiplexed 32-bit address/16-bit data, multiplexed
Embedded Systems
Another application 9080 embedded systems, such network hubs routers, printer engines industrial equipment. this configuration, four above-mentioned data transfer modes used. addition, 9080 supports Type Type configuration cycles, which allows embedded embedded system host configure other devices system.
Interrupt Generator. 9080 generate local interrupts from several sources. Clock. 9080 local interface runs from local clock generates necessary internal clocks. This clock runs asynchronously clock. Volt Volt Operation. 9080 provides either Volt Volt signaling bus. signaling environment requires VCC. local environment requires VCC. Serial EEPROM Interface. 9080 contains optional serial EEPROM interface that used load configuration information. This useful loading information that unique particular adapter (such Network Vendor ID). Mailbox Registers. 9080 contains eight mailbox registers that accessed from either local bus. Doorbell Registers. 9080 includes doorbell registers. generates interrupts from local bus. other generates interrupts from local bus. Unaligned Transfer Support. 9080 transfer data byte boundary. Big/Little Endian Conversion. 9080 supports dynamic switching between Endian Little Endian operations.
Major Features
Compliant. 9080 compliant with aspects specification version 2.1. Messaging Unit. 9080 incorporates messaging unit. This enables adapter embedded system communicate with other I2Osupported devices. messaging unit fully compatible with extension Version specification. Dual Independent Programmable Controllers with Bi-directional FIFOs. 9080 provides independently programmable controllers with bi-directional FIFOs each channel. Each channel supports both non-chaining chaining modes demand mode DMA. Direct Master. 9080 supports both memory mapped burst transfer accesses mapped single transfer accesses local from bus. 9080 also supports interlock ("LOCK#") cycles. Bi-directional FIFOs
V830
Application Note
Technology, Inc.
V830 Overview
V830 microprocessor first V830 family product offered data processing applications. V830 high-performance 32-bit RISC microprocessor. With operation(internal) frequency 100MHz, V830 perform data processing demanded multimedia devices only cycles. Besides high interrupt responsibility optimized pipeline structure, sum-ofproducts instruction, double-word shift instruction, high-speed branch instruction using branch prediction have been added support multimedia functions. Furthermore, inheriting V810 family basic instruction object level, V810 Family software used V830 offers high-performance data processing applications such image processing, game machines, navigation, high-performance TVs, color facsimile machines, etc.
General-purpose registers: bits Instruction set:
V810 basic instruction Sum-of-products operation (32bits 32bits (upper/lower) 32bits): cycles Saturatable arithmetic operation (with saturation detection function) Double-word shift (64-bit data shift): cycles High-speed branch Block transfer instruction
Memory space: Memory space, space: 4G-byte Linear addressing External interface:
Supports (16byte) burst cycles. Address/Data separate hold lock Four Chip Select outputs
Internal memory:
Instruction cache (direct mapping): bytes Data cache (direct mapping/writethrough): bytes Instruction RAM: bytes Data RAM: bytes Interrupts: Non-maskable interrupt (NMI), levels maskable interrupt. Power control: stop mode sleep mode.
V830 Features
Number instructions: Minimum number instruction execution cycles:
Package: CMOS 144-pin plastic LQFP (fine
pitch) mm).
V830
Application Note
Introduction
This application note describes interface V830, 32-bit microprocessor, using 9080 Bridge chip I2O-ready applications. This application note demonstrates connection between 9080 bridge chip, V830, SRAM, UART, FLASH EEPROM, DRAM glue logic. addition 9080's direct master direct slave transfer capabilities, this application will controllers 9080 Bridge chip transfer data both directions. Direct Slave mode will used access local memory spaces (32bit address space 4Gbyes.) Direct Master mode used local master(s) (V830 this case)
Technology, Inc. access 32bit local memory spaces including 9080 internal registers memory spaces (All 32-bit memory spaces excluding memory spaces assigned current 9080 Direct slave memory spaces Space Space Expansion ROM, Time internal memory spaces 256bytes.) PCI9080 allows local operate asynchronously through bi-directional FIFOs. this application operates while local also clocked 33MHz (Asynchronous clock). V830 internal operating frequency doubled tripled local clock frequency. following block diagram shows basic connections between major components required this application.
V830
GLUE: DRAM CONTROLLER V830 INTERFACE LOCAL ARBITER
DRAM LOAL
PCI9080
SRAM
FLASH/ROM
SQUALL MODULE CONNECTOR
PHOTOTYPE AREA
V830
Application Note
Technology, Inc.
V830 interface 9080 local
V830 access devices local glue logic. V830 signals translated 9080 local signals: BCYST# ADS#, READYo9080# READY830, ST[3:0] LLOCK9080, BLAST#, etc. Please refer glue logic source code other translated signals. Software access local peripherals simply addressing correctly. Please refer local address each local device. V830 access memory spaces 9080 Direct Master interface glue logic. 9080 provides memory space (window), space which used V830 access device port. This space also used generating Configuration Cycles. Please refer 9080 data book more information.
clock (PCLK): clock from host system. Local clock (LCLK): same BCLK V830 V830 clock (BCLK): Clock output from U301 oscillator. V830 internal clock: jumper JP300 BCLK 100MHz Jumper installed JP300 BCLK 66Mhz
Note: CMODE pull-down resistor.
Arbitration
arbitration done arbiter. local arbitration done 9080RDK-V830 local arbiter. special cases, where local other device then 9080 V830, LHOLD LHOLDA tied HLDRQ# HLDAK# inverters. this application note, local arbitrated between 9080, V830, Squall master (SQLBR#, SQLBG#) glue logic. exclusive cycle LOCK# signal also supported when V830 generates Lock Read/Write cycles. When status information, ST[3:0], `1011b', glue logic asserts LLOCK# during ADS# cycle indicate this locked direct master cycle. Note that locked cycle must start with read followed write cycle. 9080 support many writes reads after first read cycle with LLOCK#. turn, 9080 will assert LOCK# signal locked transaction. Please refer Specification 9080 data book further information.
Clocks
PCI9080 allows local operate asynchronously through bidirectional FIFOs. this application operates MHz, MHz, while local clocked 33MHz. V830 internal clock (66MHz) (100MHz) local clock rate jumper settings. Please refer schematic proper settings.
V830
Application Note
Interrupts
Local Interrupt Input (LINTi#) used generate interrupt (INTA#) when abnormal situation arises from local glue logic from V830. V830 also generate interrupt 9080 internal doorbell registers. doorbell register interrupt must cleared from side. Please refer 9080 data book further information. local interrupt output (LINTo#) used V830 internal interrupt controller. LINTo# active because more tasks done, such done interrupt, more error have occurred during operation. Please refer 9080 data book further information interrupts. V830 built interrupt controller with NMI#, INT, four interrupt vector input pins (INTV[3:0]#). Because constraint, interrupt logic been implemented discrete logic. LINTo9080# from 9080, UART interrupt (INTUART#), interrupts from Squall module ORed generate V830 interrupt input (INT830). 9080 interrupt input (LINTI9080#) also generated with above logic (Note that LINTI9080# excludes LINTO9080). Please refer schematic more information. When INTUART# active, example, INTUART# activates INT830 INTV1# indicate interrupt vector 1101b. LINTO9080#, LINTSQL0#, LINTSQL1# interrupt vector 1110b, 1011b, 0111b respectively. interrupts served from V830, local interrupt input (LINTI9080#) should disabled 9080 internal register. interrupts routed bus, host software needs find which device generated interrupt reading respective interrupt sources when interrupt (INTA#) active. Note that interrupt sources must level triggered. addition interrupts better performance, this application note supports system error Dead-Lock backoff mechanism. When system error detected 9080, 9080 will generate System Error (SERR#) Local System Error (LSERR#). Please refer Spec. 9080 data book conditions this error generation. These system errors should routed host processor. this application, LSERR# routed NMI# V830 (NMI830#). Another type system error Dead-Lock. Please refer 9080 data book further information Partial Full Dead-Lock. When 9080 detects possible Dead-Lock situation,
Technology, Inc. mainly Direct Slave Direct Master cycle occurring same time programmed amount time expires, 9080 outputs BREQO9080. This signal also generates NMI830# request back-off from V830. V830 MUST release wait until BREQO9080 deasserted. Without V830 backoff, local will hang PCI9080 will issue continuous RETRYs master device responsible Direct Slave cycle. V830 check LSERR# BREQO9080 reading 9080 internal status information. Reading 9080 internal register allowed after V830 gives Direct Master access (V830 accessing bus.) These signals also disabled.
V830
Application Note
Direct Master Mode
Direct Master read/write cycle generated V830 Squall Module Master device. other words, V830 Squall Module Master starts cycle. address must match Range Direct master base address programmed 9080 internal register order recognized Direct Master Access 9080. Direct Master memory cycle should between 8000 0000h 8FFF FFFFh cycle should between A000 0000h AFFF FFFFh. turn, 9080 will generate appropriate cycles: memory, I/O, configuration cycle. starting address, that when Direct Master memory cycle address 8000 0000h, programmed Re-Map address register 9080. example, local Direct Master address 8008 0000h, then address will 0008 0000h Re-Map Register Direct Master contains 0000 0003h indicates that memory cycles enabled. Therefore, basic Re-Map address 0000 0000h). Re-Map address changed on-the-fly. Note that Range Register must power Re-Map base address value must multiple Range(not Range Register value). Where Range Register value inverse Range. Device Configuration cycle also supported. embedded system, immediate 9080 internal registers programmed V830 accessing memory region defined, starting from 3000 0000h. Simple memory read/write modify internal register. V830 needs configure other device, V830 needs generate Configuration cycle 9080. Please refer 9080 data book more detailed information. environment, most initializations done system BIOS.
Technology, Inc. sequence. When BIOS scans devices, BIOS will assign base address each address space found. Base, Range, ReMap, Region Descriptor Register must programmed correctly before local access attempted. Note: Additional register such Arbitration Register need programmed. Please refer memory 9080 data book detailed internal register locations. Please refer initial register value this document.
Direct Slave Mode
Direct Slave read/write cycle performed host local through 9080 local interface logic. Space Space Expansion space 9080 used access local peripherals such SRAM, DRAM, UART, Squall connector, etc. user must assign Range Register values Space Space Expansion space serial EEPROM local processor (V830) during power Note that Range Register assignment must occur before BIOS scans bus. Re-Map Register Region Descriptor assigned same time after power-up
V830
Application Note
Controller
9080 built-in independent controllers. These controllers support data transfer size, 1Gbyte time, from local bus, from local bus. controller supports normal mode, chained mode, demand mode. normal mode, user must program 9080 internal registers (DMA mode, starting address, Local starting address, byte count, direction transfer(PCI Local, Local PCI)) enable/start bits kick transfer. addition above registers, user program FIFO control registers, done interrupts, etc. Please refer 9080 data book more information. chained mode, user must generate more chain information either local memory space. mode register must indicate that current transfer chained current channel (channel mode register. Finely, user must write location first descriptor (memory address side Local side). Once start written, controller reads first descriptor, which contains information about current transfer, next descriptor location chain. controller transfers data when done, reads next descriptor there any. Demand Mode utilizes Request (DREQ#, input controller) Acknowledge (DACK#, output from controller) handshake signals control flow data. setup controller either normal chained transfer with demand mode turned control register. controller will read first descriptor information chained transfer mode will start data transfer until DREQ# asserted from local bus. When DREQ# asserted, controller will arbitrate both side (Local PCI). When controller gets local bus, controller asserts DACK# start current data transfer. DREQ# deasserted during data transfer, controller will pause data transfer deassert DACK# release both side bus. data transfer resumed asserting DREQ# again. data transfer aborted writing abort control register. (Demand Mode supported current board.)
Technology, Inc. addition three transfer mode, 9080 supports Transfer(EOT[1:0]#) pins terminate current DMA. This mode supported current board.
GLUE LOGIC
most flexibility comprehensive interface between 9080, V830, peripherals Altera EPF8452AQC160 used glue logic. This glue logic interfaces between 9080 V830, DRAM controller, SRAM control signals, Squall control signals, UART control signals, FLASH control signals. DRAM, SRAM, UART,FLASH accessed from host 9080, V830, Squall master module.
SRAM
512Kbytes SRAM board. These SRAM read with wait state (ws) written with wait state. address counter provided (74FCT163) faster address valid time, address provided 9080 V830 address used instead.
DRAM
DRAM controller resides inside glue logic provide DRAM control signals well address lines signals. 4MB, 8BM, 16MB, 32MB Fast Page Mode DRAM module used.
UART
UART, serial port, used remote monitoring control. V830 monitor directly controlled this serial port terminal connection.
SQUALL CONNECTOR
other master device(s), such Ethernet networking card, connected Squall connector which accessible host processor V830. Please refer Squall Connector specifications. Check Cyclone site (www.cyclone.com) Intel site (www.intel.com) more information Squall connector.
Memory
0000 0000 0FFF FFFF V830 internal (not accessible from external) 1000 0000 1FFF FFFF DRAM region 2000 0000 2FFF FFFF SRAM region
V830 Application Note 3000 0000 3FFF FFFF 9080 internal registers region 4000 0000 4FFF FFFF 5000 0000 5FFF FFFF 6000 0000 6FFF FFFF 7000 0000 7FFF FFFF 8000 0000 8FFF FFFF Direct Master Memory region
Technology, Inc. 9000 0000 9FFF FFFF A000 0000 AFFF FFFF Direct Master region B000 0000 BFFF FFFF C000 0000 CFFF FFFF Squall Module region D000 0000 DFFF FFFF UART region E000 0000 EFFF FFFF FE00 0000 FE00 0FFF V830 Build-in instruction FF00 0000 FFFF FFFF FLASH region
V830
Application Note
Technology, Inc.
PCI9080 Configuration Registers
following configuration registers must programmed (from serial EEPROM) before Direct Slave Direct Master accesses. Note that Start (and DREQ0# demand mode DMA) must after registers programed order controller start.
Extra Long EEPROM Load
EEPROM Offset
EEPROM Value
9080 10B5 0680 0002 0000 0100 0123 4567 89AB CDEF FF00 0000 2000 0001 0000 0000 0000 0000 0000 0000 FF00 0000 4903 00C3 F000 0000 8000 0000 A000 0000 0000 0003 0000 0000 0830 10B5 FF00 0000 1000 0001 0000 00C3 0000 0000
Description
Device Vendor Class Code Class Code, Revision Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Mailbox (User Defined) Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space (POINT SRAM) Local Base Address (Remap) Local Address Space Local Arbitration Register Local Arbitration Register Local Big/Little Endian Descriptor Register Local Big/Little Endian Descriptor Register Range Local Expansion Range Local Expansion Local Base Address (Remap) Local Expansion (POINT FLASH) Local Base Address (Remap) Local Expansion Region Descriptors Local Accesses Region Descriptors Local Accesses range Direct Master (256MB) range Direct Master Local Base Address Direct Master Memory Local Base Address Direct Master Memory Local Address Direct Master IO/CFG Local Address Direct Master IO/CFG Base Address (Remap) Direct Master Base Address (Remap) Direct Master Configuration Address Register Direct Master IO/CFG Configuration Address Register Direct Master IO/CFG Subsystem Subsystem Vendor Range Local Address Space Range Local Address Space Local Base Address (Remap) Local Address Space (POINT DRAM) Local Base Address (Remap) Local Address Space Region Descriptors (Space Local Accesses Region Descriptors (Space Local Accesses Base Address local expansion Base Address local expansion
V830
Application Note
Technology, Inc.
VERILOG SOURCE CODE GLUE LOGIC
INCLUDE "arb"; INCLUDE "dram"; INCLUDE "led"; INCLUDE "memdec"; INCLUDE "reset"; INCLUDE "sram"; INCLUDE "v830-9080";
SUBDESIGN 9080V830
Input pins V830 /hldak830 /bcyst /wr830 /st[3.0] int830 INPUT; HoldAcknoledge from V830 INPUT; write/read signal form v830 INPUT; form v830 INPUT; status bits INPUT; interrupt input(this goes V830 too) -need generate LINTi9080#, input 9080
-PCI 9080 lclk la[31.2] /lbe[3.0] /ads /lwr /blast /den /wait /readyo9080 breqo9080 /lreseto9080 hold9080 user9080 /locko9080 /dack09080 /dack19080 /lserr9080 /ldshold9080 -Squall /sqlbr sqlsda sqlscl /locksql /sqlextend -Misc
INPUT; local (common) INPUT; address INPUT; local byte enables (common) address strobe (common) write/read# (common) burst last (common) data enable transceivers (common) wait wait states (common) INPUT; ready from 9080 INPUT; request output 9080 INPUT; local reset from 9080 INPUT; hold from 9080 INPUT; user from 9080 INPUT; lock from 9080 INPUT; from 9080 INPUT; from 9080 INPUT; Local system error from 9080 INPUT; Direct Slave Hold request from 9080
INPUT; request from Squall INPUT; squall serial data line eeprom INPUT; squall serial eeprom clock INPUT; lock input from Squall INPUT; squall extend
V830
/por2 srcy
Application Note
INPUT; local reset from power-on reset circuit INPUT;
Technology, Inc.
output pins -v830 /hldrq830 /ready830 /nmi830 -Arbitration breq9080 hlda9080 /lock9080 /sqlbg /readysql /lreset 9080debug failo /cs9080 /cssql /cssram /csflash /csuart -PCI 9080 /waiti9080 /bterm9080 /lreset 9080debug /ready9080 /dreq09080 /dreq19080 -Flash, UART /flashoe /flashwe /uartr uartw /ioads /iobuf -SRAM /sramoe /srinc /sramwe[3.0] -DRAM /dramwe /dramras[3.0] /dramcas[3.0] drama[10.0] OUTPUT; Dram write enable OUTPUT; Dram Address Strobe OUTPUT; Dram Column Address Strobe OUTPUT; Dram Multiplexed addresses OUTPUT; OUTPUT; OUTPUT; OUTPUT; 9080 chip select OUTPUT; Squall chip select OUTPUT; SRAM chip select OUTPUT; Flash chip select OUTPUT; Uart chip select OUTPUT; Hold request OUTPUT; Ready signal OUTPUT; input 830(when LSERR BREQo#)
OUTPUT; request 9080 OUTPUT; hold ack. 9080 OUTPUT; lock input 9080 OUTPUT; grant Squall OUTPUT; ready signal OUTPUT; local reset signal OUTPUT; debug mode output OUTPUT; failed mode output
OUTPUT; wait input 9080 OUTPUT; terminate 9080 OUTPUT; local reset (active low) OUTPUT; 9080 bedug output OUTPUT; local Ready 9080 OUTPUT; 9080 OUTPUT; 9080
OUTPUT; Flash output enable OUTPUT; Flash write enable OUTPUT; Uart Read OUTPUT; Uart Write (Note: active high) OUTPUT; uart OUTPUT; data tranceiver enable Flash Uart
VARIABLE sm_clk
NODE; State machine clock
V830
sm_rst /readydram /readyflash /readysram -boffok /readyuart count[8.0] BEGIN ready signals
Application Note
NODE; State machine reset NODE; local ready NODE; local ready NODE; NODE; NODE; local ready DFF;
Technology, Inc.
/ready9080 (/readydram /readyflash /readysql readysram /readyuart); /ready830=(/readydram /readyflash /readysql /readysram /readyuart /readyo9080);
These signals presently unused this design. -unused pins 9080 -/bigend9080 -useri9080 -/eot0 -/eot1 -/dack09080 -/dack19080 /bterm9080 '1'; /dreq09080 '1'; /dreq19080 '1'; /waiti9080 '1'; breq9080 '0'; /locksql vcc; used /lreseti9080 vcc; used
Local Arbitration (/lock9080, /hldrq830, breq9080, hlda9080, hlda9080, /sqlbg) (sm_clk, sm_rst, hold9080, /hldak830, /sqlbr, /locko9080) DRAM Controller (/dramwe, /dramras[3.0], /dramcas[3.0], drama[10.0], /readydram) dram (sm_clk, sm_rst, la[31.2], /wait, /blast, /ads, /lwr, /lbe[3.0], /den); Controller (failo, 9080debug) user9080); Memory Decoder (/cs9080, /csflash, /csuart, /cssql, /flashoe, /flashwe, /iobuf, /uartr, uartw, /readyflash, /readyuart, /ioads) memdec (la[31.24], /ads, /blast, sm_clk, sm_rst, /lwr, /wait, /den, /readysql); SRAM Controller (/sramwe[3:0], /sramoe, /srinc, /readysram, /cssram) sram (sm_clk, sm_rst, /blast, /lwr, srcy, la[31.24], /ads, /lbe[3:0]); -v830-9080 (/ready830, /nmi830, /ads, /blast, /lwr v830-9080 (sm_clk, sm_rst, /st[3:0], /lserr9080, /wr830, readyo9080, /bcyst, breqo9080); State machine Reset Logic sm_clk global(lclk); sm_rst dffe(vcc, sm_clk, !(!/por2 !/lreseto9080), count[2]); Local Reset Logic /lreset !(!/por2 !sm_rst /lreseto9080); Reset Timer
V830
count[].clk lclk; count[].clrn !(!/por2 !/lreseto9080); count[] count[]
Application Note
Technology, Inc.
END;
V830
Application Note
Technology, Inc.
Arbiter (Local bus) SUBDESIGN sm_clk sm_rst hold9080 /hldak830 /sqlbr /locko9080
INPUT; state machine clock INPUT; state machine reset INPUT; request from 9080 INPUT; grant from V830 INPUT; squall request INPUT; locked output from 9080
/lock9080 /hldrq830 breq9080 hlda9080 /sqlbg
OUTPUT; LOCK INPUT 9080 OUTPUT; request V830 OUTPUT; OUTPUT; grant 9080 OUTPUT; grant squall
-following signals used yet. -Squall Lock, Direct slave Lock, Demand DMA(/Dack[1:0]9080, Dreq[1:0]9080, EOT[1:0], etc), Sqlsda,Sqlscl,/Sqlextend -Bterm9080, waiti9080, etc. int830 /dack09080 /dack19080 sqlsda sqlscl /sqlextend /locksql /ldshold9080 /lock9080 /waiti9080 /bterm9080 /dreq09080 /dreq19080 INPUT; interrupt input(this goes V830 too) need generate LINTi9080#, input 9080 INPUT; from 9080 INPUT; from 9080 INPUT; squall serial data line eeprom INPUT; squall serial eeprom clock INPUT; squall extend INPUT; lock input from Squall INPUT; Direct Slave Hold request from 9080 OUTPUT; lock input 9080 OUTPUT; wait input 9080 OUTPUT; terminate 9080 OUTPUT; 9080 OUTPUT; 9080
VARIABLE MACHINE BITS (q[3.0]) WITH STATES idle 9080 wait
b"0001", b"0010", b"0100", b"1000",
V830 default master
BEGIN DEFAULTS /hldrq830 vcc; breq9080 gnd; hlda9080 gnd; /sqlbg vcc;
V830
idle DEFAULTS; sm.clk sm_clk; sm.reset !sm_rst;
Application Note
Technology, Inc.
Arbiter. CASE WHEN idle v830 control /hldrq830 vcc; don't request from v830 (hold9080) THEN /hldrq830 gnd; -request from v830 9080; ELSEIF (!/sqlbr) THEN /hldrq830 gnd; sql; ELSE idle; WHEN 9080 9080 wants (!/hldak830) THEN -V830 gives hlda9080 vcc; -grant 9080 wait; ELSEIF (/locko9080) THEN locked with 9080, Grant 9080. 9080; ELSEIF (!hold9080) THEN idle; ELSE 9080; WHEN squall master wants (!/hldak830) THEN -V830 gives /sqlbg gnd; -grant squall master wait; ELSEIF (/sqlbr) THEN idle; ELSE sql; WHEN wait wait before release 9080 squall (!hold9080) THEN 9080 gives hlda9080= gnd; -remove holda9080 idle; ELSEIF (/sqlbr) THEN squall master gives /sqlbg= vcc; -remove grant from squall master idle; ELSE wait;
CASE; END;
V830
Application Note
Technology, Inc.
DRAM (Address 0x10000000)
SUBDESIGN dram sm_clk sm_rst la[31.2] /wait /blast /ads /lwr /lbe[3.0] /den /dramwe /dramras[3.0] /dramcas[3.0] drama[10.0] /readydram
INPUT; state machine's clock INPUT; state machine's reset INPUT; INPUT; Wait from 9080 V830 INPUT; INPUT; INPUT; INPUT; INPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT;
VARIABLE /ras /cas[3.0] /csdram count[8.0] ref_req /mux ref_cyc cpu_cyc hold_off NODE; NODE; NODE; DFF; refresh counter NODE; refresh request NODE; NODE; NODE; NODE; NODE;
rassm
MACHINE BITS (a[1.0]) WITH STATES rasidle rasactive MACHINE BITS (b[4.0]) WITH STATES muxidle muxwait muxwait1 muxwait2 muxactive
b"01", b"10");
muxsm
b"00001", b"00010", b"00100", b"01000", b"10000");
cas0sm MACHINE BITS (c[1.0]) WITH STATES cas0idle cas0active cas1sm MACHINE BITS (d[1.0]) WITH STATES cas1idle
b"01", b"10");
b"01",
V830
cas1active cas2sm MACHINE BITS (e[1.0]) WITH STATES cas2idle cas2active cas3sm MACHINE BITS (f[1.0]) WITH STATES cas3idle cas3active drdysm MACHINE BITS (g[1.0]) WITH STATES drdyidle drdyactive b"10");
Application Note
Technology, Inc.
b"01", b"10");
b"01", b"10");
b"01", b"10");
cpu_cycsm MACHINE BITS (h[1.0]) WITH STATES cpu_cycidle cpu_cycactive ref_cycsm MACHINE BITS (i[1.0]) WITH STATES ref_cycidle ref_cycactive ref_reqsm MACHINE BITS (j[1.0]) WITH STATES ref_reqidle ref_reqactive hold_offsm MACHINE BITS (k[1.0]) WITH STATES hold_offidle hold_offactive addrsm MACHINE BITS (l[3.0]) WITH STATES addridle addrs1 addrs2 addrs3
b"01", b"10");
b"01", b"10");
b"01", b"10");
b"01", b"10");
b"0001", b"0010", b"0100", b"1000");
BEGIN DEFAULTS /ras gnd; /cas[3.0] vcc; /readydram vcc; /mux vcc; ref_cyc gnd; cpu_cyc gnd; ref_req gnd; hold_off gnd; DEFAULTS; inactive inactive
V830
rassm.clk sm_clk; rassm.reset !sm_rst; muxsm.clk sm_clk; muxsm.reset !sm_rst; cas0sm.clk sm_clk; cas0sm.reset !sm_rst; cas1sm.clk sm_clk; cas1sm.reset !sm_rst; cas2sm.clk sm_clk; cas2sm.reset !sm_rst; cas3sm.clk sm_clk; cas3sm.reset !sm_rst; drdysm.clk sm_clk; drdysm.reset !sm_rst; cpu_cycsm.clk sm_clk; cpu_cycsm.reset !sm_rst; ref_cycsm.clk sm_clk; ref_cycsm.reset !sm_rst; ref_reqsm.clk sm_clk; ref_reqsm.reset !sm_rst; hold_offsm.clk sm_clk; hold_offsm.reset !sm_rst; addrsm.clk sm_clk; addrsm.reset !sm_rst;
Application Note
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common all. Bytes selected using /dramras0 /ras; /dramras1 /ras; /dramras2 /ras; /dramras3 /ras;
/dramcas[3.0] /cas[3.0]; /dramwe !(!/den /lwr !ref_cyc !/ras);
count[].clk sm_clk; count[].clrn !ref_req; count[] count[] /csdram !(!/ads (la[31.28] H"1") (count[7] b"1") (count[3] b"1"); Control State Machine CASE rassm WHEN rasidle /ras vcc; (!/csdram /mux !ref_req) (cpu_cyc !ref_cyc) (!/cas0 ref_cyc) THEN rassm rasactive; ELSE rassm rasidle; WHEN rasactive
V830
Application Note
/ras gnd; (!/blast !/readydram) THEN rassm rasidle; ELSIF (/cas0 ref_cyc) THEN rassm rasidle; ELSE rassm rasactive;
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CASE;
Control State Machine CASE muxsm WHEN muxidle -drama[10.2] la[21.13]; drama[9.2] la[21.14]; drama[10] la[23]; (!/ras) THEN muxsm muxwait; ELSE muxsm muxidle; WHEN muxwait -drama[10.2] la[21.13]; drama[9.2] la[21.14]; drama[10] la[23]; muxsm muxwait1; WHEN muxwait1 -drama[10.2] la[21.13]; drama[9.2] la[21.14]; drama[10] la[23]; muxsm muxwait2; WHEN muxwait2 -drama[10.2] la[21.13]; drama[9.2] la[21.14]; drama[10] la[23]; muxsm muxactive; WHEN muxactive /mux gnd; drama[9.2] la[11.4]; drama[10] la[22]; (/ras) THEN muxsm muxidle; ELSE muxsm muxactive; CASE;
CAS0 Control State Machine CASE cas0sm WHEN cas0idle (!/ras !/mux !/lbe0 !ref_cyc) (!cpu_cyc ref_req) THEN cas0sm cas0active; ELSE cas0sm cas0idle; WHEN cas0active /cas0 gnd; (!ref_cyc) (!/ras ref_cyc) THEN cas0sm cas0idle; ELSE cas0sm cas0active; CASE; CAS0 Control State Machine
V830
Application Note
Technology, Inc.
CASE cas1sm WHEN cas1idle (!/ras !/mux !/lbe1 !ref_cyc) (!cpu_cyc ref_req) THEN cas1sm cas1active; ELSE cas1sm cas1idle; WHEN cas1active /cas1 gnd; (!ref_cyc) (!/ras ref_cyc) THEN cas1sm cas1idle; ELSE cas1sm cas1active; CASE;
CAS2 Control State Machine CASE cas2sm WHEN cas2idle (!/ras !/mux !/lbe2 !ref_cyc) (!cpu_cyc ref_req) THEN cas2sm cas2active; ELSE cas2sm cas2idle; WHEN cas2active /cas2 gnd; (!ref_cyc) (!/ras ref_cyc) THEN cas2sm cas2idle; ELSE cas2sm cas2active; CASE;
CAS3 Control State Machine CASE cas3sm WHEN cas3idle (!/ras !/mux !/lbe3 !ref_cyc) (!cpu_cyc ref_req) THEN cas3sm cas3active; ELSE cas3sm cas3idle; WHEN cas3active /cas3 gnd; (!ref_cyc) (!/ras ref_cyc) THEN cas3sm cas3idle; ELSE cas3sm cas3active; CASE;
DRDY Control State Machine CASE drdysm WHEN drdyidle (!/ras !/mux !ref_cyc) THEN drdysm drdyactive; ELSE drdysm drdyidle; WHEN drdyactive /readydram gnd; (!ref_cyc) THEN drdysm drdyidle; ELSE
V830
CASE;
Application Note
drdysm drdyactive;
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CPU_CYC Control State Machine CASE cpu_cycsm WHEN cpu_cycidle (!/csdram) THEN cpu_cycsm cpu_cycactive; ELSE cpu_cycsm cpu_cycidle; WHEN cpu_cycactive cpu_cyc vcc; (!/blast !/readydram) THEN cpu_cycsm cpu_cycidle; ELSE cpu_cycsm cpu_cycactive; CASE;
REF_CYC Control State Machine CASE ref_cycsm WHEN ref_cycidle (!cpu_cyc ref_req) THEN ref_cycsm ref_cycactive; ELSE ref_cycsm ref_cycidle; WHEN ref_cycactive ref_cyc vcc; (/ras !/mux) THEN ref_cycsm ref_cycidle; ELSE ref_cycsm ref_cycactive; CASE;
REF_CYC Control State Machine CASE ref_reqsm WHEN ref_reqidle !hold_off) THEN ref_reqsm ref_reqactive; ELSE ref_reqsm ref_reqidle; WHEN ref_reqactive ref_req vcc; (ref_cyc) THEN ref_reqsm ref_reqidle; ELSE ref_reqsm ref_reqactive; CASE; HOLD_OFF Control State Machine CASE hold_offsm WHEN hold_offidle (ref_cyc) THEN hold_offsm hold_offactive; ELSE hold_offsm hold_offidle;
V830
Application Note
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WHEN hold_offactive hold_off vcc; (!r4) THEN hold_offsm hold_offidle; ELSE hold_offsm hold_offactive; CASE;
CASE addrsm WHEN addridle (/mux) THEN -drama[1] la[12]; -drama[0] la[11]; drama[1] la[13]; drama[0] la[12]; ELSE drama[1] la[3]; drama[0] la[2]; generate next addresses (!/readydram /blast !la[3] !la[2]) THEN addrsm addrs1; ELSIF (!/readydram /blast la[3] !la[2]) THEN addrsm addrs3; ELSE addrsm addridle; WHEN addrs1 generate drama[0] vcc; drama[1] gnd; (!/readydram /blast) THEN addrsm addrs2; ELSIF (!/readydram !/blast) THEN addrsm addridle; ELSE addrsm addrs1; WHEN addrs2 generate drama[0] gnd; drama[1] vcc; (!/readydram /blast) THEN addrsm addrs3; ELSIF (!/readydram !/blast) THEN addrsm addridle; ELSE addrsm addrs2; WHEN addrs3 generate drama[0] vcc; drama[1] vcc; (!/readydram !/blast) THEN addrsm addridle; ELSE addrsm addrs3; CASE;
V830
END;
Application Note
Technology, Inc.
V830
Application Note
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SUBDESIGN user9080 failo 9080debug
INPUT; User 9080 OUTPUT; Fail OUTPUT; debug
-VARIABLE BEGIN 9080debug (!user9080); failo 9080debug; END;
V830
Application Note
Technology, Inc.
Memory dec., FLASH controller UART controller V830 internal DRAM address SRAM address PCI9080 internal register Direct Master memory Direct Master Squall module UART V830 Build FLASH :0000 0000h 0FFF FFFFh :1000 0000h 1FFF FFFFh :2000 0000h 2FFF FFFFh :3000 0000h 3FFF FFFFh 8000 0000h 8FFF FFFFh A000 0000h AFFF FFFFh C000 0000h CFFF FFFFh D000 0000h DFFF FFFFh FE00 0000h FE00 0FFFh FF00 0000h FFFF FFFFh
SUBDESIGN memdec sm_clk sm_rst la[31.24] /ads /blast /lwr /wait /den /readysql /cs9080 /csflash /csuart /cssql /flashoe /flashwe /iobuf /uartr uartw /readyflash /readyuart /ioads
INPUT; state machine clock INPUT; state machine reset INPUT; address address strobe burst last signal write/read~ wait wait states data enable used with tranceiver INPUT; ready from squall OUTPUT; 9080 Registers Chip Select OUTPUT; FLASH Chip Select OUTPUT; UART Chip Select OUTPUT; Squall Chip Select OUTPUT; FLASH Output Enable OUTPUT; FLASH Write Enable OUTPUT; tranceiver Enable OUTPUT; UART read OUTPUT; UART Write (active high) OUTPUT; ready flash OUTPUT; ready UART OUTPUT; UART
VARIABLE CS9080 CSFLASH CSSQL CSUART /cntclr cnten /iobufuart count[8.0] NODE; NODE; NODE; NODE; :NODE; :NODE; NODE; DFFE;
csflashsm MACHINE BITS (q[4.0]) WITH STATES csflashidle
b"00001",
V830
csflashactive csflashwait csflashactive2 csflashready csuartsm MACHINE BITS (r[4.0]) WITH STATES csuartidle csuartactive csuartactive1 csuartactive2 csuartactive3
Application Note
b"00010", b"00100", b"01000", b"10000");
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b"00001", b"00010", b"00100", b"01000", b"10000");
BEGIN DEFAULTS /csflash vcc; /readyflash vcc; /cntclr vcc; cnten vcc; /iobufuart vcc; /readyuart vcc; /ioads vcc; /uartr vcc; uartw gnd; DEFAULTS; csflashsm.clk sm_clk; csflashsm.reset !sm_rst; csuartsm.clk sm_clk; csuartsm.reset !sm_rst; count[].clk sm_clk; count[].clrn !(!sm_rst !/cntclr); count[].ena vcc; count[] count[]
Memory dec. dram.tdf file dram decoding. CSSRAM (la[31.24] H"20"); 0x20000000 2FFF FFFFh CS9080 (la[31.24] H"30"); 0x30000000 3FFF FFFFh Direct Master decodings done inside 9080. CSSQL (la[31.24] H"C0"); 0xC0000000 CFFF FFFFh CSUART (la[31.24] H"D0"); 0xD0000000 DFFF FFFFh CSFLASH (la[31.24] H"FF"); 0xFF000000 FFFF FFFFh /cs9080 !(CS9080 !/ads); /cssql dff( (CSSQL !/ads) (!/cssql (/readysql)) sm_clk, sm_rst /csuart dff( (CSUART !/ads) (!/csuart (/readyuart)) sm_clk, sm_rst /csflash !CSFLASH; FLASH controller UART controller
V830
data tranceiver control line /iobuf (!/csflash !/iobufuart) !/den); FLASH control lines -/flashoe !(!/csflash !/lwr); -/flashwe !(!/csflash /lwr !/wait); /flashoe gnd; /flashwe vcc;
Application Note
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CSFLASH Control State Machine wait state using /ready CASE csflashsm WHEN csflashidle /csflash vcc; (CSFLASH !/ads) THEN csflashsm csflashactive; ELSE csflashsm csflashidle; WHEN csflashactive (!/wait) THEN csflashsm csflashwait; ELSE csflashsm csflashactive2; WHEN csflashwait (!/wait) THEN csflashsm csflashwait; ELSE csflashsm csflashidle; WHEN csflashactive2 csflashsm csflashready; WHEN csflashready /readyflash gnd; (/blast /wait) THEN csflashsm csflashidle; ELSE csflashsm csflashready; CASE;
CSUART Control State Machine wait state using /ready CASE csuartsm WHEN csuartidle UART Idle State /cntclr gnd; /iobufuart vcc; (!/csuart) THEN csuartsm csuartactive; ELSE csuartsm csuartidle; WHEN csuartactive Continue assert /ioads gnd; (count[] THEN csuartsm csuartactive1; ELSE csuartsm csuartactive; WHEN csuartactive1 Enable buffer uartw /lwr; /uartr /lwr; (count[] THEN /iobufuart gnd;
V830
ELSE
Application Note
csuartsm csuartactive2;
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csuartsm csuartactive1; WHEN csuartactive2 wait again while enabled csuartsm csuartactive3; WHEN csuartactive3 assert ready /readyuart gnd; csuartsm csuartidle; CASE;
END;
V830
Application Note
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reset SUBDESIGN reset /lreseto9080 /por2 lclk /lreset VARIABLE count[8.0] BEGIN count[].clk lclk; count[].clrn /por2; count[] count[] /lreset dffe(vcc, lclk, /por2 lreseto9080, (count[] END; DFFE;
INPUT; 9080 local reset INPUT; Power-on reset INPUT; OUTPUT;
V830
Application Note
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there wait states SRAM writes. SRAM
SUBDESIGN sram sm_clk sm_rst /blast /lwr srcy la[31.24] /ads /lbe[3.0] /sramwe[3.0] /sramoe /srinc /readysram /cssram VARIABLE CSSRAM NODE;
INPUT; state machine's clock INPUT; state machine's reset INPUT; INPUT; INPUT; address INPUT; :OUTPUT; OUTPUT; OUTPUT; OUTPUT; OUTPUT;
sramsm MACHINE BITS (a[4.0]) WITH STATES sramidle sramreadwrite sramread sramwritewait sramwrite BEGIN DEFAULTS /readysram vcc; /cssram gnd; DEFAULTS; sramsm.clk sm_clk; sramsm.reset !sm_rst;
b"00001", b"00010", b"00100", b"01000", b"10000");
/srinc gnd; /sramoe /lwr; CSSRAM (la[31.24] H"20"); 0x20000000 2fffffff /cssram dff( (CSSRAM !/ads) (!/cssram /readysram) sm_clk, sm_rst /sramwe0 !(/lwr !/lbe0); /sramwe1 !(/lwr !/lbe1); /sramwe2 !(/lwr !/lbe2); /sramwe3 !(/lwr !/lbe3);
SRAM Control State Machine wait read, wait write CASE sramsm WHEN sramidle
V830
Application Note
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/cssram vcc; (CSSRAM !/ads) THEN sramsm sramreadwrite; ELSE sramsm= sramidle; WHEN sramreadwrite /cssram gnd; (/lwr) THEN write sramsm= sramwritewait; ELSE read sramsm= sramread; WHEN sramread /readysram gnd; /cssram gnd; (!/blast) THEN sramsm sramidle; ELSE sramsm sramread; WHEN sramwritewait /cssram gnd; sramsm sramwrite; WHEN sramwrite /readysram gnd; /cssram gnd; (!/blast) THEN sramsm sramidle; ELSE sramsm sramwrite; CASE; END;
V830
Application Note
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V830 9080 interface.
SUBDESIGN v830-9080 sm_clk sm_rst /st[3.0] /lserr9080 /wr830 readyo9080 /bcyst breqo9080 /ready830 /nmi830
INPUT; state machine clock INPUT; state machine reset INPUT; status bits INPUT; local system error from 9080 INPUT; V830 write# read INPUT; ready 9080 INPUT; from V830 INPUT; back-off-request-out from 9080 OUTPUT; ready signal V830 OUTPUT; nmi# either back-off local system error
/ads /blast /lwr
local bus. blast(burst last) local bus.
VARIABLE MACHINE BITS (q[6.0]) WITH STATES idle single burst0 burst1 burst2 burst3 locked_dm
b"0000001", b"0000010", b"0000100", b"0001000", b"0010000", b"0100000", b"1000000",
V830 default master
BEGIN DEFAULTS /ready830 '1'; /lock9080 '1'; /nmi830 '1'; /ads '1'; /blast '1'; /lwr '1'; /lock9080 '1'; /nmi '1'; idle DEFAULTS;
sm.clk sm_clk; sm.reset !sm_rst;
Unconditional back-off request system error from PCI9080 V830 when DEAD-LOCK ocurrs. 9080 will generate BREQo# signal when possible dead-lock exists.
V830
Application Note
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When BREQo# LSERR# asserted, this logic will assert NMI# V830 (system errors) Software needs take care these situations. /nmi830 !(/lserr9080 breqo9080);
/lwr !(/wr830);
Direct master local access V830. CASE WHEN idle /ads '1'; /ready830 '1'; /blast '1'; (!/bcyst (st[3.0]='0000' st[3.0]='1000' st[3.0]='1001')) THEN /ads '0'; single; ELSEIF (!/bcyst (st[3.2]='11')) THEN /ads '0'; burst0; ELSEIF (!/bcyst (st[3.0]='1011')) THEN /ads '0'; /lock9080 '0'; locked_dm; ELSE idle;
WHEN single -single cycle /ads '1'; /blast '0'; (!(/readyo9080)) THEN /ready830 '0'; /blast '1'; idle; ELSE single; WHEN burst0 Burst mode(first data) /ads '1'; (!(/readyo9080)) THEN /ready830 burst1; ELSE burst0; WHEN burst1 Burst mode(second data) (!(/readyo9080)) THEN /ready830 burst2; ELSE /ready830 '1'; burst1; WHEN burst2 Burst mode(3rd data) (!(/readyo9080)) THEN /ready830 burst3; ELSE /ready830 '1';
V830
burst2;
Application Note
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WHEN burst3 Burst mode(4th data) /blast '0'; (!(/readyo9080)) THEN /ready830 idel; ELSE /ready830 '1'; burst3; WHEN locked_dm Locked cycle bus(must start with read with write) /ads '1'; /blast '0'; ((!/readyo9080) (/wr830)) THEN /ready830 '0'; idle; ((!/readyo9080) (!/wr830)) THEN /ready830 '0'; /lock9080 '1'; idle; ELSE locked_dm
CASE; END;

V830 Application Note Features Complete Application Note des

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