M8051 Warp Internal Data Memory External SFRs Microcontrolle

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M8051 Warp Internal Data Memory External SFRs Microcontrolle

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InventraM8051Warp-A1 8051-Compatible Microcontroller
M8051 Warp
Internal Data Memory External SFRs
Microcontroller/processor FPGA
M8051 Warp features:
Core SFRs External Data Memory 16bit Registers Memory Interface Program Memory Opcode Immediate Registers Multiplier Divider Register Interface
clocks machine cycle Software compatible with Intel 8051,
8031, 80C51, 80C31 87C51
bytes external Data
Opcode Decoder
Port Registers
Port Port Port Port
Clocks Memory Wait Reset
State Machine Power Saving
Timer Counters
Memory; bytes Internal Data Memory; bytes Program Memory Optional multiplexed Program External Data interface Support synchronous asynchronous Program, External Data Internal Data Memory Wait states support slow Program External Data Memory
16-bit timer/counters Full-duplex serial port Intel-compatible ports 14-source, 2-level interrupt controller Power-saving modes Support user-defined SFRs
External Interrupts
Interrupt Controller
Serial Interface
M8051 Warp Block Diagram
Overview
M8051Warp-A1 implementation InventraM8051 Warp soft core netlist Actel SX-A family FPGAs. M8051Warp exceptionally high performance version popular 8051 8-bit microcontroller, requiring just clocks machine cycle rather than clocks cycle industry standard device while keeping functional compatibility with standard part. This allows M8051Warp times faster than standard part same power consumption have sixth power consumption when standard speed. microcode-free design software compatible with industry standard discrete devices, having their core features, well additional features corresponding Intel 8051/8031/80C51BH/80C31BH/87C51 parts. M8051Warp intended high-speed low-power single-chip solutions where conventional clocks cycle would either limit performance impose unacceptable demands power supply. Wait state support provided slow memory devices. M8051Warp-A1 deliverables comprise EDIF VHDL netlists, together with appropriate Actel-specific .adb file supporting documentation.
FPGA Implementation:
Actel SX-A Family, 0.25µm
CMOS Process
unidirectional ports Utilization: 73.7%
A54SX32A FPGA modules 1666 modules
Post Layout Performance 40MHz
FPGA Deliverables:
EDIF netlists, with without VHDL netlist (without I/O) Actel-specific database file Core specification Methodology guide Readme/help file
www.mentor.com/inventra
InventraM8051Warp-A1 FPGA
M8051 Warp Features
This represents most
Core Signals
PROCESSOR INPUTS SIGNAL SCLK CCLK PCLK PORT0n[7:0] MWAIT RESET TRESET TYPE Input Input Input Input Input Input Input DESCRIPTION State Machine Clock Input. stopped during power-down. Clock Input. stopped during powerdown idle mode. Peripheral Clock Input. stopped during power-down. Port Input Data bits Memory Wait. Used stall instruction execution Restart processor reset SFRs. Compatible with discrete part input. Test Mode Reset. Clears state machine registers test simulation. PROCESSOR OUTPUTS PORTnO[7:0] NPORTnE[7:0] IDLE PDOWN NCCLKE NPCLKE Output Port Output Data bits Output Bi-directional control (drive enable) bits Port (active output drive). Output Idle Mode Indicator. Output Power-Down Mode Indicator. Output CCLK qualifier Output PCLK qualifier MEMORY REGISTER INTERFACE SIGNALS PROGA[15:0] PROGA_EN NPSEN PROGDI[7:0] XRAMA[15:0] XRAMA_EN NXRAMR NXRAMW XRAMDI[7:0] XRAMDO[7:0] SOURCE_A[7:0] SOURCE_DI[7:0] NSOURCE_RE DESTIN_A[7:0] DESTIN_DO[7:0] NDESTIN_WE SFRSA[6:0] SFRWE ESFRDI[7:0] XINTR_SRC[13:5] XINTR_ACK[13:5] Output Program Memory Address bits Output Program Memory Address Enable. Output Program Memory Enable, active low. Input Program Memory Data bits
important feature M8051Warp design, allowing device either times speed same power consumption sixth power when running standard speed. instructions have zero-wait-state execution times that exactly sixth those standard part.
Support provided separate interrupt sources. AVING M8051Warp power-
saving modes: Power Down mode Idle mode. Power Down mode, clock entire M8051Warp stopped. Idle mode, clock stopped timer/counters serial port still active. peripheral clock driving interrupt controller, timer/counters serial interface half frequency core (CPU) clock i.e. once machine cycle, giving further power savings over standard 12-state part.
ERIAL TIMER OUNTERS: inclusion serial
port timer/counters within M8051Warp simplifies system design required range possible applications. serial port full duplex. also receive buffered.
M8051Warp
address bytes Program bytes internal Data Memory (implemented dual-port target technology). M8051Warp also address bytes external Data RAM. This external Data memory accessed through either program memory interface dedicated memory rather than ports. port pins therefore used exclusively peripheral I/O. Slow external data program memory assert memory wait signal stall activity, whilst leaving peripheral functions unaffected. Each program data memory interface configured support either asynchronous synchronous memory devices.
USER
Output External Data Memory Address bits Output External Data Memory Address Enable. Output External Data Memory Read Strobe, active low. Output External Data Memory Write Strobe, active low. Input External Data Memory Input Data bits
Output External Data Memory Output Data bits Output IRAM Source Port Address bits Input IRAM Source Port Data bits
Output IRAM Source Port Read Enable, active Output IRAM Destination Port Address bits Output IRAM Destination Port Data bits Output IRAM Destination Port Write Strobe, active low. Output External Read Address bits Output External Write Enable. Input Input External Input Data bits External Interrupt Source bits
`External' special function registers (ESFRs) added M8051Warp core, three which bitaddressable. ESFRs memory mapped into Direct Memory between addresses same manner core SFRs occupy most addresses occupied core SFR.
Output External Interrupt Acknowledge bits
Mentor Graphics Inventra trademarks Mentor Graphics Corporation. other trademarks property their respective owners.
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PD-40118.001-FO

M8051 Warp Internal Data Memory External SFRs Microcontrolle

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