TOSHIBA RISC PROCESSOR TMPR4927ATB-200 TOSHIBA RISC PROCESSO

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TOSHIBA RISC PROCESSOR TMPR4927ATB-200 TOSHIBA RISC PROCESSO

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INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
(64-bit RISC MICROPROCESSOR) GENERAL DESCRIPTION TMPR4927ATB, referred TX4927 MIPS RISC micro-controller highly integrated ASSP solution based Toshiba's TX49/H2 processor core, 64-bit MIPS I,II,III Instruction Architecture (ISA) compatible with additional instructions. TX4927 highly integrated device with integrated peripherals such SDRAM memory controller, controller, PIO, AC-Link, UART Timer. This class product targeted applications that require high performance cost-effective solution such networking printers.
FEATURES
TX49/H2 core with integrated IEEE 754-compliant single- double-precision operations 4-channel SDRAM Controller 64-bit 100MHz 8-channel External Controller 32-bit Controller 32-bit 4-channel Direct Memory Access Controller 2-channel Serial Port Parallel Port 16-bit) 3-channel Timer Counter AC-Link AC97 Interface power dissipation Typ. TX4927 operates with 1.5V Int. 3.3V I/O, while supporting low-power Halt mode. maximum operating frequency: IEEE1149.1 (JTAG) support: Debug Support Unit Enhanced JTAG 420-pin TBGA
information contained herein subject change without notice. continually working improve quality reliability products.
Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, observe standards safety, avoid situations which malfunction failure TOSHIBA product could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent products specifications. Also, please keep mind precautions conditions forth TOSHIBA Semiconductor Reliability Handbook information contained herein presented only guide applications products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights TOSHIBA others.
EJC-TMPR4927ATB-1 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Internal Block Diagram Figure shows TX4927 internal block diagram.
Clock Generator Debug (DSU)
D$(32K
SDRAMC
64bit Gbus
I$(32K)
DMAC External Controller External Interface PCIC
TX49/H2 Core
bridge
ACLC
UART
Timer
Figure TX4927 Internal Block Diagram
EJC-TMPR4927ATB-2 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
System Block Diagram Figure shows system block diagram with TX4927.
64bit Gbus SDRAMC DMAC External Controller External Interface PCIC
Debug (DSU) D$(32K) I$(32K)
SDRAM Control signals
SDRAM Memory Devices
External System Data 64bit, Address 20bit
TX49/H2 Core
Control Signals
bridge
ROM/ Flash/ SRAM
Ext. Dev.
ACLC
UART
Timer
Devices
User logic PCIC
Figure Typical TX4927 System Block Diagram
EJC-TMPR4927ATB-3 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
TX49/H2 Core Block Diagram Figure shows internal block diagram TX49/H2 core
TX49/H2 Core
Integer Unit
Data Path Pipeline Control
Registers MMU/TLB Exception Unit
Debug Support Unit
32KB 4-way Instruction Cache
Write Buffer
32KB 4-way Data Cache
Figure TX49/H2 Core Block Diagram
TX49/H2 CORE FEATURES TX49/H2 Core high performance low-power 64-bit RISC processor core developed Toshiba. 64-bit operation 64-bit integer general purpose registers 32-bit physical address space 64-bit virtual address space Optimized 5-stage pipeline Instruction MIPS compatible PREF (Prefetch) (Multiply/Accumulate) instructions. Byte Instruction Cache, Byte Data Cache 4-way associative with lock function (Memory Management Unit): 48-entry fully associative JTLB on-chip supports both single- double-precision arithmetic, specified IEEE 754. On-chip 4-deep write buffer Enhanced JTAG debug feature Built-in Debug Support Unit (DSU)
EJC-TMPR4927ATB-4 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
TX4927 Peripheral Circuit FEATURES External Controller EBUSC External Controller generates necessary signals control external memory devices. channels chip select signals, enabling control eight devices Supports access including mask ROM, page mode ROM, EPROM EEPROM), SRAM, flash ROM, devices Supports 32-bit, 16-bit 8-bit data sizing channel basis Supports selection among full speed 100MHz speed 50MHz), speed 33MHz speed 25MHz) channel basis Support specification timing channel basis user specify setup hold times address, chip enable, write enable, output enable signals Supports memory sizes byte byte devices with 32-bit data bus, byte 512M bytes devices with 16-bit data bus, byte 256M bytes devices with 8-bit data
Controller DMAC TX4927 contains 4-channel controller that executes transfer memory devices. 4-channel independently handling internal external requests Supports transfer with built-in serial controller AC-link controller based internal requests Supports signal address fly-by dual address transfers external transfer mode using external requests Supports transfer between memory external devices having 8-bit data Supports memory-to-memory copy mode, with address boundary restrictions Supports burst transfer double words single read write Supports memory fill mode, writing double-word data specified memory area Supports chained transfer
EJC-TMPR4927ATB-5 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
SDRAM Controller SDRAMC SDRAM Controller generates necessary control signals SDRAM interface. four channels handle bytes MB/channel memory supporting variety memory configurations. Memory clock frequency 100MHz sets independent memory channels Supports 128M 256M-bit SDRAM with bank size availability Supports Registered DIMM Supports parity generation check functions Supports 32-bit data sizing channel basis Supports specification SDRAM timing channel basis Supports critical word first access TX49/H2 core power mode selectable between self-refreshing pre-charge power-down
Controller PCIC TX4927 contains Controller that complies with Local Specification Revision 2.2. Compliance with Local Specification Revision 32-bit interface featuring maximum clock frequency 66MHz Supports both target initiator functions Supports change address mapping between internal arbiter enables connection external masters Supports booting TX4927 from memory channel controller dedicated controller PDMAC
Serial Controller UART TX4927 contains 2-channels asynchronous serial interface full duplex UART 2-channel full duplex UART Built-in baud rate generator FIFOs 8-bit transmitter FIFO 13-bit data bits status bits receiver FIFO Supports tranfer
EJC-TMPR4927ATB-6 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Timers Counters Controller TX4927 contains 3-channel timer counters. 3-channel 32-bit up-counter Supports three modes interval timer mode, pulse generator mode, watchdog timer mode timer output pins count clock input external watchdog reset signal
Parallel Ports TX4927 contains 16-bit parallel ports including bits shared with Independent selection direction pins output port type totem-pole open-drain outputs basis.
AC-link controller ACLC TX4927 contains AC-link controller, which operated using audio modem CODECs described Audio CODEC'97 Revision AC'97 Supports CODECs Supports recording playback right left 16-bit channels Supports playback 16-bit surround, center, channels Supports audio recording layback variable rate Supports Line1 GPIO slots modem CODEC Supports AC-link power mode, wakeup, warm reset Supports input output sample data transfer
EJC-TMPR4927ATB-7 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Interrupt Controller TX4927 contains interrupt controller, which receives interrupt requests sent both TX4927's built-in peripherals external devices issues interrupt requests TX49/H2 core. 16-bit flag register generate interrupt requests external devices TX49/H2 core. Supports internal interrupt sources from built-in peripherals external interrupt signal inputs interrupt priority levels each interrupt source Supports selection between edge- level-triggered interrupt detection each external interrupt 16-bit read write flag register interrupt requests, making possible issue interrupt request external devices TX49/H2 core interrupts
Extended EJTAG Interface TX4927 contains Extended Enhanced Joint Test Action Group Extended EJTAG interface, which provides functions JTAG boundary scan test that complies with IEEE1149.1 real-time debugging using debug support unit built into TX49/H2 core. IEEE 1149.1 JTAG Boundary Scan Real-time debugging functions using special emulation probe execution control execution, break, step, register memory access trace
EJC-TMPR4927ATB-8 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Pins
designations
PIO[1] PIO[0] SWE* CE[7]* CE[5]* CE[4]* DMAACK[2] DMAACK[1] BWE[0]* BWE[1]* EEPROM_DI EEPROM_DO EEPROM_SK EEPROM_CS PCST[3] PCST[0] PCIAD[2] PCIAD[5] C_BE[0] PCIAD[11] PCIAD[15] VddIO IRDY* C_BE[2] PIO[3] PIO[2] BUSSPRT* CE[6]* VddIO CE[3]* DMAACK[3] DMAREQ[2] DMAREQ[1] BWE[2]* DCLK PCST[8] PCST[5] PCST[2] PCIAD[0] PCIAD[3] PCIAD[6] PCIAD[8] PCIAD[12] C_BE[1] PERR* STOP* FRAME* PIO[5] PIO[4] VddIO ACK* ACE* CE[2]* CE[1]* DMAREQ[3] VddIO BWE[3]* TPC[3] PCST[7] PCST[4] PCST[1] PCIAD[1] VddIO PCIAD[7] PCIAD[9] PCIAD[13] LOCK* DEVSEL* PCIAD[17] PCIAD[16] PIO[7] PIO[6] VddIN
BYPASSPLL*
CE[0]* VddIN VddIN DMAACK[0] VddIO TPC[2] VddIO VddIN VddIO VddIN PCIAD[4] VddIO M66EN VddIO SERR* VddIN TRDY* VddIO PCIAD[18] TCLK TIMER[0] TIMER[1] VddIO
SDIN[1]
VddIO DMADONE* DMAREQ[0] TPC[1] PCST[6] TRST* PCIAD[10] PCIAD[14]
PCIAD[22] PCIAD[21] PCIAD[20] PCIAD[19] INT[2] INT[1] INT[0] NMI* VddIN VddIO C_BE[3] ID_SEL VddIO PCIAD[23] INT[5] INT[4] INT[3] RXD[0] VddIN PCIAD[28] PCIAD[27] PCIAD[26] PCIAD[25] PCIAD[24] TXD[0] RTS[0]* CTS[0]* VddIO VddIN PCIAD[29] VddIO PCICLK[0] SCLK TXD[1] RTS[1]* CTS[1]* RXD[1] PCIAD[31] PCIAD[30]
GNT[0]* PCICLK[1] RESET* TEST[0]* HALTDOZE VddIN VddIN GNT[1]* REQ[0]* PCICLK[2] SYSCLK TEST[4]* TEST[3]* TEST[2]* TEST[1]* REQ[1]* REQ[2]* GNT[2]* PCICLK[3] WDRST* VddIO VddIN VddIO REQ[3]* GNT[3]* PCICLK[4] DATA[1] DATA[32] DATA[0] VddIO PME* VddIO DATA[63] PCICLK[5]
EJC-TMPR4927ATB-9 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
DATA[2] DATA[33] VddIO VddIN CGRESET* PLL2Vcc_A PLL2Vss_A PCICLKIN DATA[35] DATA[3] DATA[34] VddIO VddIN PLL1Vcc_A PLL1Vss_A MASTERCLK DATA[5] DATA[36] VddIO DATA[4] DATA[30] DATA[62] VddIO DATA[31] DATA[38] DATA[6] DATA[37] VddIN VddIN VddIO DATA[61]
AA22 AA23 AA24 AA25 AA26
VddIO VddIO DATA[7] VddIO DATA[28] DATA[60] DATA[29] DATA[8] DATA[39] VddIN VddIO DATA[27] DATA[59] DATA[10] DATA[41] DATA[9] DATA[40] VddIO DATA[25] DATA[57] DATA[26] DATA[58] DATA[43] DATA[11] VddIO DATA[42] DATA[23] DATA[55] DATA[24] DATA[56] DATA[45] DATA[13] DATA[44] DATA[12]
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20
DQM[0] VddIO ADDR[3] ADDR[7] ADDR[17] SDCS[3]* DQM[7] CB[3] VddIO DATA[54] DATA[14] VddIN VddIO SDCS[0]* VddIO VddIO VddIN ADDR[8] VddIN VddIO VddIO VddIO VddIO VddIN DQM[2] VddIN CB[2]
AC21 AC22 AC23 AC24 AC25 AC26 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE10
DATA[48] VddIN DATA[53] DATA[22] VddIO DATA[46] CB[0] DQM[4] SDCS[1]* ADDR[5] ADDR[10] ADDR[12] ADDR[14] ADDR[15] ADDR[18] DQM[6] CB[7] DATA[17] DATA[50] DATA[52] DATA[21] DATA[15] VddIO CB[4] CB[5] DQM[1] RAS* ADDR[1] ADDR[4] ADDR[6]
AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
ADDR[9] ADDR[13] ADDR[16] ADDR[19] SDCS[2]* DQM[3] CB[6] VddIO DATA[49] VddIO DATA[20] VddIO DATA[47] CB[1] CAS* DQM[5] ADDR[0] ADDR[2] VddIO VddIO ADDR[11] SDCLK[2] SDCLK[0] SDCLKIN SDCLK[3] SDCLK[1] VddIO DATA[16] DATA[18] VddIO DATA[19] DATA[51]
EJC-TMPR4927ATB-10 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
layout
EJC-TMPR4927ATB-11 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
AA26 AA25 AA24 AA23 AA22
AB26 AB25 AB24 AB23 AB22 AB21 AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10
AC26 AC25 AC24 AC23 AC22 AC21 AC20 AC19 AC18 AC17 AC16 AC15 AC14 AC13 AC12 AC11 AC10
AF26 AF25 AF24 AF23 AF22 AF21 AF20 AF19 AF18 AF17 AF16 AF15 AF14 AF13 AF12 AF11 AF10
AD26 AE26 AD25 AE25 AD24 AE24 AD23 AE23 AD22 AE22 AD21 AE21 AD20 AE20 AD19 AE19 AD18 AE18 AD17 AE17 AD16 AE16 AD15 AE15 AD14 AE14 AD13 AE13 AD12 AE12 AD11 AE11 AD10 AE10
EJC-TMPR4927ATB-12 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Description
Note: columns, "PU" indicates with pull-up resistor, term "OD" indicates open drain output. denotes active-low signal when used suffix signal name.
Signal Name
Type
Function
SDRAM External Interface Common Signals
ADDR[19:0]
Addresses Address signals. SDRAM, ADDR[19:5] used When external controller uses these pins, meaning each varies with data width. ADDR signals also used boot configuration signals (input) during reset. ADDR signals input signals only when RESET* signal asserted become output signals after RESET* signal deasserted.
DATA[63:0]
Data 64-bit data bus. DATA[15:0] signals also used boot configuration signals (input) during reset.
BUSSPRT*
Separate Controls connection separation devices controlled external controller from high-speed device, such SDRAM. Separate devices other than SDRAM from data bus. Connect devices other than SDRAM data bus. Separation connection performed using external bi-directional buffers (such 74xx245).
EJC-TMPR4927ATB-13 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Function
SDRAM Interface Signals
SDCLK[3:0]
SDRAM Controller Clock Clock signals used SDRAM. clock frequency same G-Bus clock (GBUSCLK) frequency. When these clock signals used, pins using SDCLK Enable field configuration register (CCFG.SDCLKEN[3:0]).
SDCLKIN
SDRAM feedback clock input Feedback clock signal SDRAM controller input signals. Setting SDCLKINEN configuration register causes TX4927 feed back signals internally, making SDCLKIN output signal.
Clock Enable signal SDRAM.
SDCS[3:0]*
Synchronous Memory Device Chip Select Chip select signals SDRAM.
RAS*
Address Strobe signal SDRAM.
CAS*
Column Address Strobe signal SDRAM.
Write Enable signal SDRAM.
EJC-TMPR4927ATB-14 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
DQM[7:0]
Type
Data Mask
Function
During read cycle, they control SDRAM output buffers. bits correspond following data signals: DMQ[7] DATA[63:54], DMQ[6] DATA[53:48] DMQ[5] DATA[47:40], DMQ[4] DATA[39:32] DMQ[3] DATA[31:24], DMQ[2] DATA[23:16] DMQ[1] DATA[15:8], CB[7:0] DMQ[0] DATA[7:0]
control Data parity ECC/parity check signals. bits correspond following data signals:. CB[7] DATA[63:54], CB[6] DATA[53:48] CB[5] DATA[47:40], CB[4] DATA[39:32] CB[3] DATA[31:24], CB[2] DATA[23:16] CB[1] DATA[15:8], CB[0] DATA[7:0] CB[7:0] share pins with PIO[15:8] signals parallel I/O. boot configuration signal ADDR[18] selects between PIO[15:8] CB[7:0].
EJC-TMPR4927ATB-15 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Function
External Interface Signals
SYSCLK
System Clock Clock external devices. Outputs clock full speed mode same frequency G-Bus clock (GBUSCLK) frequency), half speed mode half GBUSCLK frequency), third speed mode third GBUSCLK frequency), quarter speed mode quarter GBUSCLK frequency). boot configuration signals ADDR[14:13] pins select which speed mode will used. When this clock signal used, using SYSCLK Enable configuration register (CCFG.SYSCLKEN). Address Clock Enable Latch enable signal high-order address bits ADDR. Chip Enable Chip select signals ROM, SRAM, devices. Output Enable Output enable signal ROM, SRAM, devices. Static Write Enable Write enable signal SRAM devices. Byte Write Enable Byte Enable BE[3:0]* indicate valid data position data DATA[31:0] both read write operation. 16-bit mode, BE[1:0]* only used. 8-bit mode, BE[0]* only used. BWE[3:0]* indicate valid data position data DATA[31:0] write operation. 16-bit mode, BWE[1:0]* only used. 8-bit mode, BWE[0]* only used. following shows correspondence between BE[3:0]*/BWE[3:0]* data bus. BE[3]* BWE[3]* DATA[31:24] BE[1]* BWE[1]* DATA[15:8] BE[2]* BWE[2]* DATA[23:16] BE[0]* BWE[0]* DATA[7:0] function these signals selected from BE[3:0]* BWE[3:0]* using DATA[5] signal EBCCRn registers External Controller during boot-mode configuration. Acknowledge Flow control signal.
ACE* [7:0]* SWE* BWE[3:0]* BE[3:0]*
ACK* READY
EJC-TMPR4927ATB-16 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name Interface
DMAREQ[3:0]
Type
Function
Request transfer request signals from external device. DMAREQ[2] signal shares with ACRESET* signal. boot configuration signal ADDR[9] selects between DMAREQ[2] ACRESET*.
DMAACK[3:0]
Acknowledge transfer acknowledge signals external device. DMAACK[2] signal shares with SYNC signal. boot configuration signal ADDR[9] selects between DMAACK[2] SYNC.
DMADONE*
Transfer/Chain Finished DMADONE* either used output signal that reports termination transfer input signal that causes transfer terminate.
Interface PCICLK[5:0]
Clock clock signals. When these clock signals used, pins using PCICLK Enable field configuration register (PCFG.PCICLKEN[5:0]).
PCICLKIN
feedback clock input feedback clock input.
PCIAD[31:0]
Address Data Multiplexed address data bus.
C_BE[3:0]
Command Byte Enable Command byte enable signals.
EJC-TMPR4927ATB-17 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Parity
Function
Even parity signal PCIAD[31:0] C_BE[3:0]*. FRAME*
Cycle Indicates that operation progress.
IRDY*
Initiator ready Indicates that initiator ready complete data transfer.
TRDY*
Target ready Indicates that initiator ready complete data transfer.
STOP*
STOP target sends this signal initiator request termination data transfer.
LOCK*
resource clock Indicates that master locking (exclusively accessing) specified memory target bus.
ID_SEL
Initialization Device select Chip select signal used configuration access.
DEVSEL*
Device select target asserts this signal response access from initiator.
REQ[3:2]*
Request Signals used master request mastership. boot configuration signal DATA[2] determines whether built-in arbiter used. internal arbiter mode, REQ[3:2]* request input signals. external arbiter mode, REQ[3:2]* used. Because pins still placed input state, they must pulled externally.
EJC-TMPR4927ATB-18 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
REQ[1]* INOUT
Type
Request
Function
Signal used master request mastership. boot configuration signal DATA[2] determines whether built-in arbiter used. internal arbiter mode, this signal request input signal. external arbiter mode, this signal external interrupt output signal (INTOUT). Request Signal used master request mastership. boot configuration signal DATA[2] determines whether built-in arbiter used. internal arbiter mode, this signal request input signal. external arbiter mode, this signal request output signal.
REQ[0]*
GNT[3:0]*
Grant Indicates that mastership been granted master. boot configuration signal DATA[2] determines whether built-in arbiter used. internal arbiter mode, GNT[3:0]* grant output signals. external arbiter mode, GNT[0]* grant input signal. Because GNT[3:1]* also become input signals, they must pulled externally.
PERR*
Data Parity Error Indicates data parity error cycle other than special cycles.
SERR*
I/OD
System Error Indicates address parity error, data parity error special cycle, fatal error. host mode, SERR* input signal. satellite mode, SERR* open-drain output signal. mode determined boot configuration signal ADDR[19] pin.
EJC-TMPR4927ATB-19 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
M66EN
Type
66MHz clock enable
Function
Enable operating mode. Disable operating mode. host mode, M66EN input signal. satellite mode, M66EN output signal. mode determined boot configuration signal ADDR[19] pin. PME*
Power management event PME* indicates power management mode. host mode, PME* input signal. satellite mode, PME* open-drain output signal. mode determined boot configuration signal ADDR[19] pin. EEPROM data This data input signal from serial EEPROM configuration. EEPROM data This data output signal serial EEPROM configuration.
EEPROM_DI
EEPROM_DO
EEPROM_CS
EEPROM chip select This chip select signal serial EEPROM configuration.
EEPROM_SK
EEPROM This clock signal serial EEPROM configuration.
Timer Interface
TIMER[1:0]
Timer Pulse Width Output Timer output signal.
TCLK
External Timer Clock Timer input clock. TMR0, TMR1 TMR2 share this signal. Watchdog Reset Watchdog reset output signal.
WDRST*
EJC-TMPR4927ATB-20 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name Interface
CTS[1:0]*
Type
Function
Clear Send signals. Request Send signals.
RTS[1:0]*
RXD[1:0]
Receive Data Serial data input signal. Transmit Data Serial data output signal. External Serial Clock Input clock SIO0 SIO1. SIO0 SIO1 share this signal.
TXD[1:0]
3state
SCLK
Interface
PIO[15:8]
Ports Parallel signals. PIO[15:8] share pins with SDRAM ECC/parity signals (CB[7:0]). boot configuration signal ADDR[18] selects between PIO[15:8] CB[7:0]. Ports Parallel signals. PIO[4:2] share pins with AC-link interface signals (SDOUT, SDIN[0], BITCLK). boot configuration signal ADDR[9] selects between PIO[4:2] AC-link interface signals.
PIO[7:0]
EJC-TMPR4927ATB-21 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Function
AC-Link Interface
ACRESET*
Master Reset ACRESET* shares with DMAREQ[2] signal. boot configuration signal ADDR[9] selects between ACRESET* DMAREQ[2].PIO[15:8] CB[7:0].
SYNC
Fixed Rate Sample Sync SYNC shares with DMAACK[2] signal. boot configuration signal ADDR[9] selects between SYNC DMAACK[2].
SDOUT
Serial, Time Division Multiplexed, Output Stream SDOUT shares with PIO[4] signal. boot configuration signal ADDR[9] selects between SDOUT PIO[4].
SDIN[1]
Serial, Time Division Multiplexed, Input Stream
SDIN[0]
Serial, Time Division Multiplexed, Input Stream SDIN[0] shares with PIO[3] signal. boot configuration signal ADDR[9] selects between SDIN[0] PIO[3].
BITCLK
Serial, Time Division Multiplexed, Input Stream BITCLK shares with PIO[2] signal. boot configuration signal ADDR[9] selects between BITCLK PIO[2].
Interrupt Signals NMI*
Mask-able Interrupt Non-Mask-able interrupt input. External Interrupt Requests external interrupt request signals.
INT[5:0]
EJC-TMPR4927ATB-22 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Function
EJTAG Debug Interface
JTAG clock input Clock input signal JTAG. used execute JTAG instructions input/output data. JTAG data input Debug interrupt input When trace mode selected, this signal JTAG data input signal. used input serial data JTAG data/instruction registers. When trace mode selected, this signal interrupt input signal used cancel trace mode debug unit. JTAG data outpur Trace output When trace mode selected, this signal JTAG data output signal. Data output means serial scan. When trace mode selected, this signal outputs value noncontiguous program counter sync with debug clock (DCLK).
DINT*
TPC[0]
TPC[3:1]
Trace Output TPC[3:1] output value noncontiguous program counter sync with DCLK.
JTAG command mainly controls state transition controller state machine. Test Reset Input Asynchronous reset input controller debug support unit. When EJTAG probe connected, this must fixed low. When connecting EJTAG probe, prevent floating, example, connecting pull-up resistor. When this signal de-asserted, G-Bus timeout detection disabled.
TRST*
DCLK
Debug Clock clock output real-time debug system. timing serial monitor trace interface signal defined this debug clock DCLK. divide operation clock TMPR4927TB time serial monitor operation.
EJC-TMPR4927ATB-23 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
PCST[8:0]
Type
Trace Status
Function
Output trace status information mode serial monitor bus.
Clock Signals
MASTERCLK
Master Clock Input Input TX4927 operating clock. crystal resonator cannot connected this because does contain oscillator.
HALTDOZE
Halt/Doze state output This signal asserted (High output) when TX4927 enters Halt Doze mode.
BYPASSPLL*
Reset This must fixed High.
CGRESET*
Reset CGRESET* initializes
Reset signals
RESET*
Reset Reset signal.
Test signals
TEST[4:0]*
Test mode Enable Test pins. These pins must left open fixed High.
EJC-TMPR4927ATB-24 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Signal Name
Type
Function
Power pins Total count
PLL1Vdd_A, PLL2Vdd_A, PLL1Vss_A, PLL2Vss_A VddIN
Power Ground pins internal circuit. PLL1Vcc_A PLL2Vcc_A 1.5V, PLL1_Vss_A PLL2_Vss_A
Internal Power Pins Power pins 1.5V
VddIO
Power Pins Power pins 3.3V
Ground Digital ground pins.
EJC-TMPR4927ATB-25 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Multiplexing
total pins TX4927 have multiplexed functions. Table shows multiplexed pins. function given selected various ways, depending pin(s) involved. Table Table show setting booting TX4927.
Table Multiplexing Signal name CB[7:0] DMAREQ[2] DMAACK[2] PIO[4:2] Multiplexed Function CB[7:0] PIO[15:8] DMAREQ[2] ACRESET* DMAACK[2] SYNC PIO[4:2] SDOUT, SDIN[0], BITCLK
Table Setting ADDR[18] Signal name CB[7:0] ADDR[18]=0 (Non ECC) PIO[15:8] ADDR[18]=1 (ECC) CB[7:0]
Table Setting ADDR[9] Signal name DMAREQ[2] DMAACK[2] PIO[4] PIO[3] PIO[2] ADDR[9]=1 (ACLC) ACRESET* SYNC SDOUT SDIN[0] BITCLK ADDR[9]=0 (Non ACLC) DMAREQ[2] DMAACK[2] PIO[4] PIO[3] PIO[2]
EJC-TMPR4927ATB-26 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATING (*1)
PARAMETER Supply voltage (for I/O) Supply voltage (for internal) Input voltage (*2) Storage Temperature Power SYMBOL
VddIOMax
RATING -0.3 -0.3 -0.3 VddIO 0.3V +125 (Typ.)
UNIT
VCCIntMax TSTG
Note) (*1) used above maximum ratings, permanent destruction result. addition, desirable normal operation under recommended condition. these conditions exceeded, reliability adversely affected. (*2) maximum rated ddIOMax voltage must exceeded even ddIO volts.
RECOMMENDED OPERATING CONDITIONS (*3)
PARAMETER Supply Voltage Internal Operating Case Temperature
(*3)
SYMBOL VddIO VddIN
CONDITION
MIN.
MAX.
UNIT
Functional operation should restricted recommended operating conditions. Those limits under which proper device operation guaranteed. Therefore, product must designed within recommended voltage temperature ranges indicated.
EJC-TMPR4927ATB-27 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
CHARACTERISTICS Characteristics except interface
70°C, VddIO 3.3V ±0.2V, VddIN 1.5V 0.1V, PARAMETER Low-level input voltage High-level input voltage Low-level output current Low-level output current High-level output current High-level output current Low-level input leakage current High-level input leakage current Hi-z output leakage current Operating current (for internal)
VIL1 VIH1 IOL1 IOL2 IOL3 IOL4 IOH1 IOH2 IOH3 IOH4 IIL1 IIL2 IIH1 IIH2 ICCInt
CONDITIONS
(*1) (*1) (*2) =0.4V (*3) =0.4V (*4) =0.4V (*5) =0.4V (*2) =2.4V (*3) =2.4V (*4) =2.4V (*5) =2.4V (*6) =VSS (*7) =VSS (*8) =VCCIO (*9) =VCCIO (*10) VddIO 3.3V, VddIN 1.6V, MASTERCLK=100MHz PClock 200MHz
MIN.
-0.3 -200
MAX.
VddIO+0.3
UNIT
Operating current (for I/O)
ICCIO
VddIO 3.5V, VddIN 1.5V, MASTERCLK=100MHz PClock 200MHz Load=25pF
(*1) input input-mode bidirectional pins except interface signals (*2) ACE*, ACK*, BUSSPRT*, BWE[3:0]*, CE[7:0]*, DMAACK[3:0], DMADONE*, EEPROM_CS, EEPROM_DO, EEPROM_SK, HALTDOZE, PIO[7:0], RTS[1:0], SWE*, SYSCLK, TIMER[1:0], TXD[1:0] (*3) DCLK, PCST[8:0], TDO, TPC[3:1] (*4) Applies ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]* when output buffer drive strength used. (*5) Drive 8mA: ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]*, (*6) EEPROM_DI, CGRESET*, RESET*, TRST*, BYPASSPLL*, MASTERCLK, DMADONE*, PIO[7:0], SDCLKIN (*7) CTS[1:0]*, DMAREQ[3:0], RXD[1:0], SCLK, TCLK, INT[5:0], TCK, TDI, TEST[4:0]*, TMS, ACK*, CB[7:0], DATA[63:0], ADDR[19:0], NMI* (*8) (*6), (*7) Signals except TRST* (*9) TRST* (*10) TXD[1:0]
EJC-TMPR4927ATB-28 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Characteristics except interface
70°C, VddIO 3.3V ±0.2V, VddIN 1.5V 0.1V, PARAMETER Low-level input voltage High-level input voltage High-level output voltage Low-level output voltage Input leakage current Hi-z output leakage current
VILPCI VIHPCI VOHPCI VOLPCI IIHPCI IILPCI IOZPCI
CONDITIONS
(*1) (*1) (*2) IOUT -500uA (*2) IOUT 1500uA VddIO (*3)
MIN.
-0.5 VddIO
MAX.
VddIO+0.3 VddIO
UNIT
(*1) ID_SEL, PCICLKIN, C_BE[3:0], DEVSEL*, FRAME*, GNT[3:0]*, IRDY*, LOCK*, M66EN, PAR, PCIAD[31:0], PERR*, REQ[3:0], SERR*, STOP*, TRDY* (*2) ID_SEL, PCICLKIN (*3) PCICLK[5:0], PME*
Power circuit Recommended circuit
TX4927
VddIN VddIN
PLL2Vdd_A PLL1Vdd_A
PLL2Vss_A PLL1Vss_A
Note) should placed closed processor possible.
PARAMETER Resistor Inductance Capacitor SYMBOL reference Value T.B.D. 1.5V 0.1V UNIT
VddIN, PLL1Vdd_A, PLL2Vdd_A
EJC-TMPR4927ATB-29 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
CHARACTERISTICS MASTERCLK Characteristics
70°C, VddIO 3.3V 0.2V, VddIN 1.5V 0.1V, PARAMETER MASTERCLK Period MASTERCLK Frequency (*1) MASTERCLK High MASTERCLK Internal Operating Frequency MASTERCLK Rise Time MASTERCLK Fall Time
tMCP fMCK tMCH tMCL fcpu tMCR tMCF
CONDITION
ADDR[2]=H boot time ADDR[2]=H boot time
MIN.
12.5
MAX.
UNIT
(*1) Proper circuit operation TX4927 guaranteed only when power supply stable on-chip enabled.
tMCP
tMCL
tMCH
MASTERCLK
VddIO VddIO
tMCR Power Characteristics
tMCF
70°C, VddIO 3.3V 0.2V, VddIN 1.5V 0.1V, PARAMETER stable time CGRESET* width time RESET* width time
tMCP_PLL tMCK_PLL tMCH_PLL
CONDITION
MIN.
MAX.
UNIT
VddIN, VddIO,
PLL1Vdd_A, PLL2Vdd_A MASTERCLK stable time
MASTERCLK
MCP_PLL CGRESET
MCK_PLL tMCH_PLL
RESET
EJC-TMPR4927ATB-30 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
SDRAM Interface Characteristics
70°C, VddIO 3.3V 0.2V, VddIN 1.5V 0.1V, Signal Name
SDCLK[3:0]
Load
(pF)
Buffer Type
16mA
Tcyc_sdclk Thigh_sdclk Tlow_sdclk Tval_addr1 Tval_sdcs Tval_ras Tval_cas Tval_we Tval_cke Tval_dqm Tval_data1 Tval_data1v Tval_data1z Tsu_data1b Th_data1b Tsu_data1n Th_data1nb
Descriptions
Clock Cycle Time Clock High Time Clock Time Clock Input Timing bypass mode Address Output Delay (*1) Output Delay Chip Select Output Delay RAS* (*1) Output Delay CAS* Cycle Operation) Output Delay Write Enable Cycle Operation) Output Delay Clock Enable Output Delay Data Mask (*1) Output Delay Data (High <->low) (*1) Output Delay Data (Hi-Z valid) Output Delay Data (valid->Hi-Z) Data Setup Time (Bypass mode) Data Hold Time (Bypass mode) Data Setup Time (Non bypass mode) Data Hold Time (Non bypass mode)
(ns)
(ns)
SDCLKIN ADDR[19:5] SDCS[3:0]* RAS* CAS* DQM[7:0] DATA[63:0]
16mA 16mA 16mA 16mA 16mA 16mA 16mA 16mA
(*1) SDRAM transaction complete more than clock cycles through programming SDRAMC Configuration registers.
EJC-TMPR4927ATB-31 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
SDCLK Tval_* OUTPUT Tsu_* INPUT inputs valid Th_*
outputs valid
Output Signals when bypass mode input Signals (SDCLK basis)
SDCLK
SDCLKIN Tsu_* INPUT inputs valid Th_*
When bypass mode input signals (SDCLK basis)
EJC-TMPR4927ATB-32 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
External Interface Characteristics
70°C, VddIO 3.3V 0.2V, VddIN 1.5V 0.1V, Signal Name
SYSCLK
Load
(pF)
Buffer Type
8mA(fix)
Tcyc_sysclk Thigh_sysclk Tlow_sysclk Tval_addr2 Tval_ce Tval_oe Tval_swe Tval_bwe Tval_ace Tval_bus Tval_data2 Tval_data2v Tval_data2z Tsu_data2 Th_data2 Tval_ack Tval_ackv Tval_ackz Tsu_ack Th_ack
Descriptions
Clock Cycle Time Clock High Time Clock Time Output Delay Address Output Delay Chip Enable Output Delay Output Enable Output Delay Write Enable Output Delay Byte Enable Output Delay Address Clock Enable Output Delay Separate Output Delay Data (High Low) Output Delay Data (Hi-Z valid) Output Delay Data (valid Hi-Z) Data Setup Time Data Hold Time Output Delay ACK* (High Low) Output Delay ACK* (Hi-Z valid) Output Delay ACK* valid Hi-Z) ACK* Setup Time ACK* Hold Time
(ns)
(ns)
ADDR[19:5] CE[7:0]* SWE* BWE*[3:0] ACE* BUSSPRT* DATA[31:0]
16mA 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 8mA(fix) 16mA
ACK*
8mA(fix)
Tcyc_sysclk Thigh_sysclk Tlow_sysclk
SYSCLK Tval_*
OUTPUT Tsu_* Th_*
outputs valid
INPUT
inputs valid
External Interface
EJC-TMPR4927ATB-33 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Interface Characteristics
Signal Name PCICLKIN PCI-bus Load Spec. 66MHz (pF) Tcyc66 Thigh66 Tlow66 Tslew66 33MHz Tcyc33 Thigh33 Tlow33 Tslew33 PCICLK[5:0] 66MHz Tcyco66 Thigho66 Tlowo66 33MHz Tcyco33 Thigho33 Tlowo33 PCIAD[31:0] C_BE[3:0] FRAME* IRDY* TRDY* STOP* DEVSEL* PERR* SERR* LOCK* M66EN PME* ID_SEL REQ[3:0]* GNT[3:0]* 66MHz 33MHz Tskw Tval66 Tsu66 Th66 Tval33 Tsu33 Th33 Descriptions Input Clock Cycle Time Input Clock High Time Input Clock Time Input Clock Through rate [V/ns] Input Clock Cycle Time Input Clock High Time Input Clock Time Input Clock Through rate [V/ns] Output Clock Cycle Time Output Clock High Time Output Clock Time Output Clock Cycle Time Output Clock High Time Output Clock Time Output Clock Slew (point point connection) Output Delay (bus connection) Setup Time (bus connection) Hold Time (bus connection) Output Delay (bus connection) Setup Time (bus connection) Hold Time (bus connection) (ns) (TBD) (ns)
66MHz
Tppd66 Tpps66 Tpph66 Tppd33 Tpps33 Tpph33
Output Delay (point point connection) Setup Time (point point connection) Hold Time (point point connection) Output Delay (point point connection) Setup Time (point point connection) Hold Time (point point connection)
33MHz
EJC-TMPR4927ATB-34 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Tcyc66/Tcyc33
Thigh66/Thigh33 (Vcc=3.3V) PCICLKIN
Tlow66/Tlow33 Tslew66/Tslew33
p-to-p (minimum)
Tsu66/Tsu33/Tpps66/Tpps33
Th66/Th33/Tpph66/Tpph33
INPUT
inputs valid
Tval66/Tval33/Tppd66/Tppd33
OUTPUT
outputs valid
Interface (3.3V)
Tcyco66/Tcyco33 Thigho66/Thigho33 Tlowo66/Tlowo33
PCICLK[n] Tskw
PCICLK [except
Clock Skew
EJC-TMPR4927ATB-35 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
Package
EJC-TMPR4927ATB-36 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
HISTORY
Modify description SDRAM Controller Modify layout Modify from signal TEST2 signal 13/Jan/01 Added Package Diagram 22/Jan/01 DC/AC Timing 26/Jan/01 Modify description 6/Feb/01 Modify description 20/Aug/01 17/Jan/02 Modify Signal description Characteristics Modify product name TMPR4927TB TMPR4927ATB-200 Modify spec 28/Aug/00
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TOSHIBA RISC PROCESSOR TMPR4927ATB-200 TOSHIBA RISC PROCESSO

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