TOSHIBA RISC PROCESSOR TMPR4925XB TOSHIBA RISC PROCESSOR
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INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TOSHIBA RISC PROCESSOR
TMPR4925XB
(64-bit RISC MICROPROCESSOR) GENERAL DESCRIPTION TMPR4925XB, referred TX4925 MIPS RISC micro-controller highly integrated ASSP solution based Toshiba's TX49/H2 processor core, 64-bit MIPS I,II,III Instruction Architecture (ISA) compatible with additional instructions. TX4925 highly integrated device with integrated peripherals such SDRAM memory controller, NAND Flash memory controller, controller, AC-Link controller, PIO, SIO, SPI, CHI, PCMCIA Timer. This class product targeted applications that require high performance cost-effective solution such networking, digital consumer Internet appliance.
FEATURES
TX49/H2 core with integrated IEEE 754-compliant single- double-precision operations 4-channel SDRAM Controller 32bit/80MHz support SyncFlash® memory NAND Flash memory Controller 6-channel External Controller 32-bit Controller MHz) 4-channel Direct Memory Access (DMA) Controller 2-channel Serial Port Parallel Port 32-bit) AC-Link Controller AC97 Interface PCMCIA Interface (2-slot) (Serial Peripheral Interface) (high-speed serial Concentration Highway Interface) Interrupt Controller 3-channel Timer/Counter 44-bit up-counter power dissipation TX4925 operates with 1.5V core 3.3V I/O, while supporting low-power (Halt) mode. maximum operating frequency: IEEE1149.1 (JTAG) support: Debug Support Unit (Enhanced JTAG) 256-pin PBGA package
products described this document subject foreign exchange foreign trade control laws. information contained herein subject change without notice. TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, observe standards safety, avoid situations which malfunction failure TOSHIBA product could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent products specifications. Also, please keep mind precautions conditions forth TOSHIBA Semiconductor Reliability Handbook. EJC-TMPR4925XB-1 information contained herein presented only guide applications products. responsibility assumed 26/Dec/01 TOSHIBA infringements patents other rights third parties which result from use. license granted TOSHIBA CORPORATION implication otherwise under patent patent rights TOSHIBA others.
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Internal Block Diagram Figure shows TX4925 internal block diagram. Debug (DSU)
D$(16K)
NAND Flash SDRAMC DMAC
32bit Gbus
I$(16K)
TX49/H2 Core
External Controller External Interface (32bit) PCIC
bridge
ACLC
Timer
Figure TX4925 Internal Block Diagram
EJC-TMPR4925XB-2 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
System Block Diagram Figure shows system block diagram with TX4925.
32bit Gbus
NAND Flash SDRAMC DMAC External Controller
Command/Data/ Address signals SDRAM Control signals
NAND Flash Memory SDRAM Memory Devices
Debug (DSU) D$(16K) I$(16K)
External System (Data=32bit, Address=20bit)
External Interface
TX49/H2 Core PCIC
Control Signals
ROM/ Flash/ SRAM
External Devices
bridge
ACLC
Timer
Devices
User logic PCIC
Figure Typical TX4925 System Block Diagram
EJC-TMPR4925XB-3 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TX49/H2 Core Block Diagram Figure shows internal block diagram TX49/H2 core
TX49/H2 Core
Integer Unit
Data Path Pipeline Control
Registers MMU/TLB Exception Unit
Debug Support Unit
16KB 4-way Instruction Cache
Write Buffer
16KB 4-way Data Cache
Figure TX49/H2 Core Block Diagram
TX49/H2 CORE FEATURES TX49/H2 Core high performance low-power 64-bit RISC processor core developed Toshiba. 64-bit operation 64-bit integer general purpose registers 32-bit physical address space 64-bit virtual address space Optimized 5-stage pipeline Instruction MIPS compatible PREF (Prefetch) (Multiply/Accumulate) instructions. Byte Instruction Cache, Byte Data Cache 4-way associative with lock function (Memory Management Unit): 48-entry fully associative JTLB on-chip supports both single- double-precision arithmetic, specified IEEE 754. On-chip 4-deep write buffer Enhanced JTAG debug feature Built-in Debug Support Unit (DSU)
EJC-TMPR4925XB-4 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TX4925 Peripheral Circuit FEATURES External Controller EBUSC External Controller generates necessary signals control external memory devices. channels chip select signals, enabling control devices (shared chip select signals channels) Supports access including mask ROM, page mode ROM, EPROM EEPROM), SRAM, flash ROM, devices Supports 32-bit, 16-bit 8-bit data sizing channel basis Supports selection among full speed 80MHz speed 40MHz), speed 27MHz speed 20MHz) channel basis Support specification timing channel basis user specify setup hold times address, chip enable, write enable, output enable signals Supports memory sizes byte byte devices with 32-bit data bus, byte 512M bytes devices with 16-bit data bus, byte 256M bytes devices with 8-bit data Controller DMAC TX4925 contains 4-channel controller that executes transfer memory devices. 4-channel independently handling internal external requests (Usable only channels external requests) Supports transfer with built-in serial controller AC-link controller based internal requests Supports signal address fly-by dual address transfers external transfer mode using external requests Supports transfer between memory external devices having 8-bit data Supports memory-to-memory copy mode, with address boundary restrictions Supports burst transfer double words single read write Supports memory fill mode, writing double-word data specified memory area Supports chained transfer
EJC-TMPR4925XB-5 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
SDRAM Controller SDRAMC SDRAM Controller generates necessary control signals SDRAM interface. four channels handle bytes MB/channel memory supporting variety memory configurations. Memory clock frequency 80MHz (divided 2.5) sets independent memory channels Supports 128M 256M 512M-bit SDRAM with bank size availability Supports Single Data Rate (SDR) SDRAM SyncFlash® memory Supports Registered DIMM Supports 16-bit data sizing channel basis Supports specification SDRAM timing channel basis Supports critical word first access TX49/H2 core power mode selectable between self-refreshing pre-charge power-down
Controller PCIC TX4925 contains Controller that complies with Local Specification Revision 2.2. Compliance with Local Specification Revision (Partly supports power management optional function) 32-bit interface featuring maximum clock frequency 33MHz Supports both target initiator functions Supports change address mapping between internal arbiter enables connection external masters Supports booting TX4925 from memory channel controller dedicated controller PDMAC
Serial Controller TX4925 contains 2-channels asynchronous serial interface full duplex UART 2-channel full duplex UART Built-in baud rate generator FIFOs 8-bit transmitter FIFO 13-bit data bits status bits receiver FIFO Supports tranfer
EJC-TMPR4925XB-6 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Timers Counters Controller TX4925 contains 3-channel timer counters. 3-channel 32-bit up-counter Supports three modes interval timer mode, pulse generator mode, watchdog timer mode timer output pins count clock input
Parallel Ports TX4925 contains 32-bit parallel ports Independent selection direction pins output port type totem-pole open-drain outputs basis. (PIO[4,2,0] input-only pins.)
AC-link controller ACLC TX4925 contains AC-link controller, which operated using audio modem CODECs described Audio CODEC'97 Revision AC'97 Supports CODECs Supports recording playback right left 16-bit channels Supports playback 16-bit surround, center, channels Supports audio recording layback variable rate Supports Line1 GPIO slots modem CODEC Supports AC-link power mode, wakeup, warm reset Supports input output sample data transfer
EJC-TMPR4925XB-7 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Interrupt Controller TX4925 contains interrupt controller, which receives interrupt requests sent both TX4925's built-in peripherals external devices issues interrupt requests TX49/H2 core. 32-bit flag register generate interrupt requests external devices TX49/H2 core. Supports internal interrupt sources from built-in peripherals external interrupt signal inputs interrupt priority levels each interrupt source Supports selection between edge- level-triggered interrupt detection each external interrupt 32-bit read write flag register interrupt requests, making possible issue interrupt request external devices TX49/H2 core interrupts
high-speed serial Concentration Highway Interface TX4925 high-speed serial Concentration Highway Interface. Contents logic interfacing external full-duplex serial time-division-multiplexed (TDM) communication peripherals Supports ISDN line interface chips other PCM/TDM serial devices Programmable Interface (numbers channels, frame rate, rate, etc.) supports data rates 4.096Mbps
Serial Peripheral Interface TX4925 Serial Peripheral Interface. full-duplex, synchronous serial data transfers (data in/out, clock signals) 8-bit 16-bit data word lengths Programmable baud rate
NAND Flash memory Controller NDFMC TX4925 NAND Flash memory Controller. Controlled NAND Flash Setting Register Supports (Error Correct Circuit) control flow
EJC-TMPR4925XB-8 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
PCMCIA Interface PCMCIA TX4925 identical full PCMCIA ports. Provide control signals accepts status signals which conform PCMCIA version standard Appropriate connector keying level-shifting buffers required 3.3V versus PCMCIA interface implementations
Real Time Clock TX4925 Real Time Clock. 44-bit up-counter Interrupts alarm, timer, prior roll-over Date managed software
Power-down mode TX4925 contains support implementation power-down mode. HALT mode (stopping core clock) TX49/H2 core block Power-down mode (stopping input clock) individual internal peripheral modules RF(Reduced Frequency) Function (1/1,1/2,1/4,1/8)
Extended EJTAG Interface TX4925 contains Extended Enhanced Joint Test Action Group Extended EJTAG interface, which provides functions JTAG boundary scan test that complies with IEEE1149.1 real-time debugging using debug support unit built into TX49/H2 core. IEEE 1149.1 JTAG Boundary Scan Real-time debugging functions using special emulation probe execution control execution, break, step, register memory access trace
EJC-TMPR4925XB-9 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE Pins
designations
PCICLKIO TDI* PIO[26] PIO[24] PIO[27] PIO[22] PIO[19] SDCLKIN* SDCLK[1] SDCLK[0] SDCS [2]* ADDR[18] SADDR10 ADDR[13] ADDR[10] ADDR[8] ADDR[6] SDCS [1]* RAS* PCICLK[1] [0]* PIO[31] PIO[29] PIO[21] PIO[18] PIO[20] SDCS [3]* ADDR[19] ADDR[14] ADDR[12] ADDR[9] ADDR[7] ADDR[5] DQM[3]* SDCS [0]* PCICLK[2] [0]* VDDS VDDC PIO[25] PIO[28] VDDC PIO[23] TRST VDDC SCANENB ADDR[17] ADDR[16] VDDC ADDR[11] VDDC VDDS DQM[2]* [2]* [1]* [1]* VDDC PIO[30] VDDS PON* VDDS VDDS VDDS CAS* DQM[0]* PCIAD[31] [3]* [3]* [2]* VDDS DATA[31] PCIAD[28] PCIAD[30] VDDS DATA[14] DATA[30] DATA[15] PCIAD[26] PCIAD[27] VDDC VDDC DATA[13] DATA[29] BE[3] PCIAD[24] PCIAD[25] VDDS VDDS DATA[12] DATA[28] PCIAD[22] PCIAD[23] IDSEL VDDC DATA[11] PCIAD[19] PCIAD[20] PCIAD[21] VDDS VDDC DATA[10] DATA[26] PCIAD[17] PCIAD[18] VDDC VDDS DATA[24] DATA[9] DATA[25] FRAME* BE[2] PCIAD[16] VDDS DATA[7] DATA[23] DATA[8] STOP* DEVSEL* TRDY* IRDY*
EJC-TMPR4925XB-10 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
RESET* DQM[1]* PCIAD[29] DATA[27] VDDS
EJC-TMPR4925XB-11 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
DATA[6] DATA[22] SERR* PERR* VDDC VDDC DATA[5] DATA[21] PCIAD[15] BE[1] VDDC DATA[19] DATA[4] DATA[20] PCIAD[12] PCIAD[13] PCIAD[14] VDDS
VDDS DATA[2] DATA[18] DATA[3] PCIAD[9] PCIAD[10] PCIAD[11] VDDS [2]* VDDS ROMCE PIO[0] VDDS PIO[6] PIO[7] DATA[16]
DATA[1] DATA[17] BE[0] PCIAD[8] VDDS VDDC [0]* [3]* VDDC ADDR[2] ROMCE PIO[2] VDDC PIO[1] PIO[5] VDDC PIO[13] PIO[16] TEST* VDDS DATA[0]
PCIAD[4] PCIAD[5] PCIAD[6] PCIAD[7] [1]* ADDR[0] ADDR[3] ADDR[15] ROMCE PIO[4] PIO[3] PIO[10] PIO[9] PIO[17] PIO[15] NMI* C32KOUT PLLVDD MSTRCLK PCIAD[0] PCIAD[1]
PCIAD[2] PCIAD[3] SYSCLK* SWE* ADDR[1] ADDR[4] ROMCE BUSSPRT* ACK* PIO[11] PIO[8] PIO[12] PIO[14] BC32K C32KIN PLLVSS
EJC-TMPR4925XB-12 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
layout
RAS*
SDCS [0]*
DQM[1]* DQM[2]* VDDS VDDC ADDR[11] VDDC ADDR[16] ADDR[17]
DQM[0]* CAS* VDDS VDDS
DATA[15] DATA[30] DATA[14]
DATA[29] DATA[13] VDDC
DATA[28] DATA[12] VDDS
DATA[27] DATA[11] VDDC
DATA[26] DATA[10] VDDC
SDCS [1]* DQM[3]* ADDR[6] ADDR[8] ADDR[10] ADDR[13] ADDR[5] ADDR[7] ADDR[9] ADDR[12]
DATA[31] VDDS
SADDR10 ADDR[14] ADDR[18] ADDR[19]
SDCS [2]* SDCLK[0] SDCLK[1] SDCLKIN* PIO[19] PIO[22] PIO[27] PIO[24] PIO[26] TDI* PCICLKIO SDCS [3]* RESET* PIO[20] PIO[18] PIO[21] PIO[29] PIO[31] [0]* PCICLK[1]
SCANENB VDDS VDDC TRST PIO[23] VDDC PIO[28] PIO[25] VDDC VDDS [0]* PCICLK[2] PON* VDDS PIO[30] VDDC [1]* [1]* [2]* View [2]* [3]* [3]* PCIAD[31] VDDS PCIAD[30] PCIAD[29] PCIAD[28] VDDC PCIAD[27] PCIAD[26] VDDS PCIAD[25] PCIAD[24] BE[3] IDSEL PCIAD[23] PCIAD[22] VDDS PCIAD[21] PCIAD[20] PCIAD[19]
EJC-TMPR4925XB-13 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
DATA[25] DATA[9] DATA[24] VDDS
DATA[8] DATA[23] DATA[7]
DATA[22] DATA[6] VDDS
DATA[21] DATA[5] VDDC
DATA[20] DATA[4] DATA[19]
DATA[3] DATA[18] DATA[2] VDDS
DATA[17] DATA[1] DATA[16] PIO[7] PIO[6] VDDS PIO[0]
MSTRCLK PLLVDD C32KOUT NMI* PIO[15] PIO[17] PIO[9] PIO[10] PIO[3] PIO[4]
DATA[0] VDDS TEST* PIO[16] PIO[13] VDDC PIO[5] PIO[1] VDDC PIO[2]
PLLVSS C32KIN BC32K PIO[14] PIO[12] PIO[8] PIO[11] ACK* BUSSPRT*
ROMCE ROMCE ADDR[4] ADDR[1] SWE* SYSCLK* PCIAD[3] PCIAD[2] PCIAD[1] PCIAD[0]
ROMCE ROMCE ADDR[15] VDDS ADDR[2] VDDC ADDR[3] ADDR[0] [1]* PCIAD[7] PCIAD[6] PCIAD[5] PCIAD[4]
[2]* [3]* View VDDC PCIAD[18] PCIAD[17] VDDS PCIAD[16] BE[2] FRAME* IRDY* TRDY* DEVSEL* STOP* VDDC PERR* SERR* VDDC BE[1] PCIAD[15] VDDS PCIAD[14] PCIAD[13] PCIAD[12] VDDS PCIAD[11] PCIAD[10] PCIAD[9] [0]* VDDC VDDS PCIAD[8] BE[0]
EJC-TMPR4925XB-14 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
signal description
Note: columns, "PU" indicates with pull-up resistor, term "PD" indicates with pull-down resistor. denotes active-low signal when used suffix signal name.
Common Memory Interface
Signal Name ADDR[19:0] Type Input/ou tput Function Address Address signals. SDRAM, ADDR[19:16 14:5] SADDR10 used. When external controller uses these pins, meaning each varies with data width. ADDR signals also used boot configuration signals (input) during reset. details configuration signals. ADDR signals input signals only when RESET* signal asserted become output signals after RESET* signal deasserted. Address10 SDRAM. Address single SDRAM. This signal also used boot configuration input signal testing. Because this signal used testing, ensure that will pulled during reset sequence. details configuration signals. This signal used input signal while RESET* signal asserted. becomes output signal once RESET* signal been deasserted. Data 32-bit data Separate Controls connection separation devices controlled external controller from high-speed device, such SDRAM. Separate devices other than SDRAM from data bus. Connect devices other than SDRAM data bus. Separation connection performed using external bidirectional buffers (such 74xx245). This signal control either QuickSwitch 74xx245. These devices differ that signal also pulled during write cycle with QuickSwitch. Boot configuration signal ADDR[19] determines hich device used. details configuration signals. Initial State Input
SADDR10
Input/ou tput
Input
DATA[31:0]
BUSSPRT*
Input/ou tput Output
Input
High
EJC-TMPR4925XB-15 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
SDRAM SyncFlash Memory Interface
Signal Name SDCLK[1:0] Type Output Function SDRAM Controller Clock Clock signals used SDRAM/SyncFlash. clock frequency same G-Bus clock (GBUSCLK) frequency. When these clock signals used, pins using SDCLK Enable field configuration register (PCFG.SDCLKEN[1:0]). SDRAM Feedback Clock input Feedback clock signal SDRAM controller input signals. Clock Enable signal SDRAM/SyncFlash. Synchronous Memory Device Chip Select Chip select signals SDRAM/SyncFlash. Address Strobe signal SDRAM/SyncFlash. Column Address Strobe signal SDRAM/SyncFlash. Write Enable signal SDRAM/SyncFlash. Data Mask During write cycle, signals function data mask. During read cycle, they control SDRAM output buffers. bits correspond following data signals: DQM[3]:DATA[31:24], DQM[2]:DATA[23:16] DQM[1]:DATA[15:8], DQM[0]:DATA[7:0] Initialize/Power Down signal SyncFlash. Initial State High
SDCLKIN SDCS[3:0]* RAS* CAS* DQM[3:0]
Input/out Output Output Output Output Output Output
Input High High High High High High
Output
EJC-TMPR4925XB-16 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
External Interface
Signal Name SYSCLK Type Output Function System Clock Clock external devices. Outputs clock full speed mode same frequency G-Bus clock (GBUSCLK) frequency), half speed mode half GBUSCLK frequency), third speed mode third GBUSCLK frequency), quarter speed mode quarter GBUSCLK frequency). boot configuration signals ADDR[4:3] pins select which speed mode will used. When this clock signal used, using SYSCLK Enable configuration register (PCFG.SYSCLKEN). Upper Address Enable Latch enable signal high-order address bits ADDR. enable polarity selected. This signal also used boot configuration input signal testing. Because this signal used testing, ensure that will pulled during reset sequence. details configuration signals. This signal used input signal while RESET* signal asserted. becomes output signal once RESET* signal been deasserted. Chip Enable Chip select signals ROM, SRAM, devices. pins shared with other functions. Chip Enable Chip select signals ROM, SRAM, devices. Output Enable Output enable signal ROM, SRAM, devices. Write Enable Write enable signal SRAM devices. Byte Enable/Byte Write Enable BE[3:0]* indicate valid data position data DATA[31:0] during read write operation. 16-bit mode, only BE[1:0]* used. 8-bit mode, only BE[0]* used. BWE[3:0]* indicate valid data position data DATA[31:0] during write operation. 16-bit mode, only BWE[1:0]* used. 8-bit mode, only BWE[0]* used. following shows correspondence between BE[3:0]*/BWE[3:0]* data signals. BE[3]*/BWE[3]*: DATA[31:24] BE[2]*/BWE[2]*: DATA[23:16] BE[1]*/BWE[1]*: DATA[15:8] BE[0]*/BWE[0]*: DATA[7:0] boot configuration signal ADDR[11] EBCCRn.BC external controller determine whether signals used BE[3:0]* BWE[3:0]*. Data Acknowledge/Ready Flow control signal. Initial State High
Output
Input
CE[5:4]*
Output Output Output Output Output
High
CE[3:0]* SWE* BWE[3:0]* /BE[3:0]*
High High High High
ACK*/ READY
Input/out
Input
EJC-TMPR4925XB-17 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Signal Name CARD1CSH* CARD1CSL* CARD2CSH* CARD2CSL* CARDREG* Type Output Output Output Output Output Output Function PCMCIA card slot chip select Chip select signals PCMCIA card slot pins shared with other functions. PCMCIA card slot chip select Chip select signals PCMCIA card slot pins shared with other functions. PCMCIA card register REG* signal PCMCIA card. shared with other functions. PCMCIA card read IORD* signal PCMCIA card. shared with other functions. PCMCIA card write IOWR* signal PCMCIA card. shared with other functions. PCMCIA card directory Controls direction bidirectional buffer used PCMCIA slot. This signal asserted during read transaction when CARD2CSH*, CARD2CSL*, CARD1CSH* CARD1CSL* asserted. shared with other functions. PCMCIA card slot wait Card wait signal from PCMCIA card slot shared with other functions. PCMCIA card slot wait Card wait signal from PCMCIA card slot shared with other functions. Initial State input
input
input
CARDIORD*
input
CARDIOWR*
input
CARDDIR*
input
CARD1WAIT*
Input Input
input
CARD2WAIT*
input
EJC-TMPR4925XB-18 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Interface
Signal Name DMAREQ [1:0] Type Input Output Function Request transfer request signals from external device. pins shared with other functions. Acknowledge transfer acknowledge signals external device. pins shared with other functions. Done DMADONE* either used output signal that reports termination transfer input signal that causes transfer terminate. shared with other functions. Initial State input
DMAACK [1:0]
input
DMADONE*
Input/out
input
Interface
Signal Name PCICLK [2:1] Type Output Function Clock clock signals. boot configuration signal (ADDR[18]) determine whether clock internally generated TX4925 used PCICLK. TX4925 internal clock selected, clock signals output from these pins. When these clock signals used, pins Hi-Z using PCICLK Enable field configuration register (PCFG.PCICLKEN[2:1]). Feedback Clock feedback clock input. boot configuration signal (ADDR[18]) determine whether clock internally generated TX4925 used PCICLK. TX4925 internal clock selected, clock signals output simultaneously back internal block. When using block, therefore, PCICLK Enable field configuration register (PCFG.PCICLKIOEN) Address Data Multiplexed address data bus. Command Byte Enable Command byte enable signals. Parity Even parity signal PCIAD[31:0] C_BE[3:0]*. Cycle Frame Indicates that operation progress. Initiator Ready Indicates that initiator ready complete data transfer. Target Ready Indicates that target ready complete data transfer. Stop target sends this signal initiator request termination data transfer. Initial State Selected ADDR[18] High
PCICLKIO
Input/out
Selected ADDR[18] High Input
PCIAD [31:0] C_BE [3:0] FRAME* IRDY* TRDY* STOP*
Input/out Input/out Input/out Input/out Input/out Input/out Input/out
Input Input Input Input Input Input Input
EJC-TMPR4925XB-19 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Signal Name ID_SEL DEVSEL* [3:2] Type Input Input/out Input Function Initialization Device Select Chip select signal used configuration access. Device Select target asserts this signal response access from initiator. Request Signals used master request mastership. boot configuration signal ADDR[1] determines whether built-in arbiter used. internal arbiter mode, REQ[3:2]* request input signals. external arbiter mode, REQ[3:2]* used. Because pins still placed input state, they must pulled externally. Request Signal used master request mastership. boot configuration signal ADDR[1] determines whether built-in arbiter used. internal arbiter mode, this signal request input signal. external arbiter mode, this signal external interrupt output signal (INTOUT). Request Signal used master request mastership. boot configuration signal ADDR[1] determines whether built-in arbiter used. internal arbiter mode, this signal request input signal. external arbiter mode, this signal request output signal. Grant Indicates that mastership been granted master. boot configuration signal ADDR[1] determines whether built-in arbiter used. internal arbiter mode, GNT[3:0]* grant output signals. external arbiter mode, GNT[0]* grant input signal. Because GNT[3:1]* also become input signals, they must pulled externally. Data Parity Error Indicates data parity error cycle other than special cycles. System Error Indicates address parity error, data parity error special cycle, fatal error. host mode, SERR* input signal. satellite mode, SERR* open-drain output signal. mode determined boot configuration signal ADDR[19] pin. Initial State Input Input Input
Input/out put/OD
Selected ADDR[1] Input Hi-Z Selected ADDR[1] Input High Selected ADDR[1] High Input
Input/out
[3:0]
Input/out
PERR* SERR*
Input/out Input/OD
Input Input
EJC-TMPR4925XB-20 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Interface
Signal Name [1:0]* Type Input PU*1 Output PU*1 Input PU*1 3-state Output PU*1 Input Function Clear Send CTS* signals. pins shared with other functions. Request Send RTS* signals. pins shared with other functions. Receive Data Serial data input signals. pins shared with other functions. Transmit Data Serial data output signals. pins shared with other functions. External Serial Clock clock input signal. SIO0 SIO1 share this signal. shared with other functions. Initial State input
[1:0]*
input
RXD[1:0]
input
TXD[1:0]
input
SCLK
input
These signals pulled channel only. pull-up resistor provided channel
Timer Interface
Signal Name TIMER[1:0] Type Output Input Function Timer Output Timer output signals. pins shared with other functions. External Timer Clock Timer input clock signal. TMR0, TMR1, TMR2 share this signal. shared with other functions. Initial State input
TCLK
input
Interface
Signal Name PIO[31:20] Type Input/out Function Ports[31:20] Parallel signals. pins shared with other functions, including trace. boot configuration signal determines whether signals used trace. Initial State Selected input Output trace function) Input
PIO[19:0]
Input/out PU*1
Ports[19:0] Parallel signals. pins shared with other functions.
PIO[17:12] have pull-up resistors.
EJC-TMPR4925XB-21 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Link Interface
Signal Name ACRESET* SYNC SDOUT SDIN]1] SDIN[0] BITCLK Type Output Output Output Input Input Input Function Master Reset shared with other functions. Fixed Rate Sample Sync shared with other functions. Serial, Time Division Multiplexed, Output Stream shared with other functions. Serial, Time Division Multiplexed, Input Stream shared with other functions. Serial, Time Division Multiplexed, Input Stream shared with other functions. 12.288 Serial Data Clock shared with other functions. Initial State input input input input input input
Interrupt Signals
Signal Name NMI* INT[7:0]* Type Input Input Function Non-Maskable Interrupt Non-maskable interrupt signal. External Interrupt Requests External interrupt request signals. pins shared with other functions. Initial State Input input
EJC-TMPR4925XB-22 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Interface
Signal Name CHIFS Type Input/out Function Frame synchronization frame synchronization signal. This used either output input mode. output mode, allows TX4925 become master synchronization source. input mode, allows external peripheral device become master synchronization source. that case, TX4925 module becomes slave external synchronization. shared with other functions. Clock clock signal. This used either output input mode. output mode, allows TX4925 become master clock source. input mode, allows external peripheral device become master clock source. that case, TX4925 module becomes slave external clock. shared with other functions. Data Output serial data output signal. shared with other functions. Data Input serial data input signal. shared with other functions. Initial State input
CHICLK
Input/out
input
CHIDOUT
Output Input
input
CHIDIN
input
Interface
Signal Name SPICLK Type Output Output Input Function Clock This used data clock from slave device. shared with other functions. Data Output This signal contains data shifted slave device. shared with other functions. Data Input This signal contains data shifted from slave device. shared with other functions. Initial State input
SPIOUT
input
SPIIN
input
EJC-TMPR4925XB-23 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
NAND Flash Memory Interface
Signal Name ND_ALE Type Output Function NAND Flash Address Latch Enable signal NAND flash memory. shared with other functions. NAND Flash Command Latch Enable signal NAND flash memory. shared with other functions. NAND Flash Chip Enable signal NAND flash memory. shared with other functions. NAND Flash Read Enable signal NAND flash memory. shared with other functions. NAND Flash Write Enable signal NAND flash memory. shared with other functions. NAND Flash Ready/Busy Ready/Busy signal NAND flash memory. shared with other functions. Initial State input
ND_CLE
Output
input
ND_CE*
Output
input
ND_RE*
Output
input
ND_WE*
Output
input
ND_R/B*
Input
input
EJC-TMPR4925XB-24 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
EJTAG Interface
Signal Name Type Input Input Function JTAG Test Clock Input Clock input signal JTAG. used execute JTAG instructions input/output data. JTAG Test Data Input/Debug Interrupt When trace mode selected, this signal JTAG data input signal. used input serial data JTAG data/instruction registers. When trace mode selected, this signal interrupt input signal used cancel trace mode debug unit. JTAG Test Data Output/PC Trace Output When trace mode selected, this signal JTAG data output signal. Data output means serial scan. When trace mode selected, this signal outputs value noncontiguous program counter sync with debug clock (DCLK). Trace Output TPC[3:1] output value noncontiguous program counter sync with DCLK. pins shared with other functions. Initial State Input
TDI/DINT*
Input
TDO/TPC[0]
Output
Input
TPC[3:1]
Output
TRST*
Input Input
DCLK
Output
PCST[8:0]
Output
JTAG Test Mode Select Input mainly controls state transition controller state machine. Test Reset Input Asynchronous reset input controller debug support unit (DSU). When EJTAG probe connected, this must fixed low. When connecting EJTAG probe, prevent floating, example, connecting pull-up resistor. When this signal deasserted, G-Bus timeout detection disabled. Debug Clock Clock output signal real-time debugging system. When trace mode selected, TPC[3:1] PCST signals output synchronously. This clock TX49/H2 core operating clock (CPUCLK) divided shared with other functions. Trace Status Information Outputs trace status other information. pins shared with other functions.
Selected input High Input Input
Selected input Selected input (PCST[8:1 BC32K(PC ST[0])
EJC-TMPR4925XB-25 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Clock signals
Signal Name MASTERCLK Type Input Function Master Clock Input TX4925 operating clock. crystal resonator cannot connected this because does contain oscillator. Crystal Input Connect this C32KOUT 32.768 crystal. Crystal output Connect this C32KIN 32.768 crystal. Buffer output Crystal Buffer output 32.768 clock. Initial State Input
C32KIN C32KOUT BC32K
Input Output Output
Input Output Selected Output (BC32K)
Reset signals
Signal Name RESET* PON* Type Input Input Reset Reset signal. Power Reset Initializes timing. Function Initial State Input Input
Test Signals
Signal Name TEST* SCANENB* Type Input Input Function Test Mode Setting Test pin. This must fixed High. Scan Mode Test Control Test pin. This must fixed High. Initial State Input Input
EJC-TMPR4925XB-26 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Power Supply Pins
Signal Name PLL1VDD_A Type Function Power Pins analog power supply pins. PLL1VDD_A Ground Pins analog ground pins. PLL1VSS_A Internal Power Pins Digital power supply pins internal logic. VccInt Power Pins Digital power supply pins input/output pins. VccIO Ground Pins Digital ground pins. Initial State
PLL1VSS_A
VccInt VccIO
EJC-TMPR4925XB-27 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE Multiplexing
total pins TX4925 have multiplexed functions. Table shows multiplexed pins. function given selected various ways, depending pin(s) involved.
Table Multiplexing
Signal name PIO[31] PIO[30] PIO[29] PIO[28] PIO[27] PIO[26] PIO[25] PIO[24] PIO[23] PIO[22] PIO[21] PIO[20] PIO[19] PIO[18] PIO[17] PIO[16] PIO[15] PIO[14] PIO[13] PIO[12] PIO[11] PIO[10] PIO[9] PIO[8] PIO[7] PIO[6] PIO[5] PIO[4] PIO[3] PIO[2] PIO[1] PIO[0] BC32K BE[3]*/BWE[3]* BE[2]*/BWE[2]*
Multiplexed Function PIO[31] CADDIR* BCLK TPC[2] PIO[30] CARDREG* PCST[8] PIO[29] CARD2CSH* CE5* INT[7] PCST[6] PIO[28] CARD2CSL* CE4* INT[6] PCST[7] PIO[27] CARD2WAIT* CHIOUT PCST[5] PIO[26] CARD1CSH* DCLK PIO[25] CARD1CSL* TPC[3] PIO[24] CARD1WAIT* TPC[1] PIO[23] SPICLK PCST[2] PIO[22] SPIIN PCST[3] PIO[21] SPIOUT PCST[4] PIO[20] TIMER[0] CHIFS PCST[1] PIO[19] TIMER[1] CHICLK PIO[18] TCLK CHIDIN PIO[17] AC_SDIN[0] ND_WE* TXD[1] PIO[16] AC_SDOUT ND_RB* RXD[1] PIO[15] AC_BITCLK ND_CLE RTS[1] INT[5] PIO[14] AC_SYNC ND_RE* CTS[1] INT[4] PIO[13] AC_SDIN[1] ND_ALE PIO[12] AC_RST* ND_CE* PIO[11] TXD[0] PIO[10] RXD[0] PIO[9] INT[3] PIO[8] INT[2] PIO[7] INT[1] PIO[6] INT[0] PIO[5] SCLK PIO[4] DMAACK[1] PIO[3] DMAREQ[1] PIO[2] DMAACK[0] PIO[1] DMAREQ[0] PIO[0] DMADONE PCST[0] CARDIOWR* CARDIORD*
EJC-TMPR4925XB-28 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
Note PIO[4], PIO[2], PIO[0] only input ports. Note enable interrupt these signals used other function because INT[7:0] directly connected IRC. Note CARD1WAIT* CARD2WAIT* directly connected PCMCIA controller. PCFG register control that enable CADRWAIT* CARD2WAIT* function. Note TCLK directly connected Timer ch0, ch2. Thus, Timer should enable external clock unless that desired function this pin. Note SCLK directly connected ch1. Thus, should enable external clock unless that desired function this pin. Note BE[3]*/BWE[3]* operates CARDIOWR* when TX4925 access PCMCIA device, BE[3]*/BWE[3]* when access other devices. BE[2]*/BWE[2]* operates CARDIORD* when TX4925 access PCMCIA device, BE[2]*/BWE[2]* when access other devices, too.
EJC-TMPR4925XB-29 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE ELECTRICAL CHARACTERISTICS
T.B.D
EJC-TMPR4925XB-30 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE Package
Package type (Package code) 256-pin PBGA PBGA[4L] (P-BGA256-2727-1.27A4)
Reference symbol
min. 2.20 0.60 26.8 26.8
typ. 2.33 1.17 0.75 0.56 27.0 24.13 27.0 24.13 1.27 0.635 0.15
max. 2.46 0.90 27.2 27.2
EJC-TMPR4925XB-31 26/Dec/01 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE HISTORY
-19/Feb/01 -10/Apl/01 -18/Apl/01 -21/May/01 -29/Aug/01 -26/Dec/01 (Rev 0.1) first edition Modify description Clock Signals signal description export regulation first page designations layout Modify description
EJC-TMPR4925XB-32 26/Dec/01 TOSHIBA CORPORATION
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