MC141598 CMOS Driver which consists high voltage driving signals drive
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MC141598 CMOS Driver which consists high voltage driving signals drive either 100-Segment 33-Common display 99-Segment 34Common display. 6800-series, 8080-series parallel interface Serial Peripheral interface capability operating with general MCU. Besides general driver features, chip Smart Bias Divider circuit such that minimized external component required applications. Single Supply Operation, 3.5V Minimum -15.0V Driving Output Voltage Current Sleep Mode(<0.5uA) Chip Voltage Generator External Power Supply chip DC-DC Converter chip Oscillator Selectable Multiplex ratio Chip Smart Bias Divider bias ratio 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface Serial Peripheral Interface Selectable Display Mode Display Mode Graphic Mode Chinese Character Mode Chip Display Data Smart Icon Mode Re-mapping Column Drivers Vertical Scrolling level Internal Contrast Control External Contrast Control Built-in Temperature Compensation Circuit Available Bare Standard (Tape Automated Bonding) Package
MC141598
MC141598T MC141598T1
MCC141598 ORDERING INFORMATION MCC141598 MC141598T MC141598T1R
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
MC141598 08/98
Block Diagram
COM0 SEG99 COM33 COM31 SEG0~SEG98 COM32
Buffer Cell Level Shifter
Level Selector
Display Timing Generator Driving Voltage Generator DC/DC Converter, Voltage Regulator, Smart Bias Divider, Contrast Control, Temperature Compensation
Latch MSTAT
Oscillator
GDDRAM Bits
Command Decoder
Command Interface Parallel Serial Interface
C68/80 (RD) (WR)
(SDA) (SCK)
MC141598 08/98
MC141598 08/98 MC141598T Assignment (Copper View)
VL6(C4N) D7(SDA) D6(SCK) E(RD) R/W(WR) C68/80 COM16 COM17 COM18 COM29 COM30 COM31 SEG0 SEG1 SEG2 SEG94 SEG95 SEG96 COM15 COM14 COM13 COM2 COM1 COM0 COM33 MSTAT
MOTOROLA MC141598T1 Assignment (Copper View)
MSTAT C68/80 R/W(WR) E(RD) D6(SCK) D7(SDA) VL6(C4N) COM33 COM0 COM1 COM2 COM13 COM14 COM15 SEG99/COM32 SEG98 SEG97 SEG2 SEG1 SEG0 COM31 COM30 COM29 COM18 COM17 COM16
MC141598 08/98
COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
MC141598 08/98
MCC141598 Assignment
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75
COM21 COM20 COM19 COM18 COM17 COM16 VL6(C4N) D7(SDA) D6(SCK) E(RD) R/W(WR) C68/80 MSTAT COM33 COM0 COM1 COM2 COM3 COM4
COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG99/COM32 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76
MCC141598 Coordinates
Name COM4 COM3 COM2 COM1 COM0 COM33 MSTAT C68/80 R/W(WR) E(RD) D6(SCK) D7(SDA) VL6(C4N) COM16 COM17 COM18 COM19 COM20 COM21 2426.2 2324.6 2223.0 2121.4 2019.8 1918.2 1816.6 1715.0 1621.0 1527.0 1433.0 1339.0 1245.0 1151.0 1057.0 963.0 869.0 775.0 681.0 587.0 493.0 399.0 305.0 211.0 117.0 23.0 -71.0 -165.0 -259.0 -353.0 -447.0 -587.4 -681.4 -775.4 -869.4 -963.4 -1057.4 -1151.4 -1245.4 -1339.4 -1433.4 -1527.4 -1621.4 -1715.4 -1817.0 -1918.6 -2020.2 -2121.8 -2223.4 -2325.0 -2426.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 1572.6 Name COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 -2823.0 1658.8 1557.2 1455.6 1354.0 1252.4 1150.8 1049.2 947.6 846.0 752.0 658.0 564.0 470.0 376.0 282.0 188.0 94.0 -94.0 -188.0 -282.0 -376.0 -470.0 -564.0 -658.0 -752.0 -846.0 -947.6 -1049.2 -1150.8 -1252.4 -1354.0 -1455.6 -1557.2 -1658.8 Name SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 -2426.0 -2324.4 -2222.8 -2121.2 -2019.6 -1918.0 -1816.4 -1714.8 -1613.2 -1511.6 -1410.0 -1316.0 -1222.0 -1128.0 -1034.0 -940.0 -846.0 -752.0 -658.0 -564.0 -470.0 -376.0 -282.0 -188.0 -94.0 94.0 188.0 282.0 376.0 470.0 564.0 658.0 752.0 846.0 940.0 1034.0 1128.0 1222.0 1316.0 1410.0 1511.6 1613.2 1714.8 1816.4 1918.0 2019.6 2121.2 2222.8 2324.4 2426.0 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 -1572.6 Name SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99/ COM32 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 2823.0 -1658.8 -1557.2 -1455.6 -1354.0 -1252.4 -1150.8 -1049.2 -947.6 -846.0 -752.0 -658.0 -564.0 -470.0 -376.0 -282.0 -188.0 -94.0 94.0 188.0 282.0 376.0 470.0 564.0 658.0 752.0 846.0 947.6 1049.2 1150.8 1252.4 1354.0 1455.6 1557.2 1658.8
Note:
Size Size
:6382 3865 9-43 44-51 52-59 60-78 79-86 (um) 89.9 82.3 89.9 114.3 114.3 114.3 (um) 114.3 114.3 114.3 89.9 82.3 89.9 87-96 97-127 128-137 138-145 146-164 165-172 (um) 89.9 82.3 89.9 114.3 114.3 114.3 (um) 114.3 114.3 114.3 89.9 82.3 89.9
MC141598 08/98
MAXIMUM RATINGS* (Voltages Referenced VSS, TA=25°C)
Symbol Tstg Input Voltage Current Drain Excluding Operating Temperature Storage Temperature Range Supply Voltage Parameter Value -0.3 +6.0 -7.5 -15.6 VSS-0.3 VDD+0.3 +150 Unit
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted limits Electrical Characteristics tables Description section.
This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that Vout constrained range (Vin Vout) VDD. Reliability operation enhanced unused input connected appropriate logic voltage level (e.g., either VDD). Unused outputs must left open. This device light sensitive. Caution should taken avoid exposure this device light source during normal operation. This device radiation protected.
ELECTRICAL CHARACTERISTICS (Voltage Referenced VSS, VDD=2.4 3.5V, TA=25°C; unless otherwise specified.)
Symbol Parameter Logic Circuit Supply Voltage Range Voltage Generator Circuit Supply Voltage Range Access Mode Supply Current Drain (VDD Pins) Test Condition (Absolute value referenced VSS) 3.0V, Voltage Generator Converter Enabled, Write accessing, Tcyc =1MHz, Osc. Freq.=22kHz, Display 3.0V, -5V, Voltage Generator DC-DC Converter Disabled, R/W(WR) Halt, Osc. Freq. 22kHz, Display -8V. VDD=3.0V, Driving Waveform Off, Osc. Freq. 22kHz, R/W(WR) halt. 3.0V, Driving Waveform Off, Oscillator Off, R/W(WR) halt. Voltage Generator Osc. Freq. 22kHz, Display -8V. Display Voltage Generator Enabled, DC/DC Converter Enabled, Osc. Freq.=50KHz, Regulator Enabled, Divider Enabled. Voltage Generator Disabled. Unit
Display Mode Supply Current Drain (VDD Pins)
Standby Mode Supply Current Drain (VDD Pins) Sleep Mode Supply Current Drain (VDD Pins) Icon Mode Supply Current Drain (VDD Pins) Driving Voltage Generator Output (VEE Pin)
ISLEEP
IICON
-15.6
-8.0
VLCD VICON VOH1
Driving Voltage Input (VEE Pin) Power Icon mode Voltage Output High Voltage (D0-D7) Output Voltage (D0-D7) Driving Voltage Source (VL6 Pin)
-15.6
-7.5
Iout=100µA
0.9*VDD
VOL1
Iout=100µA
0.1*VDD
Regulator Enabled (VL6 voltage depends Int/Ext Contrast Control) Regulator Disable.
VEE-0.5
Driving Voltage Source (VL6 Pin)
Floating
MC141598 08/98
ELECTRICAL CHARACTERISTICS (Voltage Referenced VSS, VDD=2.4 3.5V, TA=25°C; unless otherwise specified.)
Symbol VIH1 Parameter Input high voltage (RES, D0-D7,R/W(WR), D/C) Input voltage (RES, D0-D7, R/W(WR), D/C, S/P) Display Voltage Output (VL2, VL3, VL4, VL5, Pins) Voltage reference VDD, Smart Bias Divider Enabled, bias ratio Test Condition 0.8*VDD Unit
VIL1
-15V
1/5*VL6 2/5*VL6 3/5*VL6 4/5*VL6 1/6*VL6 2/6*VL6 4/6*VL6 5/6*VL6
0.2*VDD
Display Voltage Output (VL2, VL3, VL4, VL5, Pins)
Voltage reference VDD, Smart Bias Divider Enabled, bias ratio
Display Voltage Input (VL2, VL3,VL4, VL5, Pins)
Voltage reference VDD, External Voltage Generator, Smart Bias Divider Disabled
Output High Current Source (D0-D7, OSC2) Output Current Drain (D0-D7, OSC2) Output Tri-state Current Drain Source (D0-D7, OSC2) Input Current (RES, D0-D7, R/W(WR), D/C, S/P) Input Capacitance (OSC1, OSC2, logic pins) Variation Input (VDD fixed) Temperature Coefficient Compensation Flat Temperature Coefficient Temperature Coefficient Temperature Coefficient Temperature Coefficient
Vout=VDD-0.4V
Vout=0.4V
IIL/IIH
Regulator Enabled, Internal Contrast Control Enabled, Contrast Control Register (TC1=0, TC2=0, Voltage Regulator Disabled.) (TC1=0, TC2=1, Voltage Regulator Enabled.) (TC1=1, TC2=0, Voltage Regulator Enabled.) (TC1=1, TC2=1, Voltage Regulator Enabled.)
PTC0 PTC1 PTC2 PTC3
-0.20
formula temperature coefficient
TC(%)=
Vref 50°C Vref 50°C
X100% Vref 25°C
MC141598 08/98
ELECTRICAL CHARACTERISTICS (TA=25°C, Voltage referenced VSS, AVDD=DVDD=3V: unless otherwise specified.)
Symbol FOSC FFRM Parameter Test Condition FOSC 8*33 FOSC 8*33 FOSC 8*34 FOSC 8*34 Unit Oscillation Frequency Display timing generator Internal Oscillator Enabled Frame Frequency Display Graphic Display Mode
Display Pseudo Graphic Display Mode Display Graphic Display Mode
Display Chinese Character Display Mode
MC141598 08/98
TABLE Parallel Timing Characteristics (TA=25°C, VDD=2.7V, VSS=0V)
Symbol tcycle tDSW tDHW tDHR tACC PWCSL PWCSH Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Pulse Width (read) Chip Select Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Unit
R/W(WR)
E(RD) tcycle PWCSL (CS2=1) tDSW D0-D7 (Write data driver) tACC D0-D7 (Read data from driver) Valid Data Valid Data
PWCSH
tDHW
tDHR
Figure Parallel 6800-series Interface Timing Characteristics
MC141598 08/98
TABLE Parallel Timing Characteristics (TA=25°C, VDD=2.7V, VSS=0V)
Symbol tcycle tDSW tDHW tDHR tACC PWCSL PWCSH Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Pulse Width (read) Chip Select Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Parameter Unit
R/W(WR)
E(RD) tcycle PWEL (CS2=1) (Read data from driver) D0-D7 (Write data driver) tACC D0-D7 Valid Data tDSW Valid Data PWEH
tDHW
tDHR
Figure Parallel 8080-series Interface Timing Characteristics
MC141598 08/98
TABLE Serial Timing Characteristics (TA=25°C, DVDD=2.7V, VSS=0V)
Symbol tcycle tCSS tCSH tDSW tDHW tCLKL tCLKH Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time Rise Time Fall Time Parameter 1000 Unit
(CS2=1) tCSS tcycle tCLKL tDSW Valid Data tDHW tCLKH tCSH
Figure Serial Timing Characteristics
MC141598 08/98
DESCRIPTIONS
This master/slave mode select input. When high, master mode selected MSTAT will output slave devices. When low, slave mode selected inputs from master device while MSTAT become This frame signal input/output. master mode, supplies frame signal slave devices while slave mode, receives frame signal from master device. MSTAT This used together with master operation static drive output. becomes slave operation. This display clock input/output. master mode, supplies display clock signal slave devices while slave mode, receives display clock signal from master device. This blanking control input/output. master mode, supplies on/off signal slave devices. slave mode, receives on/off signal from master device. This common drive signal output master operation. becomes slave operation. This monitoring internal output voltage different testing purposes. This reset signal input. When low, initialization chip executed. This serial/parallel interface select input. When high, parallel mode selected when low, serial mode selected. serial mode, only write operation allowed. CS1, These chip select inputs. chip enabled data operation only when high. 68/80 This microprocessor interface select input. When high, 6800 series interface selected when low, 8080 series interface selected D0-D7 These pins 8-bit bi-directional data connected microprocessor's data bus. When serial mode selected, serial data input serial clock input SCK. This control/display data input flag. When high, data D0-D7 display data. When low, data D0-D7 control data. R/W(WR) This microprocessor interface signal. When interfacing 6800-series microprocessor, signal indicates read mode when high write mode when low. When interfacing 8080-
microprocessor, data write operation initiated when R/W(WR) chip selected. E(RD) This microprocessor interface signal. When interfacing 6800-series microprocessor, data operation initiated when E(RD) high chip selected. When interfacing 8080microprocessor, data read operation initiated when E(RD) chip selected. Power supply pin. Ground. This most negative voltage supply pin. supplied externally generated internal DC-DC converter. C4N, C3N, C1P, C1N, When internal DC-DC voltage converter used, external capacitor(s) is/are connected among these pins. This most negative driving voltage. supplied externally generated internal regulator. This input internal voltage regulator. When internal regulator used generate VL6, external resistors connected between VL6, respectively (see application circuit). Moreover, this used contrast adjustment. Internal current will flow from this external resistor when contrast control command set. VL2, VL3, (Voltages referenced VDD) driving voltages. They supplied externally generated internal smart bias divider. They have following relationship: bias 1/5*VL6 2/5*VL6 3/5*VL6 4/5*VL6 bias 1/6*VL6 2/6*VL6 4/6*VL6 5/6*VL6
COM0 COM31 These pins provide driving signal panel. Their voltage level during sleep mode standby mode. SEG99/COM32 This functions either SEG99 COM32 Display Mode. Display Mode selected software command. COM33 This special icon indicator line. SEG0 SEG98 These pins provide column driving signal. Their voltage level during sleep mode standby mode.
MC141598 08/98
OPERATION LIQUID CRYSTAL DISPLAY DRIVER Description Block Diagram Module
Command Decoder Command Interface This module determines whether input data interpreted data command. Data directed this module based upon input pin. high, data written Graphic Display Data (GDDRAM). low, input D0-D7 interpreted Command will decoded written corresponding command register. Reset same function Power Reset (POR). Once receives negative reset pulse about 1us, internal circuitry will back initial status. Refer Command Description section more information. Parallel 6800-series Interface parallel interface consists bi-directional data pins (D0-D7), R/W(WR), D/C, E(RD), CS2. R/W(WR) input High indicates read operation from Graphic Display Data (GDDRAM) status register.R/W(WR) input indicates write operation Display Data Internal Command Registers depending status input. E(RD) input serves data latch signal (clock) when high provided that high respectively. Refer Figure parallel timing characteristics Parallel Interface Timing Diagram 6800-series microprocessor order match operating frequency display with that microprocessor, some pipeline processing internally performed which requires insertion dummy read before first actual display data read. This shown Figure below. Parallel 8080-series interface parallel interface consists bi-directional data pins (D0-D7), E(RD), R/W(WR), D/C, CS2. E(RD) input serves data read latch signal (clock) when provided that high respectively. Whether display data status register read controlled D/C. R/W(WR) input serves data write latch signal(clock) when high provided that high respectively. Whether display data command register write controlled D/C. Refer Figure parallel timing characteristics Parallel Interface Timing Diagram 8080-series microprocessor. Similar 6800-series interface, dummy read also required before first actual display data read. Serial interface serial interface consists serial clock SCK, serial data SDA, D/C, CS2. shifted into 8-bit shift register every rising edge order D6,. sampled every eighth clock data byte shift register written Display Data command register same clock.
R/W(WR)
E(RD)
data
write column address dummy read
data read1
data read
data read
Figure display data read with insertion dummy read
Graphic Display Data (GDDRAM) GDDRAM mapped static holding pattern displayed. size 6900 bits. columns reserved future use. Only columns mapped segment outputs. Figure description GDDRAM address map. mechanical flexibility, re-mapping
both Segment Common outputs provided. vertical scrolling display, internal initial line register control portion data mapped display. Figure shows case which initial line register 38H. display data will written when column address less than set.
MC141598 08/98
Column address
Column address
Page Page Page Page Page Page Page Page Page (LSB) SEG99 (SEG0) SEG0 (SEG99)
COM8 (COM23)
COM31 (COM0)
COM0 (COM31)
COM7 (COM24) COM33
Note:
configuration parentheses represent non-remapping Rows Columns used
Figure Graphic Display Data (GDDRAM) Address (with vertical scroll value 38H) Graphic Display Mode
MC141598 08/98
Column address
Column address
Page Page Page Page Page Page Page Page
COM8 (COM23)
COM31 (COM0)
COM0 (COM31)
COM7 (COM24) COM32/SEG99
Page (LSB) SEG98 (SEG0) configuration parentheses represent non-remapping Rows Columns COM32/SEG99 will always display COM32 will remapped remapping mode used (SEG98) SEG0
COM33
Note:
Figure Graphic Display Data (GDDRAM) Address (with vertical scroll value 38H) Pseudo Graphic Display Mode
MC141598 08/98
Column address
Column address
Page Page Page Page Page (D0) Page Page Page Page Page (D0) Page 8(LSB) SEG98 (SEG0) Note: configuration parentheses represent non-remapping Rows Columns used (SEG98) SEG0
COM9 (COM23)
COM32 (COM0)
COM0 (COM32)
COM7 (COM25) COM8 (COM24) COM33
Figure Graphic Display Data (GDDRAM) Address (with vertical scroll value 38H) Graphic Display Mode
MC141598 08/98
Column address
Column address
Page Page Page (D0) Page Page Page (D0) Page Page Page (D0) Page Page Page (D0) Page (LSB) SEG98 (SEG0) Note: configuration parentheses represent non-remapping Rows Columns used (SEG98) SEG0
COM9 (COM23)
COM24 (COM8) COM25 (COM7) COM26 (COM6)
COM32 (COM0)
COM0 (COM32)
COM7 (COM25) COM8 (COM24) COM33
Figure Graphic Display Data (GDDRAM) Address (with vertical scroll value 38H) Chinese Character Display mode
MC141598 08/98
Oscillator Circuit This module chip power oscillator circuitry (Figure oscillator generates clock DC-DC voltage converter. This clock also used Display Timing Generator.
Oscillator enable enable Oscillation Circuit enable Buffer
OSC1 Internal pwell resistor
OSC2
Figure Oscillator Circuitry
Driving Voltage Generator Regulator This module generates voltage needed display output. takes single supply input generate necessary bias voltages. consists DC-DC voltage converter Please refer application notes. Voltage Regulator (Voltages referenced VDD) Feedback gain control initial voltage. External resistors connected between between VL6. These resistors chosen give desired according following equation: Ry/Rx)Vref where Vref internally generated reference voltage Vref 2.55V; resistance values resistors between VL6, respectively. Smart Bias Divider Divide regulator output give driving voltages (VL2 VL5). This power consumption circuit which saves most display current. Contrast Control (Voltages referenced VDD) Software control voltage levels voltage. Internal current Iref flowing from through external resistors. gives following equation: Ry/Rx)Vref Ry*Iref where Iref 6.5uA depending 5-bit data contrast control command. Bias Ratio Selection circuitry Software control bias ratio match characteristic panel. Self adjust temperature compensation circuitry Provide different compensation grade selections satisfy various liquid crystal temperature grades. grading selected software control. Defaulted temperature coefficient (TC) value -0.2%/oC.
Latch register carries display signal information. display mode, first bits Common driving signals other bits Segment driving signals. display mode, first bits Common driving signals other bits Segment driving signals. Data will HV-buffer Cell level-shifted required level. Level Selector Level Selector control display synchronization. Display voltage separated into sets used with different cycles. Synchronization important since selects required voltage level Buffer Cell, which turn outputs waveform. Buffer Cell (Level Shifter) Buffer Cell works level shifter which translates voltage output signal required driving voltage. output shifted with internal clock which comes from Display Timing Generator. voltage levels given level selector which synchronized with internal signal. Reset Circuit When input low, chip initialized with following status: Display 100X33 Display Display Mode Normal segment display data column address mapping (SEG0 mapped address 10H) Read-modify-write mode Power control register zero Shift register data clear serial interface Bias ratio Static indicator Vertical scroll value register Column address counter Page address Normal scan direction outputs Contrast control register zero Test mode Temperature Coefficient PTC2. Smart Icon Mode disabled. Voltage Booster OFF.
MC141598 08/98
Panel Driving Waveform
following example Common Segment drivers connected panel. waveforms shown Figure illustrate desired multiplex scheme.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4
Figure Display Example
TIME SLOT
COM0
COM1
SEG0
SEG1
Note Display Mode Psuedo 99x34 Graphic Display Mode, instead
Figure Driving Signal from MC141598 (Waveform
MC141598 08/98
Command Description
Display Mode This command switches defaulted display mode will function either COM32 display mode SEG99 respectively. Display On/Off This command alternatively turns display off. When display issued with entire display power save mode will entered. "Set Power Save Mode" details. Page Address This command positions page address possible positions GDDRAM. Refer figure Column Address Higher Nibble This command specifies higher nibble 8-bit column address display data ram. column address will incremented each data access after pre-set Column Address Lower Nibble This command specifies higher nibble 8-bit column address display data RAM. Read Status register This command issued setting during data read (refer figure parallel interface waveform). allows monitor internal status chip. status read provided serial mode. Segment Re-map This commands changes mapping between display data column address segment driver. allows flexibility layout during module assembly. Refer figure Normal/Reverse Display This command sets display either normal/reverse. normal display, data indicates "ON" pixel while reverse display, data indicates "ON" pixel. icon mode, icon line reversed this command. Entire Display On/Off This command forces entire display, including icon row, regardless contents display data RAM. This command priority over normal/reverse display. This command will used with display ON/OFF form compound command entering power save mode. "Set Power Save Mode". Bias This command selects suitable bias ratio required driving particular panel use. Read-Modify-Write Mode This command puts chip read-modify-write mode which: column address saved before entering mode column address incremented display data write display data read Read-Modify-Write Mode This command relieves chip from read-modify-write mode. column address that saved before entering read-modify-write mode will restored. Software Reset This command causes some internal status chip initialized: Static indicator Vertical scroll register Column address counter Page address Normal scan direction outputs Contrast control register zero Test mode Output Scan Direction This command sets scan direction output allowing layout flexibility module assembly. Psuedo only COM0 COM31 remapped. graphic Chinese Character display mode, COM0 COM32 will remapped. COM33 will affected this command. Refer figure Power Control Register This command turns on/off various power circuits associated with chip. Contrast Control Register This commands adjusts contrast panel changing drive voltage provided on-chip power circuits. with steps with 5-bit contrast control register. Indicator On/Off This command turns static drive indicators. also controls whether standby mode sleep mode will entered after power save compound command Power Save Mode This compound command display ON/OFF entire display ON/OFF. When entire display issued during display OFF, either standby mode sleep mode will entered, depending status static indicator. static indicators off, command sleeps system: Internal oscillator power supply circuits stopped Segment Common drivers output level display data operation mode before sleep held Internal display still accessed static indicators chip enters standby mode which similar sleep mode except: internal oscillator static drive system Note also that software reset command issued during standby mode, sleep mode will set. Both power save modes exited issue command RES. Test Mode This command allows test mode entered internal testing chip. use. Temperature Coefficient This command different temperature coefficients order match various liquid crystal temperature grades. Master Clear GDDRAM This command MASTER clear GDDRAM. internal data page page 9-12 will Zero after command issued.
MC141598 08/98
6-Phase Smart-Icon Mode This command 4-Phase 6-Phase smart icon modes which lower higher panel. Refer Smart Icon Mode Output Description detail. Smart Icon Mode ON/OFF This command switch on/off low-current Icon Display Mode. voltage booster ON/OFF This command switch on/off voltage booster. capacitor used connect between when state While state OFF, functions VL6. Vertical Scroll Value Range Register This command select Vertical Scroll Value Range Register next command Vertical Scroll Register. When Vertical Scroll Value Range Register vertical scroll value will selected from 0-63 next command. When Vertical Scroll Value Range Register vertical scroll value will selected from 65-68 next command. Remark: Vertical Scroll Register dummy value used. Vertical Scroll Register This command used scroll screen vertically selecting scroll value from With scroll value equals Page mapped COM0. With scroll value equals Page0 mapped COM0. vertical scroll values assigned Page while vertical scroll value assigned Page respectively. COM33 affected this command. Refer figure Remark: Vertical Scroll Register dummy value used.
MC141598 08/98
COMMAND TABLE
Pattern 1010111X0 1011X3X2X1X0 0001X3X2X1X0 Command Display On/Off Page Address Higher Column Address Comment X0=0: turns panel (POR) X0=1:turns panel GDDRAM Page Address using X3X2X1X0 address bits. higher nibble colume address register using X4X3X2X1X0 data bits. initial display line register reset 0000 during POR. lower nibble colume address register using X4X3X2X1X0 data bits. initial display line register reset 0000 during POR. X7=0: indicates internal operation completed. X7=1: indicates internal operation progress. X6=0: indicates normal segment mapping with column address X6=1: indicates reverse segment mapping with column address X5=0: indicates display X5=1: indicates display X4=0: initialization progress X4=1: initialization progress after software reset X0=0: column address mapped SEG0 (POR) X0=1: column address mapped SEG0 Refer Fig. X0=0: normal display (POR) X0=1: reverse display X0=0: normal display (POR) X0=1: entire display X0=0: bias (POR) X0=1: bias Read-modify-write mode will entered which column address will incremented during display data read Exit Read-modify-write mode. Column address before entering mode will restored Initialize internal status X3=0: normal mode (POR) X3=1: remapped mode. COM0-31 becomes COM31-0 100x33 99x34 with dummy COM32; COM0-32 becomes COM32-0 99x34 graphic Chinese Character mode. X0=0:turns output op-amp buffer (POR) X0=1:turns output op-amp buffer X1=0:turns internal regulator (POR) X1=1:turns internal regulator X2=0:turns internal voltage booster (POR) X2=1:turns internal voltage booster available values internal contrrast register using X4X3X2X1X0 data bits. contrast register reset 00000 during POR.
0000X3X2X1X0
Lower Column Address
X7X6X5X40000 (read data) Read Status Register
1010000X0
Segment Re-map
1010011X0 1010010X0 1010001X0 11100000 11101110 11100010 1100X3***
Normal/Reverse Display Entire Display On/Off Bias Read-Modify-Write Mode Read-Modify-Write Mode Software Reset Scan Direction Output
00101X2X1X0
Power Control Register
100X4X3X2X1X0
Contrast Control Register
MC141598 08/98
COMMAND TABLE
1010110X0 ******** 1111**** 110101X1X0 Indicator On/Off Power Save Mode Test Mode Display Mode X0=0: indicator (POR) X0=1: indicator Standby sleep mode will entered with compound commands test command. X1X0 Select Graphic Display Mode (POR) X1X0 Select Pseudo Graphic Display Mode X1X0 Select Graphic Display Mode X1X0 Select Chinese Character Display Mode X1X0 Select PTC0 X1X0 Select PTC1 X1X0 Select PTC2 (POR) X1X0 Select PTC3 Master Clear entire GDDRAM page page 9-12. X0=0; Select 6-Phase Smart Icon Mode X0=1; Select 4-Phase Smart Icon Mode (POR) X0=0; Switch Smart Icon Mode (POR) X0=1; Switch Smart Icon Mode X0=0; Switch Voltage Booster (POR) X0=1; Switch Voltage Booster
001000X1X0
Temperature Coefficient
11011100 1101001X0 1101000X0 1101111X0 1101100X0 01X5X4X3X2X1X0
Master Clear GDDRAM 4-/6-Phase Smart Icon Mode Smart Icon Mode ON/OFF Voltage Booster ON/OFF
Vertical Scroll Value Range Regis- X0=0; when Vertical Scroll Register falls within (POR) X0=1; when Vertical Scroll Register falls within Vertical Scroll Register vertical scroll value from 0-63 using 01X5X4X3X2X1X0 when Vertical Scroll Value Range Register vertical scroll value from 65-68 using 010000X1X0 when Vertical Scroll Value Range Register to1. Vertical Scroll Register reset 01000000 during POR.
MC141598 08/98
Data Read Write
read data from GDDRAM, input High R/W(WR) 6800-series parallel mode, E(RD) High 8080-series parallel mode. data read provided serial mode. normal mode, GDDRAM column address pointer will increased automatically after each data read. However, automatic increase will performed read-modify-write mode. Also, dummy read required before first data read. Figure Functional Description. write data GDDRAM, input R/W(WR) High 6800-series parallel mode. serial interface, will always write mode. GDDRAM column address pointer will increased automatically after each data write.
Address Increment Table (Automatic)
R/W(WR) Comment Write Command Read Status Write Data Read Data Address Increment Remarks
Address Increment done automatically after data read write. column address pointer GDDRAM*2 affected. Remarks: read data issued read-modify-write mode, address increase applied. Column Address will wrap round when overflow.
Commands Required R/W(WR) Actions
R/W(WR) Actions RAMs Read/Write Data from/to GDDRAM. Commands Required GDDRAM Page Address GDDRAM Column Address Read/Write Data Save/Restore GDDRAM Column Address. (1011X3X2X1X0)* (0001X3X2X1X0)* (0000X3X2X1X0) (X7X6X5X4X3X2X1X0)
Save GDDRAM Column Address read-modify(11100000) write mode Restore GDDRAM Column Address read- (11101110) modify-write mode
need resend command again previously. read write action Display Data does depend display mode. This means user change content whether target content being displayed not.
MC141598 08/98
Display Output Description Display Mode Figure example output pattern Display Mode panel. Figure data GDDRAM output pattern display with different command enabled.
COM0
Content GDDRAM PAGE PAGE PAGE PAGE COM31 COM33 SEG0 SEG99 PAGE Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble 0001110000-0000111000
Column Address
Column Address
Figure
Figure
Icon Line Column remap disable re-map enable Column remap enable re-map enable Column remap disable re-map disable
Figure Examples display with different command enabled
MC141598 08/98
Display Output Description Pseudo Graphic Display Mode Figure example output pattern Display Mode panel. Figure data GDDRAM output pattern display with different command enabled.
COM0
Content GDDRAM PAGE PAGE PAGE PAGE PAGE Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble 0001110000-0000111000
COM31 COM32 COM33 SEG0 SEG98
Column Address
Column Address
Figure
Figure
Icon Line Column remap disable re-map enable Column remap enable re-map enable Column remap disable re-map disable
Figure Examples display with different command enabled
MC141598 08/98
Display Output Description Graphic Display Mode Figure example output pattern Display Mode panel. Figure data GDDRAM output pattern display with different command enabled.
COM0 Content GDDRAM PAGE PAGE PAGE PAGE Page PAGE SEG0 SEG98 Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble Upper Nibble Lower Nibble 0000111000-0000001100 0001110000-0000111000
COM32 COM33
Column Address
Column Address
Figure
Figure
Icon Line Column remap disable re-map enable Column remap enable re-map enable Column remap disable re-map disable
Figure Examples display with different command enabled
MC141598 08/98
Display Output Description Chinese Character Display Mode Figure example output pattern Display Mode panel. Figure data GDDRAM output pattern display with different command enabled.
COM0 Content GDDRAM PAGE PAGE PAGE PAGE PAGE COM32 COM33 SEG0 SEG98 PAGE Upper Nibble Lower Nibble Upper Nibble Lower Nibble 0000000000-0000000000
Upper Nibble Lower Nibble Upper Nibble Lower Nibble 0001110000-0000111000
Column Address
Column Address
Figure
Figure
Spacing Line
Icon Line Column remap disable re-map enable Column remap enable re-map enable Column remap disable re-map disable
Figure 10c. Examples display with different command enabled
MC141598 08/98
Smart Icon Mode Output Description There driving schemes Smart Icon Mode panel with different Von/Voff VDD: Phase Smart Icon: Voff sqrt (1/4) sqrt (3/4) Phase Smart Icon: Voff sqrt (1/6) sqrt (3/6)
(non icon) COM33(icon) SEG(on) SEG(off)
DVDD DVSS DVDD DVSS DVDD DVSS DVDD DVSS
Figure 11a. Driving Signal Phase Smart Icon Mode
DVDD
(non icon) COM33(icon) SEG(on) SEG(off)
DVSS DVDD DVSS DVDD DVSS DVDD DVSS
Figure 11b. Driving Signal Phase Smart Icon Mode
MC141598 08/98
Application Circuit:
External Power Supply
COM0 COM32
MC141598
Panel
SEG0 SEG99
Remark should known state. R/W(WR), D/C, D0-D2 D5-D6 open serial mode.
MC141598 08/98
Internal Analog Circuitry enabled DC-DC converter mode
COM0 COM32
MC141598
Panel
SEG0 SEG99
Remark 4.7uF; 0.22 0.47uF.
MC141598 08/98
Internal Analog Circuitry enabled DC-DC converter mode
COM0 COM32
MC141598
Panel
SEG0 SEG99
Remark 4.7uF; 0.22 0.47uF.
MC141598 08/98
Internal Analog Circuitry enabled DC-DC converter mode
COM0 COM32
MC141598
Panel
SEG0 SEG99
Remark 4.7uF; 0.22 0.47uF.
MC141598 08/98
Internal Analog Circuitry enabled DC-DC converter mode
COM0 COM32
MC141598
Panel
SEG0 SEG99
Remark 4.7uF; 0.22 0.47uF. should left open. shorted left open.
MC141598 08/98
PACKAGE DIMENSIONS MC141598T PACKAGE DIMENSION Reference: 98ASL10034A, Issue released 13-May-98
Copper Side
MC141598 08/98
PACKAGE DIMENSIONS MC141598T PACKAGE DIMENSION Reference: 98ASL10034A, Issue released 13-May-98
MC141598 08/98
PACKAGE DIMENSIONS MC141598T1 PACKAGE DIMENSION Reference: 98ASL10036A, Issue released 19-May-98
Copper Side
MC141598 08/98
PACKAGE DIMENSIONS MC141598T1 PACKAGE DIMENSION Reference: 98ASL10036A, Issue released 19-May-98
MC141598 08/98
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others.Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure unintended unauthorized application, Buyer shall indemnify hold Motorola offices, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Literature Distribution Centres: USA: Motorola Literature Distribution; P.O. 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; Europe Literature Centre; Tanners Drive, Blakelands Milton Keynes, 145BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo Japan. ASIA-PACIFIC: Motorola Semiconductor H.K. Ltd.; Silicon Harbour Center, King Street, Industrial Estate, N.T., Hong Kong.
MC141598
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