MC141537 CMOS Driver which consists annunciator outputs high voltage d
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Segment Common Driver with Controller
MC141537 CMOS Driver which consists annunciator outputs high voltage driving signals common segment). parallel interface capability operating with general MCU. Besides general driver features, chip bias voltage generator circuit such that limited external component required during application. Single Supply Operation, Operating Temperature Range -30°C 85°C Current Stand-by Mode (<500nA) Chip Bias Voltage Generator Parallel Interface Graphic Mode Operation Chip byte Graphic Display Data Master clear Segment Drivers, Common Drivers 1/16 multiplex ratio bias ratio Re-mapping Column Drivers Three stand alone Annunciator driver circuits Selectable Drive Voltage Temperature Coefficients level Internal Contrast Control External Contrast Control Available Bare Form
MC141537
MC141537 Bare
ORDERING INFORMATION MCC141537 Bare
2/98
MC141537 3-98
BLOCK DIAGRAM
Annun0 Annun2
Com0 Com15
Seg0~Seg119
Annunciator Control Circuit
Buffer Cell Level Shifter
Level Selector VLL6 VLL2
Latch OSC1 OSC2 Display Timing Generator
Latch
Driving Voltage Generator Tripler, Doubler, Voltage Regulator, Voltage Divider Constrast Control, Temperature Compensation
GDDRAM Bits
CAVDD AVSS
Command Decoder DVSS DVDD Command Interface
Parallel Interface
D0~D7
MC141537 3-99
This page intented leave blank
MC141537 3-100
MCC141537 ASSIGNMENT
Refer MC141537 Coordinate Name Assignment
MC141537 3-101
MAXIMUM RATINGS* (Voltages Referenced VSS, TA=25°C)
Symbol AVDD,DVDD Tstg Input Voltage Current Drain Excluding Operating Temperature Using Internal Oscillator Using External Oscillator Storage Temperature Range Supply Voltage Parameter Value -0.3 +4.0 VSS-0.3 VSS+10.5 VSS-0.3 VDD+0.3 +150 Unit
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted limits Electrical Characteristics tables Description section. AVSS DVSS (DVSS =VSS Digital circuit, AVSS Analogue Circuit) AVDD DVDD (DVDD =VDDof Digital circuit, AVDD Analogue Circuit)
This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that Vout constrained range (Vin Vout) VDD. Reliability operation enhanced unused input connected appropriate logic voltage level (e.g., either VDD). Unused outputs must left open. This device light sensitive. Caution should taken avoid exposure this device light source during normal operation. This device radiation protected.
ELECTRICAL CHARACTERISTICS (Voltage Referenced VSS, VDD=2.4 3.5V, TA=25°C)
Symbol DVDD AVDD Parameter Logic Circuit Supply Voltage Range Voltage Generator Circuit Supply Voltage Range Access Mode Supply Current Drain (AVDD DVDD Pins) Test Condition (Absolute value referenced VSS) VDD=3.0V, Internal DC/DC Converter Tripler Enabled, Annunciator On/Off, accessing, Tcyc=1MHz, Osc. Freq.=38.4KHz, Display VDD=3.0V, Internal DC/DC Converter Tripler Enabled, Annunciator On/OFF, halt, Osc. Freq.=38.4KHz, Display VDD=3.0V, Internal DC/DC Converter Tripler Enabled, Annunciator On/OFF, halt, Osc. Freq.=38.4KHz, Display VDD=3.0V, Display off, Oscillator Disabled, halt. VDD=3.0V, External Oscillator, Oscillator Enabled, Display Off, halt, Osc. Freq.=38.4KHz. VDD=3.0V, Internal Oscillator, Oscillator Enabled, Display Off, halt, Osc. Freq.=38.4KHz. Display Internal DC/DC Converter Enabled, Tripler Enabled, Osc. Freq.=38.4KHz, Regulator Enabled, Divider Enabled. Display Internal DC/DC Converter Enabled, Doubler Enabled, Osc. Freq.=38.4KHz, Regulator Enabled, Divider Enabled. Internal DC/DC Converter Disabled. Iout=100µA Iout=100µA Unit
AIDP
Display Mode Supply Current Drain (AVDD Pin)
DIDP
Display Mode Supply Current Drain (DVDD Pin)
ISB1
Standby Mode Supply Current Drain (AVDD DVDD Pins) Standby Mode Supply Current Drain (AVDD DVDD Pins) Standby Mode Supply Current Drain (AVDD DVDD Pins) Driving Voltage Generator Output (VCC Pin)
ISB2
ISB3 VCC1
3*AVDD
10.5
VCC2
Driving Voltage Generator Output (VCC Pin)
2*AVDD
VLCD VOH1
Driving Voltage Input (VCC Pin) Output High Voltage (D0-D7, Annun0-2, OSC2) Output Voltage (D0-D7, Annun0-2, OSC2) Driving Voltage Source Pin)
AVDD 0.9*VDD
10.5
VOL1
0.1*VDD
Regulator Enabled voltage depends Int/Ext Contrast Control Regulator Disable.
Driving Voltage Source Pin)
Floating
MC141537 3-102
ELECTRICAL CHARACTERISTICS (Voltage Referenced VSS, VDD=2.4 3.5V, TA=25°C)
Symbol VIH1 Parameter Input high voltage (RES, OSC2, D0-D7, R/W, D/C, OSC1) Input voltage (RES, OSC2, D0-D7, R/W, D/C, OSC1) Display Voltage Output (VLL6, VLL5, VLL4, VLL3, VLL2 Pins) Voltage Divider Enabled Test Condition 0.8*VDD Unit
VIL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL6 VLL5 VLL4 VLL3 VLL2
Vout=VDD-0.4V Vout=0.4V
0.8*VR 0.6*VR 0.4*VR 0.2*VR
0.2*VDD
Display Voltage Input (VLL6, VLL5, VLL4, VLL3, VLL2 Pins)
External Voltage Generator, Voltage Divider Disable
Output High Current Source (D0-D7, Annun0-2, OSC2) Output Current Drain (D0-D7, Annun0-2, OSC2) Output Tri-state Current Drain Source (D0-D7, OSC2) Input Current (RES, OSC2, D0-D7, R/W, OSC1) Channel resistance between driving signalpins (SEG COM) driving voltage input pins (VLL2 VLL6) Memory Retention Voltage (DVDD) Input Capacitance (OSC1, OSC2, logic pins) Temperature Coefficient Compensation* Flat Temperature Coefficient Temperature Coefficient Temperature Coefficient Temperature Coefficient Internal Contrast Control Output Voltage)
IIL/IIH
During Display 0.1V apply between terminals, within operating voltage range Standby mode, retain internal configuration data
PTC0 PTC1 PTC2 PTC3
TC1=0, TC2=0, Voltage Regulator Disabled TC1=0, TC2=1, Voltage Regulator Enabled TC1=1, TC2=0, Voltage Regulator Enabled TC1=1, TC2=1, Voltage Regulator Enabled Regulator Enabled, Internal Contrast control Enabled. Voltage Levels Controlled Software. Each level typically 2.25% Regulator Output Voltage.
-0.18 -0.22 -0.35
*The formula temperature coefficient (TC) TC(%)= 50°C 50°C 25°C X100%
MC141537 3-103
ELECTRICAL CHARACTERISTICS (TA=25°C, Voltage referenced VSS, AVDD=DVDD=3V)
Symbol FOSC Parameter Oscillation Frequency Display timing generator Test Condition 60Hz Frame Frequency Either External Clock Input Internal Oscillator Enabled duty cycle Annunciator Fosc=38.4KHz Graphic Display Mode, Timing generator freq. within specification Internal Oscillator Enabled, within operation range 38.4 Unit
FANN FFRM
Backplane Frequency Annunciator (Annun0-2, Frame Frequency Internal Oscillation Frequency with different value feedback resistor
Figure relationship
Note: FFRM=FOSC/640 FANN=FOSC/1280
280k 260k Oscillation Frequency (Hz) 100k 500k 1.0M 1.5M 2.0M Resistor Value between OSC1 OSC2
Figure Internal Oscillator Frequency Relationship with External Resistance
MC141537 3-104
TABLE Parallel Timing Characteristics (Write Cycle) (TA=-30 85°C, DVDD=2.4 3.5V, VSS=0)
Symbol tcycle Enable Cycle Time Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Parameter 1000 Unit
tcycle
D0-D7 Valid Data
Figure Parallel Timing Characteristics (Write Cycle)
MC141537 3-105
TABLE Parallel Timing Characteristics (Read Cycle) (TA=-30 85°C, DVDD=2.4 3.5V, VSS=0)
Symbol tcycle Enable Cycle Time Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Parameter 1000 Unit
tcycle
D0-D7 Valid Data
Figure Parallel Timing Characteristics (Read Cycle)
MC141537 3-106
DESCRIPTIONS
(Data Command) This input tell driver input D0-D7 data command. Input High data while input command. (CLK) (Input Clock) This normal clock input. Input D0-D7 latched falling edge (Reset) active pulse this reset internal status driver (same power reset). minimum pulse width D0-D7 This bi-directional used data command transferring. (Read/Write) This input pin. read display data internal status (Busy Idle), pull this High. input indicates write operation display data internal setup registers. OSC1 (Oscillator Input) internal oscillator mode, this input internal power oscillator circuit. this mode, external resistor certain value placed between OSC1 OSC2 pins range internal operating frequencies (refer Figure external oscillator mode, OSC1 should left open. OSC2 (Oscillator Output External Oscillator Input) This output internal power oscillator circuit. external oscillator mode, OSC2 will input external clock external resistor needed. VLL6 VLL2 Group voltage level pins driving panel. They either connected external driving circuit external bias supply connected internally built-in divider circuit. internal Voltage Divider enabled, capacitor AVSS required each pin. Internal DC/DC Converter enabled, capacitor required connect these pins. Internal DC/DC Converter enable with Tripler enable, capacitor required connect between these pins. Otherwise, should left open. internal divider circuit enabled, capacitor required connect between these pins. This feedback path gain control (external contrast control) VLL1 VLL6. adjusting driving voltage, requires feedback resistor placed between gain control resistor placed between AVSS, capacitor placed between AVSS. (Refer Application Circuit Section) COM0-COM15 (Row Drivers) These pins provide driving signal panel. They output during display off. SEG0-SEG119 (Column Drivers) These pins provide column driving signal panel. They output during display off. (Annunciator Backplane) This combines with Annun0-Annun2 pins form annunciator driving part. When annunciator circuit enabled, will output square wave FANN outputs when oscillator disabled. Annun0 Annun2 (Annunciator Frontplanes) These pins three independent annunciator driving outputs. enabled annunciator outputs from corresponding FANN square wave which degrees phase with Disabled annunciator output from corresponding square wave inphase with When oscillator disabled, these pins output AVDD AVSS AVDD positive supply bias voltage generator. AVSS ground. using Internal DC/DC Converter, capacitor from this AVSS required. also external bias input Internal DC/DC Converter used. Positive power supplied Driving Level Selector Buffer Cell with this pin. Normally, this intended power supply other component. DVDD DVSS Power supplied digital control circuit driver using these pins. DVDD power DVSS ground.
MC141537 3-107
OPERATION LIQUID CRYSTAL DISPLAY DRIVER
Description Block Diagram Module
Command Decoder Command Interface This module determines whether input data interpreted data command. Data directed this module based upon operating mode part status line. High, data written Graphic Display Data (GDDRAM). indicates that data interpreted Command. Reset same function Power Reset (POR). Once received pulse, internal circuitry will reset initial status. Refer Command description section more information. Parallel Interface parallel interface consists bi-directional data lines (D0-D7) plus line High indicates read Graphic Display Data (GDDRAM). line indicates write Display Data Internal Command Registers depending status line. line serves data latch signal (clock). Refer operation conditions characteristics section Parallel Interface Timing Description. Graphic Display Data (GDDRAM) GDDRAM mapped static that holds pattern displayed graphic display mode. size determined number times number column drivers (120x16 1920 bits). Figure description GDDRAM address map. mechanical feasibility, re-mapping both Segment Common outputs provided.
Column address column address 77H)
Column address column address 00H) Com0 (com15) Seg119 Note configuration parentheses represent remapping Commons Columns Com15 (com0)
Row0
Page
Page Row15 Seg0
Figure Graphic Display Data Address
MC141537 3-108
Display Timing Generator part chip power oscillator circuitry (figure oscillator frequency selected external resistor range kHz. circuitry enabled with software control. external clock application, feed clock into OSC2 leave OSC1 open.
Annunciator Control Circuit waveform Annunciators generated this block. independent annunciators enabled software command. Annunciator also controlled oscillator circuit. Oscillator must enabled before selecting annunciator Annunciator display waveform shown Figure
Oscillator
Oscillator enable
Oscillation Circuit MC141537 OSC1 OSC2 External component
Feedback internal oscillator external input
Figure Oscillator Circuitry
DVDD DVSS DVDD ANNUN0 DVSS DVDD ANNUN1 ANNUN2 DVSS DVDD DVSS Disable Enable Enable Enable Enable Enable Disable
Annunciator Annunciator Annunciator
Figure Annunciators display waveform
MC141537 3-109
Drive Voltage Generator This module generates voltages needed display output. This section should take single supply input generate necessary bias voltage. consists Voltage Doubler Voltage Tripler generate voltage. Doubler used panel which needs lower driving voltage less power consumption. Tripler used panel which needs higher driving voltage. Voltage Regulator Feedback gain control initial display voltage. also external contrast control. Voltage Divider Divide display voltage (VLL2-VLL6) from regulator output. This power consumption circuit which consumes very little ILCD current compare with traditional resistor ladder method. Self adjust temperature compensation circuitry Provide different compensation grade selections satisfy various liquid crystal temperature grades. This temperature coefficients selected software control. Contrast Control Block Software control voltage levels display voltage. blocks individually turned external voltage generator provided.
Latch Latch long register which carries display signal information. First bits Common driving signals other bits Segment driving signals. Data will input Level Shifter bumping required level. Level Selector Level selector control display synchronization. Display voltage separated into sets used with different cycle. Synchronization important since selects required voltage level Buffer Cell output signal voltage pump. Buffer Cell (Level Shifter) buffer cell works level shifter which translates voltage output signal required driving voltage. output shifted with internal clock which comes from Display Timing Generator. voltage levels determined level selector which synchronized with internal signal.
Panel Driving Waveform
This example Common Segment drivers connected panel. waveform shown figure illustrates desired multiplex scheme.
Com0 Com1 Com2 Com3 Com4 Com5 Com6 Com7
Figure Display Waveform
Seg0 Seg1 Seg2 Seg3 Seg4
MC141537 3-110
TIME SLOT
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
Figure Driving Signal from MC141537
MC141537 3-111
TIME SLOT
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Seg0-Com0 "OFF" Pixel
Seg0-Com1 "ON" Pixel
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Seg2-Com2 "OFF" Pixel
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Seg3-Com2 "ON" Pixel
VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6
Figure Effective waveform pixel
MC141537 3-112
Command Description
Display On/Off (Display Mode Stand-by mode) Display command controls selecting output voltage effect annunciator drivers. Display command causes conversion data GDDRAM necessary waveforms Common Segment driver outputs. enables on-chip bias generator. (Note "Set Oscillator command should issued before "display on") Display Command turns display state driver follow during display off: Common Segment driver outputs fixed VLL1 (VSS). bias voltage generator turned off. content registers retained. will accept commands data. Annunciators affected this command. Oscillator affected this command. GDDRAM Column Address This command positions address pointer column boundary. address location 00H-77H (120 columns). column address will increased automatically after read write operation. Refer figure "Address Increment Table" command "Set GDDRAM Page Address" further information. GDDRAM Page Address This command positions address pointer possible positions GDDRAM. Refer figure Master Clear GDDRAM This command MASTER clear GDDRAM. internal data will Zero after command issued. clear action will taken dummy Write follows "Clear GDDRAM" command. Vertical Scroll Value When display turned this command maps selected GDDRAM (00H-0FH) Com0-Com15. With scroll value equal GDDRAM mapped Com0 through mapped Com1 through Com15 respectively. With scroll value equal GDDRAM mapped Com0, then through will mapped Com1 through Com14 respectively will mapped Com15. Save Restore Column Address With option Save Restore Column Address command saves copy Column Address GDDRAM. With option this instruction restores copy obtained from previous execution saving column address. This instruction very useful writing idle graphics characters that larger than pixels vertically. Column Mapping This instruction selects mapping GDDRAM Segment Drivers mechanically flexibility. There selected mappings: Column Column GDDRAM mapped Seg0 Seg119 respectively; Column Column GDDRAM mapped Seg119 Seg0 respectively. section "Display Output Description Example" related information. Mapping This instruction selects mapping GDDRAM Common Drivers mechanical flexibility. There selected mappings:
GDDRAM Common Common respectively; GDDRAM Common Common respectively. section "Display Output Description" related information. Annunciator Control Signals This command used control active states stand alone annunciator drivers. Oscillator Enable Disable This command used either turn Oscillator. either internal external oscillator, this command should executed. This command affected command Display On/Off" "Annunciator On/Off". command "Ext/Int Oscillator" more information. External Internal Oscillator This command used select either internal external oscillator. When internal oscillator being selected, feedback resistor between OSC1 OSC2 needed. External oscillation circuit, clock should input OSC2. OSC1 should left open. Internal DC/DC Converter On/Off This command selects Internal DC/DC Converter generate from AVDD. Disable Internal DC/DC Converter external provided. Voltage Doubler Tripler This command selects Voltage Doubler Tripler when Internal DC/DC Converter enabled. Internal Regulator On/Off With different option values, this command either enables disables regulator which consists internal contrast control temperature compensation circuits. Internal Voltage Divider On/Off Internal Voltage Divider enabled, external power supply should applied VLL6- VLL2. divider enabled, internal circuit will automatically generate bias level driving voltage. Internal Contrast Control On/Off This command used turn internal control delta voltage between bias voltages. option software selected delta bias voltage control enabled. option external contrast control through external resistor enabled. Note: software contrast control external feedback contrast controls cannot both enabled same time. Contrast Level This command select contrast levels when internal contrast control circuitry use. After power-on reset, contrast level lowest. Increase Decrease Contrast Level internal contrast control enabled, this command used increase decrease contrast level within contrast levels. constrast level starts from lowest value after POR. Temperature Coefficient This instruction selects different drive voltage temperature coefficients allowing various liquid crystal temperature grades. These temperature coefficients specified Electrical Characteristics Tables.
MC141537 3-113
COMMAND TABLE
Pattern 0000000X0 Command GDDRAM Page Address Comment GDDRAM Page Address using address bit. X0=0: page 1(POR) x0=1: page Enable Internal Contrast Value using X3X2X1X0 data bits. Reset 0000 during POR. X0=0: tripler enabled (POR) X0=1: doubler enabled X0=0 Col0 Seg0 (POR) X0=1 Col0 Seg119 X0=0 Row0 Com0 (POR) X0=1: Row0 Com15 X0=0: display (POR) X0=1: display X0=0: disable generator(POR) X0=1: enable generator X0=0: disable regulator (POR) X0=1: enable regulator When application uses supply with built-in temperature compensation, regulator should disabled X0=0: disable voltage divider (POR) X0=1: enable voltage divider When external bias network used, voltage divider should disabled. X0=0: disable constrast control (POR) X0=1: enable constrast control Internal contrast circuits should disabled external contrast circuits used.
0001X3X2X1X0 0010000X0 0010001X0 0010010X0 0010011X0 0010100X0 0010101X0 0010110X0
Contrast Level Voltage Tripler Doubler Colum Mapping Mapping Reserved Expansion Display On/Off Internal DC/DC Converter Enable Internal Regulator On/Off
0010111X0
Internal Voltage Divider On/Off
0011000X0
Internal Contrast Control On/Off
0011001X0 0011010X0 00110110 0011100X0 0011101X0
Reserved Expansion Save/Restore GDDRAM Column Address Master Clear GDDRAM Reserved Expansion Reserved X0=0: normal operation (POR) X0=1: test mode (Note: sure X0=0 during application) X0=0 restore address X0=1 save address Master Clear GDDRAM
001111X1X0 0100X3X2X1X0 01100A1A0X0
Reserved Expansion Vertical Scroll Value Annunciator Control Signals X3X2X1X0 scroll amount. Scroll value upon A1A0=00: select annunciator 0(POR) A1A0=01: select annunciator A1A0=10: select annunciator X0=0: turn selected annunciator (POR) X0=1: turn selected annunciator X1X0=00: 0.00% (POR) X1X0=01: -0.18% X1X0=10: -0.22% X1X0=11: -0.35%
011010X1X0 011011X1X0
Reserved Expansion Temperature Coefficient
MC141537 3-114
Pattern 0111000X0
Command Increment/Decrement Contrast Level
Comment X0=0: decrement level X0=1: increment level (Note: increment/decrement wraps around; total contrast levels. Start lowest level when POR.)
0111001X0 0111010X0 0111011X0
Reserved Expansion Reserved Expansion Reserved X0=0: normal operation (POR) X0=1: test mode select (Note: sure X0=0 during application)
0111100X0 0111101X0
Reserved Expansion External Internal Oscillator X0=0: external oscillator (POR) X0=1: internal oscillator internal oscillator circuit enabled, place resistor between OSC1 OSC2. external oscillator mode, feed clock OSC2.
0111110X0 0111111X0
Reserved Expansion Oscillator Enable X0=0: oscillator disable (POR) X0=1: oscillator enable. This master control oscillator circuitry. Issue command before this command.
1X6X5X4X3X2X1X0
GDDRAM Column Address
GDDRAM Column Address. X6X5X4X3X2X1X0 address bits
DATA READ/WRITE TABLE
Pattern X7X6X5X4X3X2X1X0 Command Data Read Data Write line high When line high, Data read from GDDRAM. column address pointer will have increment automatically. Address Auto increment will apply last command Clear RAM. This dummy write. Comment When line low, Data write into GDDRAM. column address pointer will have increment automatically.
Address Increment Table (Automatic)
Comment Parallel Mode Write Command Parallel Mode Read Command Parallel Mode Write Data Parallel Mode Read Data Address Increment (invalid mode) Remarks
Address Increment done automatically after command being sent data read write. Only Column address pointer GDDRAM affected. Remark Under this condition, data, command will read from RAM. write data issued after Command Clear RAM, address applied. Column Address wraps around.
MC141537 3-115
Commands Required Actions RAMs
Actions RAMs Read/Write Data from/to GDDRAM. Commands Required GDDRAM Page Address, GDDRAM Column Address, Read/Write Data. Save/Restore GDDRAM Column Address. Dummy Read Data Master Clear GDDRAM, Dummy Write Data. (0000000X0)* (1X6X5X4X3X2X1X0)* (X7X6X5X4X3X2X1X0) (0011010X0) (X7X6X5X4X3X2X1X0) (00110110) (X7X6X5X4X3X2X1X0)
Save/Restore GDDRAM Column Address. Increment GDDRAM Address Clear GDDRAM Address.
Commands Required Display Mode Setup
Display Mode Graphic Mode Commands Required External Internal Oscillator, Oscillator Enable, Display External Internal Oscillator, Oscillator Enable, Annunciator On/Off. Display Off, Oscillator Disable. External Oscillator, Display Off, Oscillator Enable. Annunciator On/Off. Internal Oscillator, Display Off, Oscillator Enable. Annunciator On/Off. (0111101X0)* (01111111)* (00101001)* (0111101X0)* (01111111)* (01100A1A0X0)* (00101000)* (01111110)* (01111010)* (00101000)* (01111111)* (01100A1A0X0)* (01111011)* (00101000)* (01111111)* (01100A1A0X0)*
Annunciator Display
Standby Mode Standby Mode
Standby Mode
Other Related Command with Graphic Mode Column Mapping, Mapping, Vertical Scroll Value. Commands Related Voltage Generator Oscillator Enable Disable, External Internal Oscillator, Voltage Doubler Tripler Temperature Coefficient, Internal Regulator On/Off, Internal Constrast Control On/Off, Increase Decrease Contrast Level, Contrast Level, Internal Voltage Divider On/Off, Display On/Off. need already.
MC141537 3-116
Power Sequence (Commands Required)
Command Required External Internal Oscillator Voltage Tripler Doubler Internal DC/DC Converter Enable Internal Regulator Temperature Coefficient Internal Contrast Control Contrast Level Internal Voltage Divider Column Mapping Mapping Vertical Scroll Value Oscillator Enable Annunciator Control Signals Master Clear Dummy Write Data Display Status External Tripler TC=0% Contrast Level Seg. Col. Com. Scroll Value Disable Annunciators Random Remarks
Remarks Required only desired status differ from POR. Effective only Internal Contrast Control enabled. Effective only Regulator enabled.
Display Output Description Example
This example output pattern panel. Figure data GDDRAM output pattern display with different command enabled. (Scrolling, Column Re-map Re-map)
COM0
COM16 SEG0 SEG119
Figure
Content GDDRAM PAGE PAGE
Figure
Graphic Mode Column remap disable remap disable
Graphic Mode Column remap enable remap disable
Graphic Mode Column remap disable remap enable
Graphic Mode Column remap disable remap disable Scroll Value
Figure
MC141537 3-117
Application Circuit: (All Internal Analog Block Disabled, External Voltage Generator used)
0.1µF AVSS AVDD DVDD CMOS MPU/MCU D0~D7 OSC2 EPROM Remark Resistor value design refer panel characteristic. RES, should known state. line Standby Mode. Annun OSC1 DVSS VLL2 VLL3 VLL4 VLL5 VLL6 COM0 COM15
MC141537
SEG0 SEG119
Panel
Oscillation Circuitry
Application Circuit: (All Internal Analog Block Enabled)
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF AVSS AVDD DVDD CMOS MPU/MCU D0~D7 Annun
MC141537
DVSS VLL2 VLL3 VLL4 VLL5
VLL6
COM0 COM15
SEG0 SEG119
Panel
OSC2 OSC1
EPROM
760K
0.1µF 200K 560pF
0.1µF 4.7µF
0.1µF
Remark Capacitor between omitted only doubler enable. omitted external oscillator. left open Regulator disable, Contrast Disable. RES, should known state. line Standby Mode.
MC141537 3-118
MC141537 Coordinate
Name COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 DUMMY2 OSC2 AVSS VLL6 VLL5 VLL4 OSC1 VLL3 VLL2 AVDD DVSS DVDD DUMMY1 ANNUN2 ANNUN1 ANNUN0 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 (um) -2900.06 -2798.31 -2696.56 -2594.81 -2493.06 -2391.31 -2289.56 -2187.81 -2086.06 -1984.31 -1882.56 -1780.81 -1679.06 -1577.31 -1475.56 -1373.81 -1272.06 -1170.31 -1068.56 -966.81 -865.06 -763.31 -661.56 -559.81 -458.06 -356.31 -254.56 -152.81 -51.06 50.69 152.44 254.19 355.94 457.69 559.44 661.19 762.94 864.69 966.44 1068.19 1169.94 1271.69 1373.44 1475.19 1576.94 1678.69 1780.44 1882.19 1983.94 2085.69 2187.44 2289.19 2390.94 2492.69 2594.44 2696.19 2797.94 2899.69 (um) -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 -1958.41 Name SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 (um) 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 2953.34 (um) -1723.46 -1621.71 -1519.96 -1418.21 -1316.46 -1214.71 -1068.19 -966.44 -864.69 -762.94 -661.19 -559.44 -457.69 -355.94 -254.19 -152.44 -50.69 51.06 152.81 254.56 356.31 458.06 559.81 661.56 763.31 865.06 966.81 1068.56 1170.31 1272.06 1373.81 1475.56 1577.31 1679.06 1780.81 Name DUMMY DUMMY DUMMY DUMMY SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 DUMMY DUMMY DUMMY DUMMY (um) 2705.44 2603.69 2501.94 2400.19 2289.19 2187.44 2085.69 1983.94 1882.19 1780.44 1678.69 1576.94 1475.19 1373.44 1271.69 1169.94 1068.19 966.44 864.69 762.94 661.19 559.44 457.69 355.94 254.19 152.44 50.69 -51.06 -152.81 -254.56 -356.31 -458.06 -559.81 -661.56 -763.31 -865.06 -966.81 -1068.56 -1170.31 -1272.06 -1373.81 -1475.56 -1577.31 -1679.06 -1780.81 -1882.56 -1984.31 -2086.06 -2187.81 -2289.56 -2400.56 -2502.31 -2604.06 -2705.81 (um) 2035.37 2035.37 2035.37 2035.37 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 1958.41 2035.37 2035.37 2035.37 2035.37 Name SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 COM14 COM13 COM12 COM11 COM10 (um) -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 -2953.71 (um) 1780.81 1679.06 1577.31 1475.56 1373.81 1272.06 1170.31 1068.56 966.81 865.06 763.31 661.56 559.81 458.06 356.31 254.56 152.81 51.06 -50.69 -152.44 -254.19 -355.94 -457.69 -559.44 -661.19 -762.94 -864.69 -966.44 -1068.19 -1214.71 -1316.46 -1418.21 -1519.96 -1621.71 -1723.46
Size
MC141537 3-119
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