AVAILABLE MILITARY SPECIFICATIONS 5962-94612 MIL-STD-883 Fast Acc
|
|
|
Top Searches for this datasheet
Austin Semiconductor, Inc. 512K FLASH MEMORY ARRAY
AVAILABLE MILITARY SPECIFICATIONS
5962-94612 MIL-STD-883 Fast Access Times: 150ns Operation with single (±10%) Theta 1.00°C/w User configurable 512Kx32, 1Mx16, 2Mx8 Eight Equal Sectors Bytes each 512Kx8 Compatible with JEDEC EEPROM command Combination Sectors Erased Supports Full Chip Erase Embedded Erase Program Algorithms Compatible Inputs CMOS Outputs Built decoupling caps noise operation Suspend Erase/Resume Function Individual Byte Read/ Write Control 10,000 Program/Erase Cycles
AS8F512K32
ASSIGNMENT (Top View)
Lead CQFP
FEATURES
Lead
OPTIONS
Timing 70ns 90ns 120ns 150ns Package Ceramic Quad Flat pack Grid Array
MARKINGS
-120 -150
GENERAL DESCRIPTION
Austin Semiconductor, Inc. AS8F512K32 Megabit CMOS FLASH Memory Module organized 512Kx32 bits. AS8F512K32 achieves high speed access ns), power consumption high reliability employing advanced CMOS memory technology. on-chip state machine controls program erase functions. embedded byte-program sector/chip erase functions fully automatic. Data-protection sector combination accomplished using hardware sector-protection feature. Erase/Resume function allows sector erase operation read data from, program non-erasing sector, then resume erase operation. Device operations selected using standard commands into command register using standard microprocessor write timings. command register acts input internal state machine that interprets commands, controls erase programming operations, outputs status device, outputs data stored device. initial power-up operation, device defaults read mode.
AS8F512K32 Rev. 6/01
more products information please visit site www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
OPERATIONS
Read Mode low-level logic signal applied pins read output AS8F512K32. power control used device selection. delay from stable address valid output data address access time (tAVQA). delay from equals logic stable addresses valid output data chip-enable access time (tELQV). output-enable access time (tGLQV) delay from =low logic valid output data, when =low logic addresses stable least tAVQAtGLQV. Standby Mode supply current reduced applying logic-high enter standby mode. standby mode, outputs placed high impedance state. device deselected during erasure programming, device continues draw active current until operation complete. Output Disable OE\= CE\=VIH, output from device disabled output pins (DQ0 DQ7) placed high-impedance state. Erasure Programming Erasure programming AS8F512K32 accomplished writing sequence commands using standard microprocessor write timings. commands written command register input command state machine. command state machine interprets command entered initiates program, erase, suspend, resume operations instructed. command state machine acts interface between write-state machine external chip operations. write-state machine controls voltage generation, pulse generation, preconditioning verification contents memory. Program block/chip-erase functions fully automatic. Once program erase operation been reached, device internally resets read mode. drops below low-voltage-detect level (VLKO), operation progress aborted device resets read mode. byte-program chip-erase operation progress, additional program/erase operations ignored until operation completes. Command Definitions Operating modes selected writing particular address data sequences into command register Command Sequence Table device will reset read mode incorrect address data value writing them incorrect
AS8F512K32 Rev. 6/01
AS8F512K32
sequence transpires. command register does fill addressable memory location. register used store command sequence, along with address data needed memory array. Commands written setting CE\=VIL OE\= bring from logic-high logic-low. Addresses latched falling edge data latched rising edge WE\. Holding =VIL toggling used alternative. Read/Reset Command read/reset mode activated writing either read/reset command register. device remains this mode until other valid command sequences input into command register. Memory data read with standard microprocessor read-cycle timing read mode. power device defaults read/reset mode. read/reset command sequence required memory data available. Algorithm-Selection Command algorithm-selection command allows access binary code that matches device with proper programming erase-command operations. After writing three cycle command sequence, first byte algorithm-selection code (01) read from address XX00. second byte code (A4) read from address XX01. This mode remains effect until another valid command sequence written device. Byte-Program Command Byte-programming four-bus-cycle-command sequence. first three cycles device into programsetup state. fourth cycle loads address location data programmed into device. addresses latched falling edge data latched rising edge fourth cycle. raising edge starts byte-program operation. embedded byte-programming function automatically provides needed voltage timing program verify cell margin. further commands written device during program operation ignored. Programming preformed address location order. When erased, bits logic state Logic programmed into device. Attempting program logic into that been previously programmed logic causes internal pulse counter exceed pulse-count limit. This sets exceed-timing-limit indicator (DQ5) logic high state. Only erase operation change bits from logic logic status device during automatic programming operation monitored completion using data-polling feature toggle-bit feature "operation status" full description.
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Chip Erase Command Chip-erase six-bus-cycle command sequence. first three cycles device into erase-setup state. next cycles unlock erase mode. sixth cycle loads chip erase command. This command sequence required ensure that memory contents erased accidentally. rising edge starts chip erase operation. further commands written device during chip erase operation ignored. embedded chip erase function automatically provides voltage timings needed program verify memory cells prior electrical erase. then erases verifies cell margin automatically. user required program memory cells prior erase. status device during automatic chip erase operation monitored completion using data-polling feature. "operation status" section full description. Sector-Erase Command Sector erase six-bus-cycle command sequence. first three cycles device into erase-setup state. next cycles unlock erase mode. sixth cycle loads sector erase command sector address location erased. address location within desired sector used. addresses latched falling edge sixth cycle. After delay 100-ms from rising edge WE\, sector erase operation begins selected source. Sectors selected erased concurrently during sector-erase command sequence. each additional sector selected erase, another cycle issued. cycle loads next sector-address location sectorerase command. time between previous cycle start next cycle must less than ms-other wise, sector location loaded. time delay from raising edge last starts sector erase operation. there falling edge within time delay, timer reset. eight sector address locations loaded order. state delay timer monitored using sector-erase-delay indicator (DQ3). logic low, time delay expired. "operation status" full description. commands other than erase-suspend (B0) sector erase (30) written device during sector erase operation causes device exit sector erase mode. contents sector(s) selected erase valid. complete sector-erase operation, reissue sector erase command.
AS8F512K32
embedded sector erase function automatically provides voltage timings needed program verify memory cells prior electrical erase then erases verifies cell margin automatically. user required program memory cells prior erase. status device during automatic sector erase operation monitored completion using data-polling feature toggle feature. "operation status" section full description. Erase-Suspend Command Sector-erase operations interrupted erasesuspend command (B0) order read data from unaltered sectors device. Erase-suspend one-bus-cycle command. addresses erase-suspend command (B0) latched rising edge WE\. Once sector-erase operation progress, erase-suspend command request internal write-state-machine halt operation predetermined break points. erase-suspend command valid only during sector-erase operation valid only during byte-programming chip-erase operations. sector-erase delay timer expires immediately erase-suspend command issued while delay active. After erase-suspend issued, device takes between 0.1ms suspend operation. toggle must monitored determine when suspend been executed. When toggle stops toggling, data read from sectors that selected erase. "operation status" section full definition. Reading from sector marked erase result invalid data. Once sector-erase operation suspended, further writes erase-suspend command ignored. command other than erase-suspend (B0) erase-resume (30H) written device during erase-suspend mode causes device exit suspend mode. complete sectorerase operation, reissue sector-erase command sequence. Erase-Resume Command erase-resume command (30H) restarts suspended sector erase operation from where halted completion. Erase-resume one-bus-cycle command. addresses erase-resume command (30H) latched rising edge WE\. When erase-suspend/ eraseresume command combination written, internal pulse counter (exceed timing limit) reset. erase-resume command valid only erase-suspend state. After eraseresume command executed, device returns valid sector-erase state further writes erase-resume commands ignored. After device resumed sectorerase operation, another erase-resume command issued device.
Austin Semiconductor, Inc. reserves right change products specifications without notice.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc.
AS8F512K32
Operation Status Flags Table
Device Operations Byte-programming progress Byte-programming exceed time limit Byte-programming complete Sector/chip erase progress Sector/chip erase exceed time limit Sector/chip erase complete
NOTES: toggle, D=data, X=data undefined DQ4, DQ2, DQ1, reserved future use.
Status Definition During operation automatic embedded program erase functions, status device determined reading data state designated outputs. data-polling (DQ7) toggle-bit (DQ6) require multiple successive reads observe change state designated output. Operation Status Flags Table defines values Flag status. Data-Polling data-polling status outputs complement data latched into data register while write-state machine engaged program erase operation. Data changing from complement true indicates operation. Data-polling available only during byte-programming, chip-erase, sector-erase, sector-erase timing delay. Datapolling valid after rising edge ?W/E last cycle command sequence loaded into command register. During byte-program operation, reading outputs complement data programmed selected address location. Upon completion, reading outputs true data loaded into program data register. During erase operations, reading outputs Upon completion, reading outputs Also, data polling must performed sector address that within sector being erased; otherwise status valid. When using data-polling, address should remain stable throughout operation. During data-polling read, while ?W/E low, data change asynchronously. Depending read timing, system read valid data DQ7, while other pins still invalid. subsequent read device valid. Data-Polling function toggle-bit status, output data that toggles between while write-state machine engaged program erase operation. When toggleAS8F512K32 Rev. 6/01
OPERATION STATUS
stops toggling after consecutive reads same address, operation complete. toggle-bit only available during byte-programming, chip-erase, sectorerase timing delay. Toggle-bit data valid after raising edge ?W/E last cycle command sequence loaded into command register. Depending read timing, stop toggling while other pins still invalid. subsequent read device valid. Exceed Time Limit program erase operations internal pulse counter limit number pulses applied. pulse count limit exceeded, data state. This indicates that program erase operation failed. will change from complemented data true data will stop toggling when read. continue operation, device must reset. This condition occurs when attempting program logic state into that been programmed previously logic Only erase operation change bits from After reset, device functional erased reprogrammed. Sector-Load- Timer sector-load timer status determines time load additional sector addresses expired. remains logic after completion sector-erase sequence. This indicates another sector-erase command sequence issued. logic high, indicates that delay expired attempts issue additional sectorerase commands ignored. data polling toggle valid during time delay used determine valid sector erase command been issued. ensure additional sector erase commands have been accepted, status should read before after each additional sector-erase command. logic both reads, then additional sector-erase accepted.
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
DATA PROTECTION
Hardware-Sector Protection Feature This feature disables both programming erase operations combination eight sectors. Commands program erase protected sector change data contained sector. data-polling toggle bits operate 100ms then return valid data. This feature enabled using high-voltage (11.5V 12V) address control control CE\. device delivered with sector unprotected. Sector-unprotected mode available unprotect protected sectors. Sector Protect Operation sector protect mode activated when WE\=VIH, CE\=VIL address control forced VID. sector-select address pins A18, A17, used select sector protected. Address pins A0-A15 pins DQ0- must stable VIH. Once addresses stable, pulsed operation begins falling edge terminates raising edge WE\. Sector Protect Verify Verification sector protection activated when WE\=VIH, CE\=VIL OE\=VIL address VID. Address pins VIH. sector address pins A18, A17, select sector verified. other addresses VIL. sector selected protected, output sector selected unprotected output Sector protection also verified using algorithmselection command. After issuing three bus-cycle command sequence, sector protection status read DQ0. address pins VIL, VIH, VIL. Sector address pins A18, A17, select sector verified. remaining addresses sector selected protected. outputs state, sector selected unprotected outputs state. This mode remains effect until another valid sequence written device. Sector Unprotect Prior sector unprotected, sectors should protected using sector unprotect mode. sector unprotect activated when WE\=VIH, control CE\, OE\, address forced VID. Address pins A12, VIH. sector select address pins A18, A17, VIH. eight sectors unprotected parallel. Once inputs stable, pulsed 10ms. unprotect operation begins falling edge terminates raising edge WE\. Sector Unprotect Verify Verification sector unprotected activated when VIH, VIL, VIL, address VID. Select sector verified. Address VIL. other addresses VIH. sector selected protected, output sector selected unprotected output Sector unprotect also read using algorithm selection command. Write Lock During power-up power-down locked less than VLKO VCC<VLKO, command inputs disabled device reset read mode. power-up, CE\=VIL, WE\= VIL, OE\=VIH, device does accept commands raising edge device automatically powers read mode. Glitiching Pulses less than (typical) WE\, OE\, will issue write cycle. Power Supply Consideration Each device should have maximum ceramic capacitor connected between suppress circuit noise. Printed circuit traces should have appropriate handle current demand minimize inductance.
AS8F512K32
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Flow Chart Sector Protect Algorithm
AS8F512K32
Start
Select Sector Address A18,A17,A16
and, A9=VID CE=VIL
Apply Pulse
Select Sector Address A18, A17,
Read Data
Data
Sector-Protect Failed Protect Additional Sector
A9=VIH Write Reset Command
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
Flow Chart Sector Unprotect Algorithm
Start
Protect Sectors
CE,OE,A9=VID A12, A16=VIH
Apply Pulse
Select Sector Address A18, A17,
Read Data
1000 Data Next Sector Address
Sector-unprotect Failed Last Sector?
A9=VIH Write Reset Command
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Voltage Supply Relative (Note .-2.0V +7.0V (Note -2.0V +14V Other Pins (Note 1).-2.0V +7.0V Operating Temperature, (Ambient).55°C +125°C Storage Temperature .-65°C +150°C Power Dissipation.1.5W Short Circuit Output Current (Note 3).200mA Lead Temperature (soldering seconds).+300°C Junction Temperature.+165°C
AS8F512K32
*Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation section this specification implied, Exposure absolute maximum rating conditions extended periods affect reliability.
NOTES: Minimum voltage input pins -0.5V. During Voltage transitions, inputs overshoot -2.0V periods Maximum voltage input pins +0.5V. During Voltage transitions, inputs overshoot +2.0V periods Minium input voltage -0.5V. During voltage transitions, pins overshoot -2.0V periods Maximum input voltage +12.5V inputs which overshoot +13.5V periods more than output shorted time. Duration short circuit should greater than second.
Capacitance Table
1MHz, Symbol CADD CWE, Parame A0-A18 Capactiance Capactiance Capactiance Capactiance Maximum Units
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
User Operations
Operation Read Output Disable Standby Write Inhibit Write Sector Protect Verify Sector Protect Sector Unprotect Chart Verify Sector Unprotect Erase Operations
Chart
AS8F512K32
Chart
Note Note Note Note Note
Data HIGH HIGH Data Data Data Data Note
LEGEND: VIL, VIH, Don't Care, 12V, Charateristics voltage levels NOTE: Chip/Sector Erase Operation Timings Alternate Controlled Write Operation Timings.
Sector Address Table
SECTOR ADDRESS RANGE 00000-0FFFF 10000-1FFFF 20000-2FFFF 30000-3FFFF 40000-4FFFF 50000-5FFFF 60000-6FFFF 70000-7FFFF
Description
A0-A18 0-31
AS8F512K32 Rev. 6/01
Function Address Inputs Data Input/Outputs Chip Enable Write Enable Output Enable Device Ground Device Internal Power Supply (5.0 V+/- 10%)
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Command Denfinitions Table
Cycles
AS8F512K32
Command Sequence Reset Read Algorithm Selection Program Chip Erase Sector Erase Sector Erase Supend Sector Erase Resume
Cycles Second Third Fourth First Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data XXXX 5555 2AAA 5555 5555 2AAA 5555 5555 2AAA 5555 5555 2AAA 5555 5555 2AAA 5555 5555 2AAA 5555 5555 2AAA XXXX Erase-supend vaild during sector-erase operation XXXX Erase-resume vaild only after erase supend
LEGEND: Address location read Address location programed Address sector erased Addresses A18, A17, select sectors Data read selected address location Data programmed selected address location *Address A18, A17, A16, cycle addresses except program address (PA), sector address(SA), read address (RA).
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55°C 125°C; +5%/-10%)
NOTES: active while Embedded Program Embedded Erase Algorithm progress. 100% tested. Applies operations.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55°C 125°C; -5%/+10%)
Parameter Symbol JEDEC Std. tAVAV tAVQV tELQV tGLQV tACC tOEH tEHQZ tGHQZ tAXQX Speed Options Parameter Description Read Cycle Time (Note Address Output Delay Chip Enable Output Valid Output Enable Output Delay Read Output Enable Hold Time Toggle (Note Data\Polling Chip Enable High Output High (Note Output Enable Output High (Note 2,3) Output Hold Time from Addresses, OE\, Whichever Occurs First Test Setup CE\=VIL, OE\=VIL CE\=VIL, OE\=VIL -120 -150 Units
NOTES: Test Specification test conditions. Output driver disable time. Guaranteed Tested.
Read Operation Timings
Addresses
Addresses Stable
Outputs High-Z
High-Z
Output Valid
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55°C 125°C; 10%)
Erase Program Controlled
Parameter Symbol JEDEC Std. tAVAV tAVWL tWLAX tDVWH tWHDX tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tWHWH3 tVCHEL tGHWL tWPH tWHWH1 tWHWH2 tWHWH3 Parameter Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Write Enable High Input Transition Output Enable Setup Time Read Recover time Before Write (OE\ high low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Programming Operation Sector Erase Operation Chip Erase Operation Setup Time Chip Program Time Speed Options -120 Units -150
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Program Operation Timings
555h
AS8F512K32
Addresses
GHWL
Status DOUT
Data
NOTE: Program Address, Program data, DOUT true data program address.
AS8F512K32 Rev. 6/01
543214321 543212121 2141 2343 543412121 543412321 2341
WHWH1
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
Chip/Sector Erase Operation Timings
AS8F512K32
Addresses
2AAh
555h Chip Erase
GHWL
30th
Chip Erase
Data
NOTE: Sector Address. Valid Address reading status data.
AS8F512K32 Rev. 6/01
543114321 2521 543112121 1341 4343 2521 543412121 2523 543112321 2341
WHWH2
Progress
Complete
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
Data Polling Timings (During Embedded Algorithms)
Addresses
Complement True Valid Data
High-Z
Complement
DQ0-DQ6
Status Data
Status Data
NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Toggle Timings During Embedded Algorithms)
Addresses
Valid Status Valid Status Valid Status
DQ6/DQ2
Valid Status
(first read)
NOTE: VA=Valid address; required DQ6. Illustration shows first status cycles after command sequence, last status read cycle, array data read cycle.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
654321 654321 654321 654321 654321
654523 65452121 65454321 32121 65432121 65454321
5432343 543212121 4343 1543 412121 543412121 1343 2321 543212121 1343 543212121
True
543254321 543454321 4321 543254321 2121 543232121 1123 4541 543454321
Valid Data
High-Z
Austin Semiconductor, Inc.
AS8F512K32
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS (-55°C 125°C; 10%)
Erase Program Controlled (Alternate Controlled Writes)
Parameter Symbol JEDEC Std. tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tGHEL tWLEL tEHWH tELEH tCPH tEHEL tWHWH1 tWHWH1 tWHWH2 tWHWH2 Parameter Description Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recover time Before Write Setup Time, Hold Time, Pulse Duration Pulse Duration High Byte Programming Operation Sector Erase Operation Chip Erase Chip Programming Speed Options -120 Units -150
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
Alternate Controlled Write Operation Timings
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
TEST CONDITIONS
AS8F512K32
Current Source
Device Under Test
1.5V (Bipolar Supply)
Ceff 50pf
Current Source
NOTES: programable from programmable from typically midpoint VOL. adjusted simulate typical resistive load circuit.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
MECHANICAL DEFINITIONS*
Case #702 (Package Designator 5962-94612, Case Outline
DETAIL
DETAIL
SPECIFICATIONS SYMBOL 0.123 0.118 0.005 0.010 0.013 0.800 0.870 0.980 0.936 0.050 0.010 0.035 0.045 0.890 1.000 0.956 0.017 0.200 0.186 0.015
*All measurements inches.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
MECHANICAL DEFINITIONS*
Case #904 (Package Designator 5962-94612, Case Outline
(identified 0.060 square pad)
SPECIFICATIONS SYMBOL D1/E1 0.135 0.025 0.016 0.045 0.065 1.064 1.000 0.600 1.020 0.100 0.145 0.155 1.060 0.195 0.035 0.020 0.055 0.075 1.086
*All measurements inches.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc. ORDERING INFORMATION
AS8F512K32
EXAMPLE: AS8F512K32Q-120/XT
Device Number AS8F512K32 AS8F512K32 AS8F512K32 AS8F512K32 Package Type Speed -120 -150 Process
EXAMPLE: AS8F512K32P-120/XT
Device Number AS8F512K32 AS8F512K32 AS8F512K32 AS8F512K32 Package Type Speed -120 -150 Process
*AVAILABLE PROCESSES Commercial Temperature Range Industrial Temperature Range Extended Temperature Range 883C Full Military Processing
+70oC -40oC +85oC -55oC +125oC -55oC +125oC
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Austin Semiconductor, Inc.
AS8F512K32
DSCC PART NUMBER* CROSS REFERENCE
Package Designator
Part
AS8F512K32Q-150/883C AS8F512K32Q-120/883C AS8F512K32Q-90/883C AS8F512K32Q-70/883C AS8F512K32Q-150/883C AS8F512K32Q-120/883C AS8F512K32Q-90/883C AS8F512K32Q-70/883C
Part
5962-9461201HMA 5962-9461202HMA 5962-9461203HMA 5962-9461204HMA (pending) 5962-9461201HMC 5962-9461202HMC 5962-9461203HMC 5962-9461204HMC (pending)
Package Designator
Part
AS8F512K32P-150/883C AS8F512K32P-120/883C AS8F512K32P-90/883C AS8F512K32P-70/883C AS8F512K32P-150/883C AS8F512K32P-120/883C AS8F512K32P-90/883C AS8F512K32P-70/883C
Part
5962-9461201H4A 5962-9461202H4A 5962-9461203H4A 5962-9461204H4A (pending) 5962-9461201H4C 5962-9461202H4C 5962-9461203H4C 5962-9461204H4C (pending)
part number reference only. Orders received referencing part number will processed SMD.
AS8F512K32 Rev. 6/01
Austin Semiconductor, Inc. reserves right change products specifications without notice.
Other recent searches
T1210-XXX - T1210-XXX T1210-XXX Datasheet
STM690A - STM690A STM690A Datasheet
STM692A - STM692A STM692A Datasheet
STM703 - STM703 STM703 Datasheet
STM704 - STM704 STM704 Datasheet
STM802 - STM802 STM802 Datasheet
STM805 - STM805 STM805 Datasheet
STM817 - STM817 STM817 Datasheet
SSB6553 - SSB6553 SSB6553 Datasheet
SQM40N10-30 - SQM40N10-30 SQM40N10-30 Datasheet
MTD6P10E - MTD6P10E MTD6P10E Datasheet
MMBD717W - MMBD717W MMBD717W Datasheet
CS2300-CP - CS2300-CP CS2300-CP Datasheet
CP-1201 - CP-1201 CP-1201 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
