wire interface Real-Time Clock EA-120-0505 R2033K(Preliminar

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OUTLINE
wire interface Real-Time Clock
EA-120-0505
R2033K(Preliminary) R2033T
R2033K/T CMOS real-time clock connected three signal lines, SCLK, SIO, configured perform serial transmission time calendar data CPU. periodic interrupt circuit configured generate interrupt signals with selectable interrupts ranging from seconds month. alarm interrupt circuits generate interrupt signals preset times. oscillation circuit driven under constant voltage, fluctuation oscillator frequency supply voltage small, time keeping current small (TYP. 0.45µA 3V). oscillation halt sensing circuit used judge validity internal data such events power-on; supply voltage monitoring circuit configured record drop supply voltage below selectable supply voltage monitoring threshold settings. 32.768kHz clock output function (CMOS output with control pin) intended output sub-clock pulses external microcomputer. oscillation adjustment circuit intended adjust time counts with high precision correcting deviations oscillation frequency crystal oscillator. Since package these TSSOP10G (4.0x2.9x1.0: R2033T) FFP12 (2.0x2.0x1.0: R2033K), high density mounting boards possible.
FEATURES
Minimum Timekeeping supply voltage TYP:0.66 5.5v (Worst: 1.00V 5.5v); power consumption 0.45µA VDD=3V (1.00µA MAX.) Three signal lines (CE, SCLK, SIO) required connection CPU. (Maximum clock frequency 1MHz (with Time counters (counting hours, minutes, seconds) calendar counters (counting years, months, days, weeks) format) Interrupt circuit configured generate interrupt signals (with interrupts ranging from seconds month) provided with interrupt flag interrupt halt alarm interrupt circuits (Alarm_W week, hour, minute alarm settings Alarm_D hour minute alarm settings) With Power-on flag prove that power supply starts from 32-kHz clock output (CMOS push-pull output with control pin) Supply voltage monitoring circuit with supply voltage monitoring threshold settings Automatic identification leap years year 2099 Selectable 12-hour 24-hour mode settings High precision oscillation adjustment circuit Built-in oscillation stabilization capacitors Package TSSOP10G (4.0mm 2.9mm 1.0mm: R2033T) FFP12 (2.0mm 2.0mm 1.0mm: R2033K) CMOS process
R2033K(Preliminary) R2033T
CONFIGURATION
R2033T(TSSOP10G)
R2033K(FFP12)
OSCOUT OSCIN CLKC
32KOUT SCLK
OSCIN OSCOUT CLKC INTR
INTR
SCLK
VIEW
VIEW
BLOCK DIAGRAM
32KOUT CLKC 32kHz OUTPUT CONTROL COMPARATOR_W ALARM_W REGISTER (MIN,HOUR, WEEK) ALARM_D REGISTER (MIN,HOUR) VOLTAGE DETECT POWER_ON RESET
COMPARATOR_D OSCIN OSCOUT
DIVIDER CORREC -TION
TIME COUNTER
32KOUT
DETECT
ADDRESS DECODER
ADDRESS REGISTER
(VSS) (VSS)
SCLK CONTROL
INTR
INTERRUPT CONTROL
SHIFT REGISTER
SELECTION GUIDE
Part Number designated follows: R2033K-E2 Part Number R2033a-cc Code Description Designation package. FFP12 TSSOP10G Designation taping type. Only available.
R2033K(Preliminary) R2033T
DESCRIPTION
Symbol Item Chip enable Input Description used interfacing with CPU. Should held high allow access CPU. Incorporates pull-down resistor. Should held open when powered off. Allows maximum input voltage 5.5v regardless supply voltage. SCLK used input clock pulses synchronizing input output data from pin. Allows maximum input voltage 5.5v regardless supply voltage. used input output data intended writing reading synchronization with SCLK pin. CMOS input output. INTR used output alarm interrupt (Alarm_W) alarm interrupt (Alarm_D) output periodic interrupt signals CPU. Disabled power-on from N-channel open drain output. Allows maximum pull-up voltage 5.5v regardless supply voltage. 32KOUT used output 32.768-kHz clock pulses. CMOS push-pull output. output disabled held when CLKC open, certain register setting. This enabled power-on from CLKC used control output 32KOUT pin. clock output disabled held when this open. Incorporated pull down register. OSCIN OSCOUT pins used connect 32.768-kHz crystal oscillator (with other oscillation circuit components built into R2033K/T). connected power supply. grounded.
SCLK
Serial Clock Input Serial Input Output Interrupt Output
INTR
32KOUT
32kHz Clock Output
CLKC
Clock Control
OSCIN OSCOUT (VSS)
Oscillation Circuit Input Output Positive/Negative Power Supply Input
Please connect ground line, connect lines.
R2033K(Preliminary) R2033T
ABSOLUTE MAXIMUM RATINGS
(VSS=0V) Symbol Item Supply Voltage Input Voltage Input Voltage Output Voltage Output Voltage Power Dissipation Topt Operating Temperature Tstg Storage Temperature Name SCLK, CLKC SIO, 32KOUT INTR Topt 25°C Description -0.3 +6.5 -0.3 +6.5 -0.3 -0.3 -0.3 +6.5 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Vaccess Item Supply Voltage Name Power supply voltage interfacing with CGout,CDout=0pF *1), CGout,CDout=0pF *1), INTR 32KOUT (VSS=0V, Topt=-40 +85°C) Min, Typ. Max. Unit 1.00 0.66 32.768 5.50 1.00
VCLK VCLKL VPUP
Time keeping Voltage Minimum Time keeping Voltage Oscillation Frequency Pull-up Voltage
+0.3 CGout connected between OSCIN VSS, CDout connected between OSCOUT VSS. R2033K/T incorporates capacitors between OSCIN VSS, between OSCOUT VSS. Then normally, CGout CDout necessary. more detail, "P.32 Adjustment Circuit" Crystal oscillator: CL=6-9pF, R1=50K
R2033K(Preliminary) R2033T
ELECTRICAL CHARACTERISTICS
R2033K/T
(Unless otherwise specified: VSS=0V, VDD=3.0V, Topt=-40 +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=50k) Symbol Item Name Conditions Min. Typ. Input Voltage VIH1 SCLK, VDD=1.7 5.5V 0.8x CLKC VIH2 0.8x -0.3 Input Voltage SCLK, CLKC, Output SIO, VOH=VDD-0.5V Current 32KOUT VOL=0.4V IOL1 Output INTR Current IOL2 SIO, 32KOUT Input Leakage SCLK VI=5.5V -1.0 Current VDD=5.5V RDNCE Pull-down Resistance ICLKC Pull-down Resister CLKC 0.35 Input Leakage Current IOZ1 VO=5.5V Output Off-state VDD=5.5V Current VO=5.5V IOZ2 INTR VDD=5.5V Time Keeping Current VDD=3V, CE=SCLK=SIO=CLKC 0.45 INTR 32KOUT=OFF Output OPEN CGout=CDout=0pF VDETH Supply Voltage 1.45 1.60 Topt=-30 +70°C Monitoring Voltage VDETL Supply Voltage 1.15 1.30 Topt=-30 +70°C Monitoring Voltage time keeping current when outputting 32.768kHz from 32KOUT pin, "P.44 CHARACTERISTICS". time keeping current when CGOUT, CDOUT equal 0pF, oscillation frequency".
Max. VDD+0. 0.2x -0.5
Unit
1.00
1.00
1.75 1.45 TYPICAL "P.29
R2033K(Preliminary) R2033T
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 +85°C Input Output Conditions: Item CondiVDD1.7V -bol Tions Min. Typ. Max. tCES Set-up Time tCEH Hold Time Recovery Time fSCLK SCLK Clock Frequency tCKH SCLK Clock Time tCKL SCLK Clock Time tCKS SCLK Set-up Time Data Output Delay Time Data Output Floating Time tCEZ Data Output Delay Time After Falling Input Data Set-up Time Input Data Hold Time Time tDELAY Output Delay Time Voltage Keeping Detector Unit
tCKH tCKS SCLK tCES
tCKL tCEH
SIO(write cycle) SIO(read cycle)
tCEZ
reading/writing timing, "P.26 Reading Writing Time Data under special condition".
R2033K(Preliminary) R2033T
PACKAGE DIMENSIONS
R2033K
1PIN INDEX
0.05
2PIN INDEX 0.35 0.35 0.25 1.0Max
0.103
0.3±0.15
0.2±0.15
(BOTTOM VIEW) 0.17±0.1 0.27±0.15 2.0±0.1
unit:
2.0±0.1
R2033K(Preliminary) R2033T
R2033T
2.9±0.2
2.8±0.2
4.0±0.2
(0.75)
0.13 -0.05
+0.1
0.2±0.1 0.15
-0.05
+0.1
0.85±0.15
0.55±0.2
unit:
TAPING SPECIFICATION
R2033K/T have designated taping direction. product designation taping components "R2033K/T-E2".
R2033K(Preliminary) R2033T
GENERAL DESCRIPTION
Interface with
R2033K/T connected three signal lines (Chip Enable), SCLK (Serial Clock), (Serial Input Output), through which reads writes data from CPU. accessed when held high. Access clock pulses have maximum frequency allowing high-speed data transfer CPU.
Clock Calendar Function
R2033K/T reads writes time data from units ranging from seconds last digits calendar year. calendar year will automatically identified leap year when last digits multiple Consequently, leap years year 2099 automatically identified such. year 2000 leap year while year 2100 leap year.
Alarm Function
R2033K/T incorporates alarm interrupt circuit configured generate interrupt signals preset times. alarm interrupt circuit allows types alarm settings specified Alarm_W registers Alarm_D registers. Alarm_W registers allow week, hour, minute alarm settings including combinations multiple day-of-week settings such "Monday, Wednesday, Friday" "Saturday Sunday". Alarm_D registers allow hour minute alarm settings. Alarm_W outputs from INTR pin, Alarm_D outputs also from /INTR pin. Each alarm function checked from using polling function.
High-precision Oscillation Adjustment Function
R2033K/T built-in oscillation stabilization capacitors CD), which connected external crystal oscillator configure oscillation circuit. kinds accuracy this function alternatives. correct deviations oscillator frequency crystal, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm ±0.5ppm 25°C) from CPU. maximum range approximately ±189ppm ±63ppm) increments approximately 3ppm 1ppm). Such oscillation frequency adjustment each system following advantages: Allows timekeeping with much higher precision than conventional RTCs while using crystal oscillator with wide range precision variations. Corrects seasonal frequency deviations through seasonal oscillation adjustment. Allows timekeeping with higher precision particularly with temperature sensing function RTC, through oscillation adjustment tune with temperature fluctuations.
Power-on Reset, Oscillation Halt Sensing Function Supply Voltage Monitoring Function
R2033K/T incorporates oscillation halt sensing circuit equipped with internal registers configured record past oscillation halt. Power reset function reset control resisters when system powered from same time, fact memorized resister flag, thereby identifying whether they powered from battery backed-up. R2033K/T also incorporates supply voltage monitoring circuit equipped with internal registers configured record drop supply voltage below certain threshold value. Supply voltage monitoring threshold
R2033K(Preliminary) R2033T
settings selected between 1.6V 1.3V through internal register settings. sampling rate normally oscillation halt sensing circuit power-on reset flag configured confirm established invalidation time data contrast supply voltage monitoring circuit intended confirm potential invalidation time data. Further, supply voltage monitoring circuit applied battery supply voltage monitoring.
Periodic Interrupt Function
R2033K/T incorporates periodic interrupt circuit configured generate periodic interrupt signals aside from interrupt signals generated alarm interrupt circuit output from INTR pin. Periodic interrupt signals have five selectable frequency settings (once seconds), (once second), 1/60 (once minute), 1/3600 (once hour), monthly (the first every month). Further, periodic interrupt signals also have selectable waveforms, normal pulse form (with frequency special form adapted interruption from level mode (with second, minute, hour, month interrupts). condition periodic interrupt signals monitored with using polling function.
32kHz Clock Output
R2033K/T incorporates 32-kHz clock circuit configured generate clock pulses with oscillation frequency 32.768kHz crystal oscillator output from 32KOUT pin. 32KOUT CMOS push-pull output output enabled disabled when CLKC held high, open, respectively. 32-kHz clock output disabled certain register settings cannot disabled without manipulation registers with different addresses prevent disabling such events runaway CPU. 32-kHz clock circuit enabled power-on, when CLKC held high.
R2033K(Preliminary) R2033T
Address Mapping
Address A3A2A1A0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Register Name Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter Month Counter Century Year Counter Oscillation Adjustment Register Alarm_W (Minute Register) Alarm_W (Hour Register) Alarm_W (Day-of-week Register) Alarm_D (Minute Register) Alarm_D (Hour Register) Control Register Control Register WALE VDSL WM40 DM40 WM20 WH20 DM20 MO10 WM10 WH10 DM10 WAFG DAFG
DH10 DH20 DALE CLEN2 TEST VDET CLEN1 CTFG
Notes: data listed above accept both reading writing. data marked with invalid writing reset reading. When Control Register bits reset Oscillation Adjustment Register, Control Register Control Register excluding bit. When DEV=0, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm. When DEV=1, oscillation adjustment circuit configured allow correction time count gain loss ±0.5ppm. power-on-reset flag.
R2033K(Preliminary) R2033T
Register Settings
Control Register (ADDRESS
TEST (For Writing) WALE DALE CLEN2 WALE DALE TEST (For Reading) CLEN2 Default Settings Default settings: Default value means read written values when power-on from volts.
WALE, DALEAlarm_W Enable Bit, Alarm_D Enable
WALE,DALE Description Disabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers). Enabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers) (Default)
/24-hour Mode Selection Description Selecting 12-hour mode with a.m. p.m. indications. Selecting 24-hour mode Setting specifies 12-hour mode 24-hour mode, respectively.
(Default)
24-hour mode 12-hour mode 24-hour mode (AM12) (AM10) (AM11) Setting should precede writing time data
12-hour mode (PM12) (PM10) (PM11)
CLEN2
32kHz Clock Output
Description CLEN2 Enabling 32-kHz clock circuit (Default) Disabling 32-kHz clock circuit Setting CLEN2 CLEN1 control register CLKC high specifies generating clock pulses with oscillation frequency 32.768-kHz crystal oscillator output from 32KOUT pin. Conversely, setting both CLEN1 CLEN2 CLKC specifies disabling ("L") such output.
R2033K(Preliminary) R2033T
TEST
TEST
Test
(Default)
Description Normal operation mode. Test mode. TEST used only testing factory should normally
CT2,CT1,
Periodic Interrupt Selection Bits
Wave form mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Interrupt Cycle Falling Timing OFF(H) Fixed 2Hz(Duty50%) 1Hz(Duty50%) Once second (Synchronized with second counter increment) Once minute seconds every minute) Once hour minutes seconds every hour) Once month hours, minutes, seconds first every month) (Default)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG INTR Approx. 92µs (Increment second counter) Rewriting second counter
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving INTR low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
R2033K(Preliminary) R2033T
CTFG INTR Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. 60sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784 example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784
R2033K(Preliminary) R2033T
Control Register (Address
CTFG WAFG DAFG (For Writing) VDSL VDET CLEN1 VDSL VDET CTFG WAFG DAFG (For Reading) CLEN1 Indefinite Default Settings Default settings: Default value means read written values when power-on from volts.
VDSL
VDSL
Supply Voltage Monitoring Threshold Selection
(Default)
Description Selecting supply voltage monitoring threshold setting 2.1v. Selecting supply voltage monitoring threshold setting 1.35v. VDSL intended select supply voltage monitoring threshold settings.
VDET
VDET
Supply Voltage Monitoring Result Indication
Description Indicating supply voltage above supply voltage monitoring (Default) threshold settings. Indicating supply voltage below supply voltage monitoring threshold settings. Once VDET supply voltage monitoring circuit will disabled while VDET will hold setting VDET accepts only writing which restarts supply voltage monitoring circuit. Conversely, setting VDET causes event.
Oscillation Halt Sensing Monitor
Description Sensing halt oscillation Sensing normal condition oscillation accepts reading writing will when oscillation halt sensing. will hold even after restart oscillation.
Power-on-reset Flag
Description Normal condition Detecting power-on -reset sensing power-on reset condition.
(Default)
will when power-on from volts. will hold setting even after power-on. When bits will reset Oscillation Adjustment Register, Control Register Control Register except PON. result, INTR stops outputting. accepts only writing Conversely, setting causes event.
R2033K(Preliminary) R2033T
CLEN1
32kHz Clock Output
Description CLEN1 Enabling 32-kHz clock circuit (Default) Disabling 32-kHz clock circuit Setting CLEN1 CLEN2 control register CLKC high specifies generating clock pulses with oscillation frequency 32.768-kHz crystal oscillator output from 32KOUT pin. Conversely, setting both CLEN1 CLEN2 CLKC specifies disabling ("L") such output.
CTFG
CTFG
Periodic Interrupt Flag
Description Periodic interrupt output (Default) Periodic interrupt output CTFG when periodic interrupt signals output from INTR ("L"). CTFG accepts only writing level mode, which disables ("H") INTR until enabled ("L") again next interrupt cycle. Conversely, setting CTFG causes event.
WAFG,DAFG
Alarm_W Flag Alarm_D Flag
WAFG,DAFG Description Indicating mismatch between current time preset alarm time (Default) Indicating match between current time preset alarm time WAFG DAFG bits valid only when WALE DALE have setting which caused approximately 61µs after match between current time preset alarm time specified Alarm_W registers Alarm_D registers. WAFG (DAFG) accepts only writing INTR outputs ("H") when this INTR outputs again next preset alarm time. Conversely, setting WAFG DAFG bits causes event. WAFG DAFG bits will have reading when alarm interrupt circuit disabled with WALE DALE bits settings WAFG DAFG bits synchronized with output INTR shown timing chart below.
Approx. 61µs WAFG(DAFG) INTR Writing WAFG(DAFG) (Match between current time preset alarm time) (Match between current time preset alarm time) Writing WAFG(DAFG) (Match between current time preset alarm time) Approx. 61µs
R2033K(Preliminary) R2033T
Time Counter (Address 0-2h)
Second Counter (Address Indefi Indefi nite nite Minute Counter (Address Indefi Indefi nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Hour Counter (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. Time digit display (BCD format) follows: second digits range from carried minute digit transition from minute digits range from carried hour digits transition from hour digits range shown "P12 Control Register (ADDRESS /24: /24-hour Mode Selection Bit" carried day-of-month day-of-week digits transition from PM11 AM12 from writing second counter resets divider units less than second. carry from lower digits with writing non-existent time cause time counters malfunction. Therefore, such incorrect writing should replaced with writing existent time data.
R2033K(Preliminary) R2033T
Day-of-week Counter (Address
(For Writing) (For Reading) Indefi Indefi Indefi Default Settings nite nite nite Default settings: Default value means read written values when power-on from volts. day-of-week counter incremented when day-of-week digits carried day-of-month digits. Day-of-week display (incremented septimal notation): (W4, 1).(1, Correspondences between days week day-of-week digits user-definable (e.g. Sunday writing (W4, prohibited except when days week unused.
Calendar Counter (Address 4-6h)
Day-of-month Counter (Address Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Month Counter Century (Address MO10 MO10 Indefin Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Year Counter (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. calendar counters configured display calendar digits format using automatic calendar function follows: day-of-month digits (D20 range from January, March, May, July, August, October, December; from April, June, September, November; from February leap
R2033K(Preliminary) R2033T
years; from February ordinary years. day-of-month digits carried month digits reversion from last month month digits (MO10 MO1) range from carried year digits reversion from year digits (Y80 range from (00, leap years) carried digits reversion from digits cycle between reversion from year digits. carry from lower digits with writing non-existent calendar data cause calendar counters malfunction. Therefore, such incorrect writing should replaced with writing existent calendar data.
Oscillation Adjustment Register (Address
(For Writing) (For Reading) Default Settings Default settings: Default value means read written values when power-on from volts. When Oscillation Adjustment Circuit operates seconds. When Oscillation Adjustment Circuit operates seconds. bits Oscillation Adjustment Circuit configured change time counts second basis settings Oscillation Adjustment Register timing DEV. Oscillation Adjustment Circuit will operate with same timing (00, seconds) timing writing Oscillation Adjustment Register. setting causes increment time counts ((F5, setting causes decrement time counts F5,F4,F3,F2,F1,F0 settings ("*" representing either "1") bits cause neither increment decrement time counts. Example: (DEV, when second digits read increment current time counts 32768 32780 current time count loss). (DEV, when second digits read neither increment decrement current time counts 32768. (DEV, when second digits read decrement current time counts 32768 32764 current time count gain). increase clock pulses once seconds causes time count loss approximately (32768 3.051 ppm). Conversely, decrease clock pulses once seconds causes time count gain ppm. Consequently, when "0", deviations time counts corrected with precision ±1.5 ppm. same way, when "1", deviations time counts corrected with precision ±0.5 ppm. Note that oscillation adjustment circuit configured correct deviations time counts oscillation frequency 32.768-kHz clock pulses. further details, "P32 Configuration Oscillation Circuit Correction Time Count Deviations Oscillation Adjustment Circuit".
R2033K(Preliminary) R2033T
Alarm_W Registers (Address 8-Ah)
Alarm_W Minute Register (Address WM40 WM20 WM10 WM40 WM20 WM10 Indefi Indefi Indefi nite nite nite Alarm_W Hour Register (Address WH10 WH20 WH20 WH10 Indefi Indefi nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Alarm_W Day-of-week Register (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. Alarm_W Hour Register represents when 12-hour mode selected a.m. p.m.) WH20 when 24-hour mode selected (tens hour digits). Alarm_W Registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_W registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read a.m. p.m., respectively. (See "P12 Register (ADDRESS /24: /24-hour Mode Selection Bit") correspond day-of-week counter with settings ranging from with respective settings disable outputs Alarm_W Registers.
R2033K(Preliminary) R2033T
Example Alarm Time Setting Alarm
Preset alarm time Sun. Mon.
Day-of-week
Tue. Wed. Fri. Sat.
12-hour mode
24-hour mode
min. min.
min. min.
00:00 a.m. days 01:30 a.m. days 11:59 a.m. days 00:00 p.m. Mon. Fri. 01:30 p.m. Sun. 11:59 p.m. Mon. ,Wed., Fri.
Note that correspondence between days week shown above table only example mandatory.
Alarm_D Register (Address B-Ch)
Alarm_D Minute Register (Address DM40 DM20 DM10 DM40 DM20 DM10 Indefi Indefi Indefi nite nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Alarm_D Hour Register (Address DH20 DH10 (For Writing) DH20 DH10 (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. represents when 12-hour mode selected a.m. p.m.) DH20 when 24-hour mode selected (tens hour digits). Alarm_D registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_D registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read 0a.m. 0p.m., respectively. (See "P12 Register (ADDRESS /24: /24-hour Mode Selection Bit")
R2033K(Preliminary) R2033T
Interfacing with
DATA TRANSFER FORMATS Timing Between Transition Data Input Output
R2033K/T adopts 3-wire serial interface which they (Chip Enable), SCLK (Serial Clock), (Serial Input/Output) pins receive send data from CPU. 3-wire serial interface provides types input/output timings with which output input synchronized with rising falling edges SCLK input, respectively, vice versa. R2033K/T configured select either different input/output timings depending level SCLK high transition pin. Namely, when SCLK held high transition pin, models will select timing with which output synchronized with rising edge SCLK input, input synchronized with falling edge SCLK input, illustrated timing chart below.
SCLK (for writing)
tCES
(for reading)
Conversely, when SCLK held high high transition pin, models will select timing with which output synchronized with falling edge SCLK input, input synchronized with rising edge SCLK input, illustrated timing chart below.
SCLK (for writing)
tCES
(for reading)
R2033K(Preliminary) R2033T
Data Transfer Formats
Data transfer commenced high transition input completed high transition. Data transfer conducted serially multiple units byte bits). former bits used specify Address Pointer head address with which data transfer commenced from host. latter bits used select either reading data transfer writing data transfer, Transfer Format Register specify appropriate data transfer format. data transfer formats designed transfer most significant (MSB) first.
SCLK
Setting Address Pointer
Setting Transfer Format Register
Writing Reading data transfer
types data transfer formats available reading data transfer writing data transfer each.
Writing Data Transfer Formats
1-byte Writing Data Transfer Format
first type writing data transfer format designed transfer 1-byte data time selected specifying address pointer head address with which writing data transfer commenced then writing setting transfer format register. This 1-byte writing data transfer completed driving continued specifying head address address pointer setting data transfer format.
Example 1-byte Writing Data Transfer (For Writing Data Addresses
Specifying FhSetting Address Pointer Transfer Format Register
Data
Writing data address
Data
Specifying Setting Writing data Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
R2033K(Preliminary) R2033T
Burst Writing Data Transfer Format
second type writing data transfer format designed transfer sequence data serially selected specifying address pointer head address with which writing data transfer commenced then writing setting transfer format register. address pointer incremented each transfer 1-byte data cycled from This burst writing data transfer completed driving low.
Example Burst Writing Data Transfer (For Writing Data Addresses
Data Data
Writing data address
Data
Writing data address
Specifying EhSetting Writing data Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
Reading Data Transfer Formats
1-byte Reading Data Transfer Format
first type reading data transfer format designed transfer 1-byte data time selected specifying Address Pointer head address with which reading data transfer commenced then setting writing Transfer Format Register. This 1-byte reading data transfer completed driving continued specifying head address Address Pointer selecting this type reading data Transfer Format.
Example 1-byte Reading Data Transfer (For Reading Data from Addresses
Specifying EhSetting Address Pointer Transfer Format Register
Data
Reading data from address
Data
Specifying Setting Reading data from Address Pointer Transfer Format Register address
Data transfer from host
Data transfer from RTCs
R2033K(Preliminary) R2033T
Burst Reading Data Transfer Format
second type reading data transfer format designed transfer sequence data serially selected specifying address pointer head address with which reading data transfer commenced then writing setting transfer format register. address pointer incremented each transfer 1-byte data cycled from This burst reading data transfer completed driving low.
Example Burst Reading Data Transfer (For Reading Data from Addresses
DATA DATA
Reading data from address
DATA
Reading data from address
Specifying FhSetting Reading data from Transfer address Address Pointer Format Register
Data transfer from host
Data transfer from RTCs
Combination 1-byte Reading writing Data Transfer Formats
1-byte reading writing data transfer formats combined together further followed other data transfer format.
Example Reading Modify Writing Data Transfer (For Reading Writing Data from Address
DATA
Specifying FhSetting Address Pointer Transfer Format Register
DATA
Writing data address
Specifying FhSetting Reading data from Transfer address Format Address Pointer Register
Data transfer from host
Data transfer from RTCs
reading writing data transfer formats correspond settings transfer format register shown table below. Byte (1,0,0,0) (1,1,0,0) Burst (0,0,0,0) (0,1,0,0)
Writing data transfer Reading data transfer
R2033K(Preliminary) R2033T
Considerations Reading Writing Time Data under special condition
carry second digits process reading writing time data cause reading writing erroneous time data. example, suppose carry 13:59:59 into 14:00:00 occurs process reading time data middle shifting from minute digits hour digits. this moment, second digits, minute digits, hour digits read seconds, minutes, hours, respectively (indicating 14:59:59) cause reading time data deviating from actual time virtually hour. similar error also occurs writing time data. prevent such errors reading writing time data, R2033K/T function temporarily locking carry second digits during high interval unlocking such carry high transition. Note that carry second digits locked only second, during which time should driven low.
13:59:59 14:00:00 14:00:01
Actual time
Max.62µs
Time counts within
13:59:59
14:00:00
14:00:01
effective this function requires following considerations reading writing time data: Hold high each session reading writing time data. Ensure that high interval lasts within second. Should there possibility host going down process reading writing time data, make arrangements peripheral circuitry drive open moment that host actually goes down. Leave time span 31µs more from high transition start access addresses order that ongoing carry time digits completed within this time span. Leave time span 62µs more from high transition high transition order that ongoing carry time digits during high interval adjusted within this time span. considerations listed (1), (3), above required when process reading writing time data obviously free from carry time digits. (e.g. reading writing time data synchronization with periodic interrupt function level mode alarm interrupt function). Good examples reading writing time data illustrated next page.
R2033K(Preliminary) R2033T
Good Example
Time span 31µs more
address other than addresses permits immediate reading writing without requiring time span
Address Pointer Transfer Format Register
DATA
Reading from Address (control2)
DATA
Reading from Address (sec.)
DATA
Reading from Address (min.)
DATA
Reading from Address (hr.)
Example (Where once driven process reading time data)
31µs more 31µs more
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Address Pointer Transfer Format Register
Data
Reading from Address (min.)
Data
Reading from Address (hr.)
Example (Where time span less than 31µs left until start process writing time data)
Time span less than 31µs
Address Pointer Transfer Format Register
Data
Writing Address (contorl2)
Data
Writing Address (sec.)
Data
Writing Address (min.)
Data
Writing Address (hr.)
Example (Where time span less than 62µs left between adjacent processes reading time data)
Less than 62µs
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Address Pointer Transfer Format Register
Data
Reading from Address (sec.)
Data transfer from host
Data
Data transfer from RTCs
R2033K(Preliminary) R2033T
Configuration Oscillation Circuit Correction Time Count Deviations
Configuration Oscillation Circuit
Typical externally-equipped element X'tal 32.768kHz (R1=30k typ) (CL=6pF 8pF) Standard values internal elements CG,CD 10pF
OSCIN Oscillator Circuit OSCOUT
32kHz
oscillation circuit driven constant voltage approximately volts relative level input. such, configured generate oscillating waveform with peak-to-peak voltage order volts positive side input. Considerations Handling quartz crystal unit Generally, quartz crystal units have basic characteristics including equivalent series resistance (R1) indicating ease their oscillation load capacitance (CL) indicating degree their center frequency. Particularly, quartz crystal units intended R2033K/T recommended have typical value typical value 9pF. confirm these recommended values, contact manufacturers quartz crystal units intended these particular models. Considerations Installing Components around Oscillation Circuit Install quartz crystal unit closest possible vicinity real-time clock ICs. Avoid laying signal lines power lines vicinity oscillation circuit (particularly area marked above figure). Apply highest possible insulation resistance between OSCIN OSCOUT pins printed circuit board. Avoid using long parallel lines wire OSCIN OSCOUT pins. Take extreme care cause condensation, which leads various problems such oscillation halt. Other Relevant Considerations cannot recommend connecting external input 32.768-kHz clock pulses OSCIN pin. maintain stable characteristics quartz crystal unit, avoid driving other through 32.768-kHz clock pulses output from OSCOUT pin.
R2033K(Preliminary) R2033T
Measurement Oscillation Frequency
CLKC OSCIN OSCOUT 32KOUT 32768Hz Frequency Counter
R2033K/T configured generate 32.768-kHz clock pulses output from CLKOUT pin. frequency counter with (more preferably more digits order 1ppm recommended measurement oscillation frequency oscillation circuit.
Adjustment Oscillation frequency
oscillation frequency oscillation circuit adjusted varying procedures depending usage Model R2033K/T system into which they built allowable degree time count errors. flow chart below serves guide selecting optimum oscillation frequency adjustment procedure relevant system.
Start
32-kHz clock output?
Allowable time count precision order oscillation frequency variations crystal oscillator (*1) plus frequency variations (*2)? (*3)
Course
Course
32-kHz clock output without regard frequency precision Course Allowable time count precision order oscillation frequency variations crystal oscillator (*1) plus frequency variations (*2)? (*3)
Course
Generally, quartz crystal units commercial classified terms their center frequency depending their load capacitance (CL) further divided into ranks order ±10, ±20, ±50ppm depending degree their oscillation frequency variations. Basically, Model R2033K/T configured cause frequency variations order ±10ppm 25°C. Time count precision referred above flow chart applicable normal temperature actually affected temperature characteristics other properties quartz crystal units.
R2033K(Preliminary) R2033T
Course When time count precision each adjusted, quartz crystal unit intended that have value requiring presetting. quartz crystal unit subject frequency variations which selectable within allowable range time count precision. Several quartz crystal units RTCs should used find center frequency quartz crystal units method described "P29 Measurement Oscillation Frequency" then calculate appropriate oscillation adjustment value method described "P32 Oscillation Adjustment Circuit" writing this value R2033K/T. Course When time count precision each adjusted within oscillation frequency variations quartz crystal unit plus frequency variations real-time clock ICs, becomes necessary correct deviations time count each method described Oscillation Adjustment Circuit". Such oscillation adjustment provides quartz crystal units with wider range allowable settings their oscillation frequency variations their values. real-time clock quartz crystal unit intended that real-time clock should used find center frequency quartz crystal unit method described Measurement Oscillation Frequency" then confirm center frequency thus found fall within range adjustable oscillation adjustment circuit before adjusting oscillation frequency oscillation circuit. normal temperature, oscillation frequency oscillator circuit adjusted approximately ±0.5ppm. Course Course together with Course requires adjusting time count precision each well frequency 32.768-kHz clock pulses output from 32KOUT pin. Normally, oscillation frequency crystal oscillator intended RTCs should adjusted adjusting oscillation stabilizing capacitors connected both ends crystal oscillator. R2033K/T, which incorporate require adjusting oscillation frequency crystal oscillator through value. Generally, relationship between value values represented following equation: CD)/(CG where "CS" represents floating capacity printed circuit board. crystal oscillator intended R2033K/T recommended have value order 9pF. oscillation frequency should measured method described P.29 Measurement Oscillation Frequency crystal oscillator found have excessively high oscillation frequency (causing time count gain loss, respectively) should replaced with another having smaller greater value, respectively until another having optimum value selected. this case, settings disabling oscillation adjustment circuit (see P.32 Oscillation Adjustment Circui") should written oscillation adjustment register. Incidentally, high oscillation frequency crystal oscillator also adjusted adding external oscillation stabilization capacitor CGOUT or/and CDOUT illustrated diagram below.
CGOUT or/and CDOUT should have capacitance ranging from
OSCIN Oscillator Circuit 32kHz OSCOUT CDOUT CGOUT
R2033K(Preliminary) R2033T
However, adding CGOUT and/or CDOUT, Time keeping Voltage Current will worse, will hard oscillate. reference, data Time keeping voltage current when adding CGOUT=CDOUT=5pF shown table below. (Topt=-40 85°C, VSS=0v) Item Condition Min. TYP. MAX. UNITS Vclk Time Keeping CGout=CDout=5pF 1.15 Voltage Time Keeping VDD=3V, 0.55 1.20 Current SCLK, SIO, CLKC, INTR 32KOUT=OFF CGout=CDout=0pF Course necessary select crystal oscillator same manner Course well correct errors time count each same manner Course method described P.32 Oscillation Adjustment Circuit
R2033K(Preliminary) R2033T
Oscillation Adjustment Circuit
oscillation adjustment circuit used correct time count gain loss with high precision varying number 1-second clock pulses once seconds seconds. When Oscillation Adjustment Register R2033K/T varies number 1-second clock pulses once seconds. When R2033K/T varies number 1-second clock pulses once seconds. oscillation adjustment circuit disabled writing settings ("*" representing "1") bits oscillation adjustment circuit. Conversely, when such oscillation adjustment made, appropriate oscillation adjustment value calculated equation below writing oscillation adjustment circuit.
When Oscillation Frequency Higher Than Target Frequency (Causing Time Count Gain) When DEV=0: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.1) Oscillation frequency 3.051 10-6 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.0333) Oscillation frequency 1.017 10-6 (Oscillation Frequency Target Frequency)
Oscillation frequency: 32768 times frequency clock pulse output from INTR normal temperature manner described Measurement Oscillation Frequency". Target frequency: Desired frequency set. Generally, 32.768-kHz quartz crystal unit such temperature characteristics have highest oscillation frequency normal temperature. Consequently, quartz crystal unit recommended have target frequency settings order 32.768 32.76810 (+3.05ppm relative 32.768 kHz). Note that target frequency differs depending environment location where equipment incorporating expected operated. Oscillation adjustment value: Value that finally written bits Oscillation Adjustment Register represented 7-bit coded decimal notation. When Oscillation Frequency Equal Target Frequency (Causing Time Count neither Gain Loss) Oscillation adjustment value -64,
R2033K(Preliminary) R2033T
When Oscillation Frequency Lower Than Target Frequency (Causing Time Count Loss) When DEV=0: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 3.051 10-6 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 1.017 10-6 (Oscillation Frequency Target Frequency) Oscillation adjustment value calculations exemplified below oscillation frequency 32768.85Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32768.85 32768.05 0.1) (32768.85 3.051 10-6) (32768.85 32768.05) 9.001 this instance, write settings oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count gain represents distance from 01h. When setting Oscillation adjustment value (32768.85 32768.05 0.0333) (32768.85 1.017 10-6) (32768.85 32768.05) 25.00 this instance, write settings oscillation adjustment register. oscillation frequency 32762.22Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 3.051 10-6) (32762.22 32768.05) -58.325 represent oscillation adjustment value 7-bit coded decimal notation, subtract (3Ah) from (80h) obtain 46h. this instance, write settings (DEV,F6,F5,F4,F3,F2,F1,F0) (0,1,0,0,0,1,1,0) oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count loss represents distance from 80h. When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 1.017 10-6) (32762.22 32768.05) -174.97 -175 Oscillation adjustment value from Then, this case, Oscillation adjustment value range.
R2033K(Preliminary) R2033T
Difference between DEV=0 DEV=1 Difference between DEV=0 DEV=1 following, DEV=0 -189.2ppm 189.2ppm 3ppm DEV=1 -62ppm 63ppm 1ppm
Maximum value range Minimum resolution
Notes: following conditions completed, actual clock adjustment value could different from target adjustment value that oscillator adjustment function. Using oscillator adjustment function Access R2033K/T random, synchronized with external clock that relation R2033K/T, synchronized with periodic interrupt pulse mode. Access R2033K/T more than times each second average. more details, please contact Ricoh.
evaluate clock gain loss
oscillator adjustment circuit configured change time counts second basis settings oscillation adjustment register once seconds seconds. oscillation adjustment circuit does effect frequency 32768Hz-clock pulse output from CLKOUT pin. Therefore, after writing oscillation adjustment register, cannot measure clock error with probing CLKOUT clock pulses. measure clock error follows: Output clock pulse Pulse Mode with interrupt (0,0,x,x,0,0,1,1) Control Register address After setting oscillation adjustment register, clock period changes every 20seconds every seconds) like next page figure.
clock pulse times time
Measure interval with frequency counter. frequency counter with more digits recommended measurement. Calculate typical period from Calculate time error from
R2033K(Preliminary) R2033T
Power-on Reset, Oscillation Halt Sensing, Supply Voltage Monitoring
PON, VDET
power-on reset circuit configured reset control register1, clock adjustment register when power from oscillation halt sensing circuit configured record halt oscillation 32.768-kHz clock pulses. supply voltage monitoring circuit configured record drop supply voltage below threshold voltage 1.3v. Each function monitor bit. I.e. power-on reset circuit, oscillation halt sensing circuit, VDET supply voltage monitoring circuit. VDET bits activated "H". However, activated "L". VDET accept only writing accepts writing when power-up from VDET indefinite. functions these three monitor bits shown table below. Monitoring power-on reset function Address High only
Monitoring oscillation halt sensing function Address indefinite
Function
Address Activated When power from accept writing
VDET drop supply voltage below threshold voltage 1.3v Address High only
Both
relationship between PON, VDET shown table below.
VDET
Conditions supply voltage oscillation Halt oscillation, drop supply voltage below threshold voltage Halt oscillation drop supply voltage below threshold voltage, drop drop supply voltage below threshold voltage halt oscillation Drop supply voltage below threshold voltage halt oscillation Drop supply voltage
Condition oscillator, back-up status Halt oscillation cause condensation etc. Halt oscillation cause drop back-up battery voltage Normal condition
halt oscillation, drop back-up battery voltage Power-up from
R2033K(Preliminary) R2033T
Threshold voltage (1.6v 1.3v) 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (XST) Supply voltage monitor flag (VDET) VDET0 XST1 PON0 VDET0 XST1 PON1 VDET0 XST1 PON0
Internal initialization period sec.)
Internal initialization period sec.)
When control register DEV, WALE, DALE, /24, CLEN2 TEST, CT2, CT1, CT0, VDSL, VDET, CLEN1 CTFG, WAFG, DAFG bits reset oscillation adjustment register, control register control register also power-on from Considerations Using Oscillation Halt Sensing Circuit sure prevent oscillation halt sensing circuit from malfunctioning preventing following: Instantaneous power-down Condensation crystal oscillator On-board noise crystal oscillator Applying individual pins voltage exceeding their respective maximum ratings particular, note that fail presence applied supply voltage illustrated below such events backup battery installation. Further, give special considerations prevent excessive chattering oscillation halt sensing circuit.
R2033K(Preliminary) R2033T
Voltage Monitoring Circuit
supply monitoring circuit configured conduct sampling operation during interval 7.8ms second check drop supply voltage below threshold voltage 1.3v VDSL setting (the default setting) respectively, Control Register thus minimizing supply current requirements illustrated timing chart below. This circuit suspends sampling operation once VDET Control Register supply voltage monitor useful back-up battery checking.
1.6v 1.3v
Internal initialization period 2sec.)
7.8ms
Sampling timing supply voltage VDET Address PON0 VDET0 VDET0
R2033K(Preliminary) R2033T
Alarm Periodic Interrupt
R2033K/T incorporates alarm interrupt circuit periodic interrupt circuit that configured generate alarm signals periodic interrupt signals output from INTR described below. Alarm Interrupt Circuit alarm interrupt circuit configured generate alarm signals output from INTR which driven (enabled) upon occurrence match between current time read time counters (the day-of-week, hour, minute counters) alarm time preset alarm registers (the Alarm_W registers intended day-of-week, hour, minute digit settings Alarm_D registers intended hour minute digit settings). Periodic Interrupt Circuit periodic interrupt circuit configured generate either clock pulses pulse mode interrupt signals level mode output from INTR depending CT2, CT1, settings control register above types interrupt signals monitored flag bits (i.e. WAFG, DAFG, CTFG bits Control Register enabled disabled enable bits (i.e. WALE, DALE, CT2, CT1, bits Control Register listed table below. Flag bits WAFG Address DAFG Address CTFG Address Enable bits WALE Address DALE Address CT2=CT1=CT0=0 (These setting disable Periodic Interrupt) Address
Alarm_W Alarm_D Peridic interrupt
power-on, when WALE, DALE, CT2, CT1, bits Control Register INTR driven high (disabled). When types interrupt signals output simultaneously from INTR pin, output from INTR becomes waveform their negative logic.
Example: Combined Output INTR Under Control Alarm_D Periodic Interrupt
Alarm_D
Periodic Interrupt INTR
this event, which type interrupt signal output from INTR confirmed reading DAFG, CTFG settings Control Register
R2033K(Preliminary) R2033T
Alarm Interrupt
alarm interrupt circuit controlled enable bits (i.e. WALE DALE bits Control Register flag bits (i.e. WAFG DAFG bits Control Register enable bits used enable this circuit when disable when When intended reading, flag bits used monitor alarm interrupt signals. When intended writing, flag bits will cause event when will drive high (disable) alarm interrupt circuit when enable bits will affected even when flag bits this event, therefore, alarm interrupt circuit will continue function until driven (enabled) upon next occurrence match between current time preset alarm time. alarm function presetting desired alarm time alarm registers (the Alarm_W Registers day-of-week digit settings both Alarm_W Registers Alarm_D Registers hour minute digit settings) with WALE DALE bits once then Control Register Note that WALE DALE bits should once order disable alarm interrupt circuit upon coincidental occurrence match between current time preset alarm time process setting alarm function.
Interval (1min.) during which match between current time preset alarm time occurs
INTR
WALE1 current time WALE0 preset alarm time (DALE) (DALE)
WALE1 (DALE)
current time preset alarm time
INTR
WALE1 current time preset alarm time (DALE)
WAFG0 (DAFG)
current time preset alarm time
After setting WALE(DALW) Alarm registers current time, WALE(DALE) INTR will driven immediately, INTR will driven next alarm setting time.
R2033K(Preliminary) R2033T
Periodic Interrupt
Setting periodic selection bits (CT2 CT0) enables periodic interrupt CPU. There waveform modes: pulse mode level mode. pulse mode, output waveform duty cycle around 50%. level mode, output cyclically driven and, when CTFG output return High (OFF). Wave form mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Interrupt Cycle Falling Timing OFF(H) Fixed 2Hz(Duty50%) 1Hz(Duty50%) Once second (Synchronized with Second counter increment) Once minute seconds every Minute) Once hour minutes Seconds every hour) Once month hours, minutes, seconds first every month) (Default)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG INTR Approx. 92µs (Increment second counter) Rewriting second counter
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving INTR low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
R2033K(Preliminary) R2033T
CTFG INTR Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784ms. example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784ms.
32-kHz CLOCK OUTPUT
R2033K/T, 32.768-kHz clock pulses output from 32KOUT when either CLEN1 Control Register CLEN2 Control Register when CLKC high. condition satisfied, output low.
CLEN1 Address 0(Default) CLEN2 Address 0(Default)
CLKC input
32KOUT (CMOS push-pull output) Clock pulses
32KOUT output synchronized with CLEN1 CLEN2 CLKC settings illustrated timing chart below.
CLKC CLEN1 CLEN2 setting 32KOUT
Max.62.0µs
R2033K(Preliminary) R2033T
Typical Applications
Typical Power Circuit Configurations
Sample circuit configuration R1163xxx1B series regulator with reverse current protection circuit. should pull-up system power supply voltage, should connect system power supply VSS. Please select VOUT voltage equal power supply voltage that interfaces R2033K/T SRAM.
System Power Supply
VOUT
Install bypass capacitors high-frequency low-frequency applications parallel close vicinity R2033K/T.
R1163xxx1B SRAM etc. Primary Battery
Sample circuit configuration
OSCIN OSCOUT 32768Hz System power supply
Primary Battery
OSCIN OSCOUT 32768Hz
System power supply
Secondary Battery
R2033K(Preliminary) R2033T
Connection INTR
INTR follows N-channel open drain output logic contains protective diode power supply side. such, connected pull-up resistor 5.5v regardless supply voltage.
System power supply
INTR OSCIN OSCOUT 32768Hz
Backup power supply
Depending whether INTR used during battery backup, should connected pull-up resistor following different positions: Position left diagram when used during battery backup. Position left diagram when used during battery backup.
Connection 32KOUT
32KOUT CMOS output, supply voltage R2033K/T devices connected should same. When device powered down, 32KOUT output should disabled. When CLKC connected system power supply through pull-up resistor, pull-up resistor should 10k, 32KOUT should connect host device through resistor (approx. 10k)
CLKC 32KOUT
R3111 XXXXC
Power Supply CLKC 32KOUT
Power Supply
Approx.10K Back-up Power Supply Back-up Power supply
R2033K(Preliminary) R2033T
Typical Characteristics
Test circuit
OSCIN CGOUT 32768Hz OSCOUT CDOUT 32KOUT Frequency Counter
X'tal 32.768kHz (R1=50k typ) (CL=6pF 9pF) Topt 25°C Output pins Open
Timekeeping Current Supply Voltage (with 32kHz clock output) (Output=Open, Topt=25°C)
Timekeeping Current IDD(uA)
Timekeeping Current Supply Voltage (with 32kHz clock output) (Output=Open, Topt=25°C)
Timekeeping Current IDD(uA)
Supply Vlotage VDD(v)
Supply Voltage VDD(v)
(CGout, CDout)=(5pF, 5pF) (CGout, CDout)=(0pF, 0pF)
(CGout, CDout)=(5pF, 5pF)
(CGout, CDout)=(0pF, 0pF)
Access Current SCLK Clock Frequency (Output pins=Open, Topt=25°C, CGout=CDout=0pF)
Access Current IDD(uA)
Timekeeping Current Operating Temperature (Output pins=Open, CGout=CDout=0pF)
Timekeeping Current IDD(uA)
VDD=5v
VDD=3v
with 32kHz clock output
with 32kHz clock output
1000
Clock Frequency (kHz)
Operating Temperature Topt(Celcius)
R2033K(Preliminary) R2033T
Oscillation Frequency Deviation External CGout (VDD=3v, Topt=25°C, CGout=CDout=0pF standard)
Oscillation Frequency Deviation (ppm)
Oscillation Frequency Deviation Supply Voltage (Topt=25°C,VDD=3v standard)
Oscillation Frequency Deviation (ppm)
-100
CDout=0pF
CDout=5pF
Supply Voltage
External CGout (pF)
Oscillation Frequency Deviation Operating Temperature (VDD=3V, Topt=25°C standard)
Oscillation Frequency Deviation (ppm)
INTR pin) (Topt=25°C)
-100 -120 Operating TemperatureTopt(Celsius)
(mA)
VDD=5v VDD=3v VDD=1.5v
R2033K(Preliminary) R2033T
Typical Software-based Operations
Initialization Power-on
Start Power-on
PON=1?
VDET=0?
Oscillation Adjustment Register Control Register etc.
Warning Back-up Battery Run-down
After power-on from volt, start oscillation process internal initialization require time span 2seconds, that access should done after lapse this time span more. setting Control Register indicates power-on from backup battery from further details, "P.35 PON, VDET". This step required when supply voltage monitoring circuit used. This step involves ordinary initialization including Oscillation Adjustment Register interrupt cycle settings, etc.
Writing Time Calendar Data
When writing clock calendar counters, insert CE=L until times from second year have been written prevent error writing time. (Detailed "P.24 Reading Writing Time Data under special condition". writing second counter will reset divider units lower than second digits.
Write Time Counter Calendar Counter
R2033K/T also initialized power-on process writing time calendar data.
R2033K(Preliminary) R2033T
Reading Time Calendar Data
Ordinary Process Reading Time Calendar Data
When reading clock calendar counters, insert CE=L until times from second year have been read prevent error reading time. (Detailed "P.24 Reading Writing Time Data under special condition".
Read from Time Counter Calendar Counter
Basic Process Reading Time Calendar Data with Periodic Interrupt Function
Periodic Interrupt Cycle Selection Bits
This step intended select level mode waveform mode periodic interrupt function. This step must completed within second. This step intended CTFG Control Register cancel interrupt CPU.
Generate Interrupt
CTFG=1?
Read from Time Counter Calendar Counter
Other Interrupt Processes
Control Register (X1X1X011)
R2033K(Preliminary) R2033T
Applied Process Reading Time Calendar Data with Periodic Interrupt Function
Time data need read from time counters when used such ordinary purposes time count indication. This applied process used read time calendar data with substantial reductions load involved such reading. Time Indication "Day-of-Month, Day-of-week, Hour, Minute, Second" Format:
Control Register (XXXX0100) Control Register (X1X1X011)
This step intended select level mode waveform mode periodic interrupt function. This step must completed within sec. This step intended read time data from time counters only first session reading time data after writing time data. This step intended CTFG Control Register cancel interrupt CPU.
Generate interrupt Other interrupts Processes
CTFG=1?
Sec.=00?
Previous Min.,Hr., Day,and Day-of-week data
Read Min.,Hr.,Day, Day-of-week
Control Register (X1X1X011)
R2033K(Preliminary) R2033T
Interrupt Process
Periodic Interrupt Cycle Selection Bits
Periodic Interrupt
Generate Interrupt
CTFG=1?
Conduct Periodic Interrupt
Other Interrupt Processes
This step intended select level mode waveform mode periodic interrupt function. This step intended CTFG Control Register cancel interrupt CPU.
Control Register (X1X1X011)
R2033K(Preliminary) R2033T
Alarm Interrupt
WALE DALE0
Alarm Min., Hr., Day-of-week Registers
WALE DALE1
Generate Interrupt
WAFG DAFG=1?
Other Interrupt
Processes
Conduct Alarm Interrupt
This step intended once disable alarm interrupt circuit setting WALE DALE bits anticipation coincidental occurrence match between current time preset alarm time process setting alarm interrupt function. This step intended enable alarm interrupt function after completion alarm interrupt settings. This step intended once cancel alarm interrupt function writing settings "X,1,X, 1,X,1,0,1" "X,1,X,1,X,1,1,0" Alarm_W Registers Alarm_D Registers, respectively.
Control Register (X1X1X101)

wire interface Real-Time Clock EA-120-0505 R2033K(Preliminar

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