wire serial interface Real-Time Clock EA-124-0506 R2023K/T (
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OUTLINE
wire serial interface Real-Time Clock
EA-124-0506
R2023K/T (Preliminary)
R2023K/T CMOS real-time clock connected signal lines, SCL, SDA, configured perform serial transmission time calendar data CPU. periodic interrupt circuit configured generate interrupt signals with selectable interrupts ranging from seconds month. alarm interrupt circuits generate interrupt signals preset times. oscillation circuit driven under constant voltage, fluctuation oscillator frequency supply voltage small, time keeping current small (TYP. 0.45µA 3V). oscillation halt sensing circuit used judge validity internal data such events power-on; supply voltage monitoring circuit configured record drop supply voltage below selectable supply voltage monitoring threshold settings. 32.768kHz clock output function (CMOS output with control pin) intended output sub-clock pulses external microcomputer. oscillation adjustment circuit intended adjust time counts with high precision correcting deviations oscillation frequency crystal oscillator. Since package these TSSOP10G (4.0x2.9x1.0: R2023T) FFP12 (2.0x2.0x1.0: R2023K), high density mounting boards possible.
FEATURES
Minimum Timekeeping supply voltage TYP:0.66 5.5v (Worst: 1.00V 5.5v); power consumption 0.45µA VDD=3V (1.00µA MAX.) signal lines (SCL, SDA) required connection CPU. Time counters (counting hours, minutes, seconds) calendar counters (counting years, months, days, weeks) format) Interrupt circuit configured generate interrupt signals (with interrupts ranging from seconds month) provided with interrupt flag interrupt halt alarm interrupt circuits (Alarm_W week, hour, minute alarm settings Alarm_D hour minute alarm settings) With Power-on flag prove that power supply starts from 32-kHz clock output (CMOS push-pull output with control pin) Supply voltage monitoring circuit with supply voltage monitoring threshold settings Automatic identification leap years year 2099 Selectable 12-hour 24-hour mode settings High precision oscillation adjustment circuit Built-in oscillation stabilization capacitors Package TSSOP10G (4.0mm 2.9mm 1.0mm: R2023T) FFP12 (2.0mm 2.0mm 1.0mm: R2023K) CMOS process
R2023K/T (Preliminary)
CONFIGURATION
R2023T(TSSOP10G)
R2023K(FFP12)
OSCOUT OSCIN CLKC
32KOUT INTRB
OSCIN OSCOUT CLKC INTRA
INTRA INTRB
VIEW
VIEW
BLOCK DIAGRAM
32KOUT CLKC ALARM_W REGISTER (MIN,HOUR, WEEK) ALARM_D REGISTER (MIN,HOUR) VOLTAGE DETECT POWER_ON RESET
32kHz OUTPUT CONTROL
COMPARATOR_W
COMPARATOR_D OSCIN OSCOUT
DIVIDER CORREC -TION
TIME COUNTER
32KOUT
DETECT INTRA
ADDRESS DECODER
ADDRESS REGISTER
(VSS) (VSS)
CONTROL
INTRB
INTERRUPT CONTROL
SHIFT REGISTER
SELECTION GUIDE
Part Number designated follows: R2023K-E2 Part Number R2023a-bb Code Description Designation package. FFP12 TSSOP10G (Preliminary) Designation taping type. Only available.
R2023K/T (Preliminary)
DESCRIPTION
Symbol Item Serial Clock Line Serial Data Line Description used input clock pulses synchronizing input output data from pin. Allows maximum input voltage 5.5v regardless supply voltage. used input output data intended writing reading synchronization with pin. Allows maximum input voltage 5.5v regardless supply voltage. Nch. open drain output. INTRA used output alarm interrupt (Alarm_D) periodic interrupt signals CPU. Disabled power-on from N-channel open drain output. Allows maximum pull-up voltage 5.5v regardless supply voltage. INTRB used output alarm interrupt (Alarm_W) CPU. Disabled power-on from N-channel open drain output. Allows maximum pull-up voltage 5.5v regardless supply voltage. 32KOUT used output 32.768-kHz clock pulses. CMOS push-pull output. output disabled held when CLKC open, certain register setting. This enabled power-on from CLKC used control output 32KOUT pin. clock output disabled held when this open. Incorporated pull down register. OSCIN OSCOUT pins used connect 32.768-kHz crystal oscillator (with other oscillation circuit components built into R2023K/T). connected power supply. grounded.
INTRA
Interrupt Output
INTRB
Interrupt Output 32kHz Clock Output
32KOUT
CLKC
Clock Control
OSCIN OSCOUT (VSS)
Oscillation Circuit Input Output Positive/Negative Power Supply Input
Please connect ground line, connect lines.
R2023K/T (Preliminary)
ABSOLUTE MAXIMUM RATINGS
(VSS=0V) Symbol Topt Tstg Item Supply Voltage Input Voltage Output Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Name SCL, SDA, CLKC SDA, INTRA INTRB 32KOUT Topt 25°C Description -0.3 +6.5 -0.3 +6.5 -0.3 +6.5 -0.3 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol Vaccess Item Supply Voltage Name Power supply voltage interfacing with CGout,CDout=0pF *1), CGout,CDout=0pF *1), (VSS=0V, Topt=-40 +85°C) Min, Typ. Max. Unit 1.00 0.66 5.50 1.00
VCLK VCLKL VPUP
Time keeping Voltage Minimum Time keeping Voltage Oscillation Frequency Pull-up Voltage
32.768 INTRA INTRB SCL, CGout connected between OSCIN VSS, CDout connected between OSCOUT VSS. R2023K/T incorporates capacitors between OSCIN VSS, between OSCOUT VSS. Then normally, CGout CDout necessary. more detail, "P.31 oscillation frequency" Crystal oscillator: CL=6-9pF, R1=50K
R2023K/T (Preliminary)
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified: VSS=0V, VDD=3.0V, Topt=-40 +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=50k) Symbol Item Name Conditions Min. Input Voltage 0.8x SCL, SDA, VDD=1.7 5.5V CLKC -0.3 Input Voltage IOL1 IOL2 IOL3 ICLKC Output Current Output Current 32KOUT 32KOUT INTRA INTRB CLKC SDA, INTRA INTRB VO=5.5V VDD=5.5V VDD=3V, SCL=SDA=CLKC=0V 32KOUT=OFF OUTPUT=OPEN CGout=CDout=0pF Topt=-30 +70°C VOH=VDD-0.5V VOL=0.4V -1.0 0.35 Typ. Max. 0.2x -0.5 Unit
Input Leakage Current Pull-down Resister Input Leakage Current Output Off-state Current Time Keeping Current
VI=5.5V VDD=5.5V
1.00
0.45
1.00
Supply Voltage 1.45 1.60 1.75 Monitoring Voltage VDETL Supply Voltage 1.15 1.30 1.45 Topt=-30 +70°C Monitoring Voltage time keeping current when outputting 32.768kHz from 32KOUT pin, "P.46 TYPICAL CHARACTERISTICS". time keeping current when CGOUT, CDOUT equal 0pF, "P.31 oscillation frequency".
VDETH
R2023K/T (Preliminary)
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: VSS=0V,Topt=-40 +85°C Input Output Conditions: Item CondiUnit VDD2.5V VDD1.7V -bol Tions Min. Typ. Max. Min. Typ. Max. fSCL Clock Frequency tLOW Clock Time tHIGH Clock High Time tHD;STA Start Condition Hold Time tSU;STO Stop Condition Time tSU;STA Start Condition Time tSU;DAT Data Time tHD;DAT Data Hold Time tPL;DAT Stable Time After Falling tPZ;DAT Stable Time After Falling Rising Time 1000 (input) Falling Time (input) Spike Width that removed with Input Filter tRCV Recovery Time from Stop Condition Start Condition reading/writing timing, "P.29 Interfacing with Transmission under Special Conditions".
tLOW tHIGH tHD;STA
SDA(IN) tHD;STA tSU;DAT tHD;DAT tSU;STA
tSU;STO
SDA(OUT) tPL;DAT
tPZ;DAT
Start Condition Repeated Start Condition
Stop Condition
R2023K/T (Preliminary)
PACKAGE DIMENSIONS
R2023K
1PIN INDEX
0.05
2PIN INDEX 0.35 0.35 0.25 1.0Max
0.103
0.3±0.15
0.2±0.15
(BOTTOM VIEW) 0.17±0.1 0.27±0.15 2.0±0.1
unit:
2.0±0.1
R2023K/T (Preliminary)
R2023T
2.9±0.2
2.8±0.2
4.0±0.2
(0.75)
0.13 -0.05
+0.1
0.2±0.1 0.15
-0.05
+0.1
0.85±0.15
0.55±0.2
unit:
R2023K/T (Preliminary)
GENERAL DESCRIPTION
Interface with
R2023K/T connected signal lines, SDA, through which reads writes data from CPU. Since open drain, data interfacing with different supply voltage possible applying pull-up resistors circuit board. maximum clock frequency 400kHz VDD2.5v) enables data transfer fast mode.
Clock Calendar Function
R2023K/T reads writes time data from units ranging from seconds last digits calendar year. calendar year will automatically identified leap year when last digits multiple Consequently, leap years year 2099 automatically identified such. year 2000 leap year while year 2100 leap year.
Alarm Function
R2023K/T incorporates alarm interrupt circuit configured generate interrupt signals preset times. alarm interrupt circuit allows types alarm settings specified Alarm_W registers Alarm_D registers. Alarm_W registers allow week, hour, minute alarm settings including combinations multiple day-of-week settings such "Monday, Wednesday, Friday" "Saturday Sunday". Alarm_D registers allow hour minute alarm settings. Alarm_W outputs from INTRB pin, Alarm_D outputs from INTRA pin. Each alarm function checked from using polling function.
High-precision Oscillation Adjustment Function
R2023K/T built-in oscillation stabilization capacitors CD), which connected external crystal oscillator configure oscillation circuit. kinds accuracy this function alternatives. correct deviations oscillator frequency crystal, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm ±0.5ppm 25°C) from CPU. maximum range approximately ±189ppm ±63ppm) increments approximately 3ppm 1ppm). Such oscillation frequency adjustment each system following advantages: Allows timekeeping with much higher precision than conventional RTCs while using crystal oscillator with wide range precision variations. Corrects seasonal frequency deviations through seasonal oscillation adjustment. Allows timekeeping with higher precision particularly with temperature sensing function RTC, through oscillation adjustment tune with temperature fluctuations.
Power-on Reset, Oscillation Halt Sensing Function Supply Voltage Monitoring Function
R2023K/T incorporates oscillation halt sensing circuit equipped with internal registers configured record past oscillation halt. Power reset function reset control resisters when system powered from same time, fact memorized resister flag, thereby identifying whether they powered from battery backed-up. R2023K/T also incorporates supply voltage monitoring circuit equipped with internal registers configured record drop supply voltage below certain threshold value. Supply voltage monitoring threshold settings selected between 1.6V 1.3V through internal register settings. sampling rate normally oscillation halt sensing circuit power-on reset flag configured confirm established invalidation time data contrast supply voltage monitoring circuit intended confirm potential invalidation time data. Further, supply voltage monitoring circuit applied battery supply voltage monitoring.
R2023K/T (Preliminary)
Periodic Interrupt Function
R2023K/T incorporates periodic interrupt circuit configured generate periodic interrupt signals aside from interrupt signals generated alarm interrupt circuit output from INTRA pin. Periodic interrupt signals have five selectable frequency settings (once seconds), (once second), 1/60 (once minute), 1/3600 (once hour), monthly (the first every month). Further, periodic interrupt signals also have selectable waveforms, normal pulse form (with frequency special form adapted interruption from level mode (with second, minute, hour, month interrupts). condition periodic interrupt signals monitored with using polling function.
32kHz Clock Output
R2023K/T incorporates 32-kHz clock circuit configured generate clock pulses with oscillation frequency 32.768kHz crystal oscillator output from 32KOUT pin. 32KOUT CMOS push-pull output output enabled disabled when CLKC held high, open, respectively. 32-kHz clock output disabled certain register settings cannot disabled without manipulation registers with different addresses prevent disabling such events runaway CPU. 32-kHz clock circuit enabled power-on, when CLKC held high.
R2023K/T (Preliminary)
Address Mapping
Address A3A2A1A0 Control Register Control Register Register Name Second Counter Minute Counter Hour Counter Day-of-week Counter Day-of-month Counter Month Counter Century Year Counter Oscillation Adjustment Register Alarm_W (Minute Register) Alarm_W (Hour Register) Alarm_W (Day-of-week Register) Alarm_D (Minute Register) Alarm_D (Hour Register) WM40 WM20 WH20 MO10 WM10 WH10 Data
WALE VDSL
DM40 DALE VDET
DM20 DH20
DM10 DH10 CLEN2
TEST
WAFG
DAFG
CLEN1 CTFG
Notes: data listed above accept both reading writing. data marked with invalid writing reset reading. When Control Register bits reset Oscillation Adjustment Register, Control Register Control Register excluding bit. When DEV=0, oscillation adjustment circuit configured allow correction time count gain loss ±1.5ppm. When DEV=1, oscillation adjustment circuit configured allow correction time count gain loss ±0.5ppm. power-on-reset flag.
R2023K/T (Preliminary)
Register Settings
Control Register (ADDRESS
WALE DALE TEST (For Writing) CLEN2 WALE DALE TEST (For Reading) CLEN1 Default Settings Default settings: Default value means read written values when power-on from volts.
WALE, DALEAlarm_W Enable Bit, Alarm_D Enable
WALE,DALE Description Disabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers). Enabling alarm interrupt circuit (under control settings Alarm_W registers Alarm_D registers) (Default)
/24-hour Mode Selection Description Selecting 12-hour mode with a.m. p.m. indications. (Default) Selecting 24-hour mode Setting specifies 12-hour mode 24-hour mode, respectively.
24-hour mode 12-hour mode 24-hour mode (AM12) (AM10) (AM11) should precede writing time data Setting
12-hour mode (PM12) (PM10) (PM11)
CLEN2
32kHz Clock Output
Description CLEN2 Enabling 32-kHz clock circuit (Default) Disabling 32-kHz clock circuit Setting CLEN2 CLEN1 control register CLKC high specifies generating clock pulses with oscillation frequency 32.768-kHz crystal oscillator output from 32KOUT pin. Conversely, setting both CLEN1 CLEN2 CLKC specifies disabling ("L") such output.
TEST
Test
(Default)
TEST Description Normal operation mode. Test mode. TEST used only testing factory should normally
R2023K/T (Preliminary)
CT2, CT1,
Periodic Interrupt Selection Bits
Wave form mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Interrupt Cycle Falling Timing OFF(H) Fixed (Duty50%) (Duty50%) Once second (Synchronized with second counter increment) Once minute seconds every minute) Once hour minutes seconds every hour) Once month hours, minutes, seconds first every month) (Default)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG INTRA Approx. 92µs (Increment second counter) Rewriting second counter
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving INTRA low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
CTFG INTRA Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
R2023K/T (Preliminary)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. 60sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784 example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784
Control Register (Address
VDSL VDET VDSL VDET Default settings: CTFG WAFG DAFG (For Writing) CLEN1 CTFG WAFG DAFG (For Reading) CLEN1 Indefinite Default Settings Default value means read written values when power-on from volts.
VDSL
VDSL
Supply Voltage Monitoring Threshold Selection
(Default)
Description Selecting supply voltage monitoring threshold setting 1.6v. Selecting supply voltage monitoring threshold setting 1.3v. VDSL intended select supply voltage monitoring threshold settings.
VDET
VDET
Supply Voltage Monitoring Result Indication
Description Indicating supply voltage above supply voltage monitoring (Default) threshold settings. Indicating supply voltage below supply voltage monitoring threshold settings. Once VDET supply voltage monitoring circuit will disabled while VDET will hold setting VDET accepts only writing which restarts supply voltage monitoring circuit. Conversely, setting VDET causes event.
Oscillation Halt Sensing Monitor
Description Sensing halt oscillation Sensing normal condition oscillation accepts reading writing will when oscillation halt sensing. will hold even after restart oscillation.
Power-on-reset Flag
Description Normal condition Detecting power-on -reset sensing power-on reset condition.
(Default)
will when power-on from volts. will hold setting even after power-on. When bits will reset Oscillation Adjustment Register, Control Register Control Register except PON. result, INTR stops outputting.
R2023K/T (Preliminary)
accepts only writing Conversely, setting causes event.
R2023K/T (Preliminary)
CLEN1
32kHz Clock Output
Description CLEN1 Enabling 32-kHz clock circuit (Default) Disabling 32-kHz clock circuit Setting CLEN1 CLEN2 control register CLKC high specifies generating clock pulses with oscillation frequency 32.768-kHz crystal oscillator output from 32KOUT pin. Conversely, setting both CLEN1 CLEN2 CLKC specifies disabling ("L") such output.
CTFG
Periodic Interrupt Flag
CTFG Description Periodic interrupt output (Default) Periodic interrupt output CTFG when periodic interrupt signals output from INTRA ("L"). CTFG accepts only writing level mode, which disables ("H") INTRA until enabled ("L") again next interrupt cycle. Conversely, setting CTFG causes event.
WAFG,DAFG
Alarm_W Flag Alarm_D Flag
WAFG,DAFG Description Indicating mismatch between current time preset alarm time (Default) Indicating match between current time preset alarm time WAFG DAFG bits valid only when WALE DALE have setting which caused approximately 61µs after match between current time preset alarm time specified Alarm_W registers Alarm_D registers. WAFG (DAFG) accepts only writing INTRA INTRB outputs ("H") when this INTRA INTRB outputs again next preset alarm time. Conversely, setting WAFG DAFG bits causes event. WAFG DAFG bits will have reading when alarm interrupt circuit disabled with WALE DALE bits settings WAFG DAFG bits synchronized with output INTRA INTRB shown timing chart below.
Approx. 61µs WAFG(DAFG) INTRB (INTRA) Writing WAFG(DAFG) (Match between current time preset alarm time) (Match between current time preset alarm time) Writing WAFG(DAFG) (Match between current time preset alarm time) Approx. 61µs
R2023K/T (Preliminary)
Time Counter (Address 0-2h)
Second Counter (Address Indefi Indefi nite nite Minute Counter (Address Indefi Indefi nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Hour Counter (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. Time digit display (BCD format) follows: second digits range from carried minute digit transition from minute digits range from carried hour digits transition from hour digits range shown "P12 Control Register (ADDRESS /24: /24-hour Mode Selection Bit" carried day-of-month day-of-week digits transition from PM11 AM12 from writing second counter resets divider units less than second. carry from lower digits with writing non-existent time cause time counters malfunction. Therefore, such incorrect writing should replaced with writing existent time data.
Day-of-week Counter (Address
(For Writing) (For Reading) Indefi Indefi Indefi Default Settings nite nite nite Default value means read written values when power-on from volts.
Default settings:
day-of-week counter incremented when day-of-week digits carried day-of-month digits. Day-of-week display (incremented septimal notation): (W4, 1).(1,
R2023K/T (Preliminary)
Correspondences between days week day-of-week digits user-definable (e.g. Sunday writing (W4, prohibited except when days week unused.
Calendar Counter (Address 4-6h)
Day-of-month Counter (Address Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Month Counter Century (Address MO10 MO10 Indefi Indefi nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Year Counter (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. calendar counters configured display calendar digits format using automatic calendar function follows: day-of-month digits (D20 range from January, March, May, July, August, October, December; from April, June, September, November; from February leap years; from February ordinary years. day-of-month digits carried month digits reversion from last month month digits (MO10 MO1) range from carried year digits reversion from year digits (Y80 range from (00, leap years) carried digits reversion from digits cycle between reversion from year digits. carry from lower digits with writing non-existent calendar data cause calendar counters malfunction. Therefore, such incorrect writing should replaced with writing existent calendar data.
R2023K/T (Preliminary)
Oscillation Adjustment Register (Address
Default settings: (For Writing) (For Reading) Default Settings Default value means read written values when power-on from volts.
When Oscillation Adjustment Circuit operates seconds. When Oscillation Adjustment Circuit operates seconds. bits Oscillation Adjustment Circuit configured change time counts second basis settings Oscillation Adjustment Register timing DEV. Oscillation Adjustment Circuit will operate with same timing (00, seconds) timing writing Oscillation Adjustment Register. setting causes increment time counts ((F5, setting causes decrement time counts F5,F4,F3,F2,F1,F0 settings ("*" representing either "1") bits cause neither increment decrement time counts. Example: (DEV, when second digits read increment current time counts 32768 32780 current time count loss). (DEV, when second digits read neither increment decrement current time counts 32768. (DEV, when second digits read decrement current time counts 32768 32764 current time count gain). increase clock pulses once seconds causes time count loss approximately (32768 3.051 ppm). Conversely, decrease clock pulses once seconds causes time count gain ppm. Consequently, when "0", deviations time counts corrected with precision ±1.5 ppm. same way, when "1", deviations time counts corrected with precision ±0.5 ppm. Note that oscillation adjustment circuit configured correct deviations time counts oscillation frequency 32.768-kHz clock pulses. further details, "P34 Configuration Oscillation Circuit Correction Time Count Deviations Oscillation Adjustment Circuit".
R2023K/T (Preliminary)
Alarm_W Registers (Address 8-Ah)
Alarm_W Minute Register (Address WM40 WM20 WM10 WM40 WM20 WM10 Indefi Indefi Indefi nite nite nite Alarm_W Hour Register (Address WH20 WH10 WH10 WH20 Indefi Indefi nite nite
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Indefi nite
Indefi nite
Indefi nite
Indefi nite
(For Writing) (For Reading) Default Settings
Alarm_W Day-of-week Register (Address (For Writing) (For Reading) Indefi Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. Alarm_W Hour Register represents when 12-hour mode selected a.m. p.m.) WH20 when 24-hour mode selected (tens hour digits). Alarm_W Registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_W registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read a.m. p.m., respectively. (See "P12 Register (ADDRESS /24: /24-hour Mode Selection Bit") correspond day-of-week counter with settings ranging from with respective settings disable outputs Alarm_W Registers.
R2023K/T (Preliminary)
Example Alarm Time Setting Alarm Day-of-week Preset alarm Sun. Mon. Tue. Wed. time
Fri.
Sat.
12-hour mode
24-hour mode
00:00 a.m. days 01:30 a.m. days 11:59 a.m. days 00:00 p.m. Mon. Fri. 01:30 p.m. Sun. 11:59 p.m. Mon. ,Wed., Fri. Note that correspondence between days week shown above table only example mandatory.
Alarm_D Register (Address B-Ch)
Alarm_D Minute Register (Address DM40 DM20 DM10 DM40 DM20 DM10 Indefinit Indefinit Indefinit
Indefinit
Indefinit
Indefinit
Indefinit
(For Writing) (For Reading) Default Settings
Alarm_D Hour Register (Address DH20 DH10 (For Writing) DH10 (For Reading) DH20 Indefi Indefi Indefi Indefi Indefi Indefi Default Settings nite nite nite nite nite nite Default settings: Default value means read written values when power-on from volts. represents when 12-hour mode selected a.m. p.m.) DH20 when 24-hour mode selected (tens hour digits). Alarm_D registers should have non-existent alarm time settings. (Note that mismatch between current time preset alarm time specified Alarm_D registers disable alarm interrupt circuit.) When 12-hour mode selected, hour digits read 0a.m. 0p.m., respectively. (See "P12 Register (ADDRESS /24: /24-hour Mode Selection Bit")
R2023K/T (Preliminary)
Interfacing with
R2023K/T employs I2C-Bus system connected 2-wires. I2C-Bus described following sections. Connection system
Connection I2C-Bus
2-wires, pins that connected I2C-Bus used transmit clock pulses data respectively. that connected these lines designed that will clamped when voltage beyond supply voltage applied input output pins. Open drain pins used output. This construction allows communication signals between with different supply voltages adding pull-up resistor each signal line shown figure below. Each designed affect signal lines when power each these turned separately.
VDD1 VDD2 VDD3 VDD4
data interface, following conditions must met: VCC4VCC1 VCC4VCC2 VCC4VCC3 When master one, micro-controller ready driving required.
MicroController
R2023K/T
Other Peripheral Device
Cautions determining resistance, Dropping voltage input current output current conditions each connected I2C-Bus shall adequately small. Rising time each signal kept short even when capacity driven. Current consumed I2C-Bus small compared consumption current permitted entire system. When connected I2C-Bus CMOS type, condition usually ignored since input current off-state output current extremely small many CMOS type ICs. Thus maximum resistance determined based (2), while minimum most cases. actual cases resistor place between input/output pins each improve noise margins which case minimum value determined resistance. Consumption current review above expressed formula below: consumption current (Sum input current state output current devices standby mode standby duration stand-by duration operation duration Supply voltage operation duration resistance (Bus stand-by duration operation duration)
Supply voltage capacity Charging/Discharging times unit time Operation second member denominator above formula derived from assumption that
R2023K/T (Preliminary)
duration pins half operation duration. numerator same member because there pins SCL. third member, (charging/discharging times unit time) means number transition from signal line.
Calculation example shown below: Pull-up resistor (Rp) 10k, capacity 50pF(both SCL, SDA), VDD=3V, system with input current off-state output current each 0.1µA, I2C-Bus used 10ms every second while rest 990ms stand-by mode, this mode, number transitions from state while every second. consumption current 990msec 10msec 10msec (990msec 10msec)
50pF (100 0.099µA 3.0µA 0.0225µA 3.12µA Generally, second member above formula larger enough than first third members consumption current determined second member many cases.
R2023K/T (Preliminary)
Transmission System I2C-Bus
Start Condition Stop Condition
I2C-Bus, must kept certain state while state during data transmission shown below.
tHD;DAT
tSU;DAT
pins level when data transmission made. Changing from when activates Start Condition access started. Changing from when activates Stop Condition accessing stopped. Generation Start Stop Conditions always made master (see figure below).
Start Condition Stop Condition
tHD;STA
tSU;STO
Data transmission acknowledge
After Start condition entered, data transmitted 1byte (8bits). bytes data serially transmitted. receiving side will send acknowledge signal transmission side each time 8bit data transmitted. acknowledge signal sent immediately after falling 8bit clock pulses data transmitted, releasing transmission side that asserted that time turning receiving side. When transmission 1byte data next preceding 1byte data received receiving side releases falling edge 9bit clock pulses when receiving side switches transmission side starts data transmission. When master receiving side, generates acknowledge signal after last 1byte data from slave tell transmitter that data transmission completed. slave side (transmission side) continues release that master will able generate Stop Condition, after falling edge 9bit clock pulses.
from master from transmission side from receiving side Start Condition Acknowledge signal
R2023K/T (Preliminary)
Data Transmission Format I2C-Bus
I2C-Bus chip enable signal line. place each device 7bit Slave Address allocated. first 1byte allocated this 7bit address command (R/W) which data transmission direction designated data transmission thereafter. 7bit address sequentially transmitted from after bytes read, when 8bit when write "L". Slave Address R2023K/T specified (0110010). data transmission receiving, Stop Condition generated complete transmission. However, start condition generated without generating Stop Condition, Repeated Start Condition transmission receiving data continue setting Slave Address again. this procedure when transmission direction needs change during transmission.
Data written slave from master Slave Address (0110010) When data read from slave immediately after 7bit addressing from master Slave Address (0110010) When transmission direction changed during transmission.
Slave Address (0110010)
R/W=0(Write) R/W=1(Read)
Data
Data
Data
Data
Inform read been completed generate acknowledge signal slave side.
R/W=0(Write)
Data
Salve Address
(0110010) Data
R/W=1(Read)
Data
Inform read been completed generate acknowledge signal slave side.
Master slave Start Condition
Slave master Stop Condition
Acknowledge Signal
Repeated Start Condition
R2023K/T (Preliminary)
Data Transmission Write Format R2023K/T
Although I2C-Bus standard defines transmission format slave allocated each transmission method address information defined. R2023K/T transmits data internal address pointer (4bit) Transmission Format Register (4bit) 1byte next which transmitted Slave Address write command. write operation only transmission format available (0000) Transmission Format Register. 3byte transmits data address specified internal address pointer written 2byte. Internal address pointer setting automatically incremented 4byte after. Note that when internal address pointer will change transmitting next byte.
Example data writing (When writing internal address
R/W=0(Write) Slave Address (0110010) Address Transmission Pointer Format Register
Data Writing data internal address
Data Writing data internal address
Master slave Start Condition Acknowledge signal
Slave master Stop Condition
R2023K/T (Preliminary)
Data transmission read format R2023K/T
R2023K/T allows following three read method data internal register. first method reading data from internal register specify internal address setting internal address pointer transmission format register described (4), generate Repeated Start Condition (See (3)) change data transmission direction perform reading. internal address pointer when Stop Condition met. Therefore, this method reading allows insertion Stop Condition before Repeated Start Condition. Transmission Format Register when this method used.
Example Data Read (when data read from
R/W=0(Write) Repeated Start Condition R/W=1(Read)
Slave Address (0110010) Address Transmission Pointer2h Format
Register0h
Slave Address (0110010)
Data Reading data from internal address
Data Reading data from internal address
Data Reading data from internal address
Master slave Start Condition Acknowledge signal
Slave master Repeated Start Condition Stop Condition
R2023K/T (Preliminary)
second method reading data from internal register start reading immediately after writing Internal Address Pointer Transmission Format Register. Although this method based I2C-Bus standard strict sense still effective shorten read time ease load master. transmission format register when this method used.
Example data read (when data read from internal addresses
R/W=0(Write) Slave Address (0110010) Address Transmission Pointer Format Register4h Data Reading data from internal address
Data Reading data from internal address
Data Reading data from internal address
Data Reading data from internal address
Master slave Start Condition Acknowledge Signal
Slave Master Stop Condition
third method reading data from internal register start reading immediately after writing Slave Address bit. Since Internal Address Pointer default described first method, this method only effective when reading started from Internal Address
Example data read (when data read from internal addresses
R/W=1(Read) Slave Address (0110010) Data Reading data from Internal Address Data Reading data from Internal Address
Data Reading data from Internal Address
Data Reading data from Internal Address
Data Reading data from Internal Address
Master slave Start Condition Acknowledge Signal
Slave master Stop Condition
R2023K/T (Preliminary)
Data Transmission under Special Condition
R2023K/T holds clock tentatively duration from Start Condition avoid invalid read write clock carrying clock. When clock carried during this period, which will adjusted within approx. 61µs from Stop Condition. prevent invalid read write, clock calendar data shall made during transmission operation (from Start Condition Stop Condition). When second elapses after Start Condition, access R2023K/T automatically released release tentative hold clock, access from forced terminated (The same action made Stop Condition received: automatic resume function from I2C-Bus interface). Therefore, access must complete within seconds. automatic resume function prevents delay clock even stopped from sudden failure system during clock read operation. Also second Start Condition after first Start Condition before Stop Condition regarded "Repeated Start Condition". Therefore, when seconds passed after first Start Condition, access R2023K/T automatically released. access tried after automatic resume function activated, acknowledge signal will output writing while will output reading. user shall always able access real-time clock long three conditions met. Stop Condition shall generated until clock calendar data read/write started completed. cycle read/write operation shall complete within seconds. make Start Condition within 61µs from Stop Condition. When clock carried during access, which will adjusted within approx. 61µs from Stop Condition. example reading from seconds hours (invalid read) (Start Condition) (Read seconds) (Read minutes) (Stop Condition) (Start Condition) (Read hour) (Stop Condition) Assuming read started 05:59:59 P.M. while reading seconds minutes time advanced 06:00:00 P.M. this time second digit hold read read 05:59:59. Then R2023K/T confirms (Stop Condition) carries second digit being hold time change 06:00:00 P.M. Then, when hour digit read, changes wrong results 06:59:59 will read.
R2023K/T (Preliminary)
Configuration Oscillation Circuit Correction Time Count Deviations
Configuration Oscillation Circuit
Typical externally-equipped element X'tal 32.768kHz (R1=50k typ) (CL=6pF 9pF) Standard values internal elements CG,CD 10pF
OSCIN Oscillator Circuit OSCOUT
32kHz
oscillation circuit driven constant voltage approximately volts relative level input. such, configured generate oscillating waveform with peak-to-peak voltage order volts positive side input. Considerations Handling quartz crystal unit Generally, quartz crystal units have basic characteristics including equivalent series resistance (R1) indicating ease their oscillation load capacitance (CL) indicating degree their center frequency. Particularly, quartz crystal units intended R2023K/T recommended have typical value typical value 9pF. confirm these recommended values, contact manufacturers quartz crystal units intended these particular models. Considerations Installing Components around Oscillation Circuit Install quartz crystal unit closest possible vicinity real-time clock ICs. Avoid laying signal lines power lines vicinity oscillation circuit (particularly area marked above figure). Apply highest possible insulation resistance between OSCIN OSCOUT pins printed circuit board. Avoid using long parallel lines wire OSCIN OSCOUT pins. Take extreme care cause condensation, which leads various problems such oscillation halt. Other Relevant Considerations cannot recommend connecting external input 32.768-kHz clock pulses OSCIN pin. maintain stable characteristics quartz crystal unit, avoid driving other through 32.768-kHz clock pulses output from OSCOUT pin.
R2023K/T (Preliminary)
Measurement Oscillation Frequency
CLKC OSCIN OSCOUT 32KOUT 32768Hz Frequency Counter
R2023K/T configured generate 32.768-kHz clock pulses output from 32KOUT pin. frequency counter with (more preferably more digits order 1ppm recommended measurement oscillation frequency oscillation circuit.
Adjustment Oscillation frequency
oscillation frequency oscillation circuit adjusted varying procedures depending usage Model R2023K/T system into which they built allowable degree time count errors. flow chart below serves guide selecting optimum oscillation frequency adjustment procedure relevant system.
Start
32-kHz clock output?
Allowable time count precision order oscillation frequency variations crystal oscillator (*1) plus frequency variations (*2)? (*3)
Course
Course
32-kHz clock output without regard frequency precision Course Allowable time count precision order oscillation frequency variations crystal oscillator (*1) plus frequency variations (*2)? (*3)
Course
Generally, quartz crystal units commercial classified terms their center frequency depending their load capacitance (CL) further divided into ranks order ±10, ±20, ±50ppm depending degree their oscillation frequency variations. Basically, Model R2023K/T configured cause frequency variations order ±10ppm 25°C. Time count precision referred above flow chart applicable normal temperature actually affected temperature characteristics other properties quartz crystal units.
R2023K/T (Preliminary)
Course When time count precision each adjusted, quartz crystal unit intended that have value requiring presetting. quartz crystal unit subject frequency variations which selectable within allowable range time count precision. Several quartz crystal units RTCs should used find center frequency quartz crystal units method described "P31 Measurement Oscillation Frequency" then calculate appropriate oscillation adjustment value method described "P34 Oscillation Adjustment Circuit" writing this value R2023K/T. Course When time count precision each adjusted within oscillation frequency variations quartz crystal unit plus frequency variations real-time clock ICs, becomes necessary correct deviations time count each method described Oscillation Adjustment Circuit". Such oscillation adjustment provides quartz crystal units with wider range allowable settings their oscillation frequency variations their values. real-time clock quartz crystal unit intended that real-time clock should used find center frequency quartz crystal unit method described Measurement Oscillation Frequency" then confirm center frequency thus found fall within range adjustable oscillation adjustment circuit before adjusting oscillation frequency oscillation circuit. normal temperature, oscillation frequency oscillator circuit adjusted approximately ±0.5ppm. Course Course together with Course requires adjusting time count precision each well frequency 32.768-kHz clock pulses output from 32KOUT pin. Normally, oscillation frequency crystal oscillator intended RTCs should adjusted adjusting oscillation stabilizing capacitors connected both ends crystal oscillator. R2023K/T, which incorporate require adjusting oscillation frequency crystal oscillator through value. Generally, relationship between value values represented following equation: CD)/(CG where "CS" represents floating capacity printed circuit board. crystal oscillator intended R2023K/T recommended have value order 9pF. oscillation frequency should measured method described P.31 Measurement Oscillation Frequency crystal oscillator found have excessively high oscillation frequency (causing time count gain loss, respectively) should replaced with another having smaller greater value, respectively until another having optimum value selected. this case, settings disabling oscillation adjustment circuit (see P.34 Oscillation Adjustment Circui") should written oscillation adjustment register. Incidentally, high oscillation frequency crystal oscillator also adjusted adding external oscillation stabilization capacitor CGOUT or/and CDOUT illustrated diagram below.
CGOUT or/and CDOUT should have capacitance ranging from
OSCIN Oscillator Circuit 32kHz OSCOUT CDOUT CGOUT
R2023K/T (Preliminary)
However, adding CGOUT and/or CDOUT, Time keeping Voltage Current will worse, will hard oscillate. reference, data Time keeping voltage current when adding CGOUT=CDOUT=5pF shown table below. (Topt=-40 85°C, VSS=0v) Item Condition Min. TYP. MAX. UNITS Vclk Time Keeping CGout=CDout=5pF 1.15 Voltage Time Keeping VDD=3V, Current SCL, SDA, CLKC=0V 0.55 1.20 32KOUT=OPEN OUTPUT=OPEN CGout=CDout=0pF Course necessary select crystal oscillator same manner Course well correct errors time count each same manner Course method described P.34 Oscillation Adjustment Circuit
R2023K/T (Preliminary)
Oscillation Adjustment Circuit
oscillation adjustment circuit used correct time count gain loss with high precision varying number 1-second clock pulses once seconds seconds. When Oscillation Adjustment Register R2023K/T varies number 1-second clock pulses once seconds. When R2023K/T varies number 1-second clock pulses once seconds. oscillation adjustment circuit disabled writing settings ("*" representing "1") bits oscillation adjustment circuit. Conversely, when such oscillation adjustment made, appropriate oscillation adjustment value calculated equation below writing oscillation adjustment circuit.
When Oscillation Frequency Higher Than Target Frequency (Causing Time Count Gain)
When DEV=0: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.1) Oscillation frequency 3.051 10-6 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (*3) (Oscillation frequency Target Frequency 0.0333) Oscillation frequency 1.017 10-6 (Oscillation Frequency Target Frequency)
Oscillation frequency: Frequency clock pulse output from 32KOUT normal temperature manner described Measurement Oscillation Frequency". Target frequency: Desired frequency set. Generally, 32.768-kHz quartz crystal unit such temperature characteristics have highest oscillation frequency normal temperature. Consequently, quartz crystal unit recommended have target frequency settings order 32.768 32.76810 (+3.05ppm relative 32.768 kHz). Note that target frequency differs depending environment location where equipment incorporating expected operated. Oscillation adjustment value: Value that finally written bits Oscillation Adjustment Register represented 7-bit coded decimal notation.
When Oscillation Frequency Equal Target Frequency (Causing Time Count neither Gain Loss)
Oscillation adjustment value -64,
When Oscillation Frequency Lower Than Target Frequency (Causing Time Count Loss)
When DEV=0: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 3.051 10-6 (Oscillation Frequency Target Frequency) When DEV=1: Oscillation adjustment value (Oscillation frequency Target Frequency) Oscillation frequency 1.017 10-6 (Oscillation Frequency Target Frequency)
R2023K/T (Preliminary)
Oscillation adjustment value calculations exemplified below oscillation frequency 32768.85Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32768.85 32768.05 0.1) (32768.85 3.051 10-6) (32768.85 32768.05) 9.001 this instance, write settings oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count gain represents distance from 01h. When setting Oscillation adjustment value (32768.85 32768.05 0.0333) (32768.85 1.017 10-6) (32768.85 32768.05) 25.00 this instance, write settings oscillation adjustment register. oscillation frequency 32762.22Hz target frequency 32768.05Hz When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 3.051 10-6) (32762.22 32768.05) -58.325 represent oscillation adjustment value 7-bit coded decimal notation, subtract (3Ah) from (80h) obtain 46h. this instance, write settings (DEV,F6,F5,F4,F3,F2,F1,F0) (0,1,0,0,0,1,1,0) oscillation adjustment register. Thus, appropriate oscillation adjustment value presence time count loss represents distance from 80h. When setting Oscillation adjustment value (32762.22 32768.05) (32762.22 1.017 10-6) (32762.22 32768.05) -174.97 -175 Oscillation adjustment value from range. Then, this case, Oscillation adjustment value
Difference between DEV=0 DEV=1
Difference between DEV=0 DEV=1 following, DEV=0 -189.2ppm 189.2ppm 3ppm DEV=1 63ppm
Maximum value range Minimum resolution
-62ppm 1ppm
Notes: Oscillation adjustment circuit does affect frequency 32.768-kHz clock pulses output from 32KOUT pin. following conditions completed, actual clock adjustment value could different from target adjustment value that oscillator adjustment function.
R2023K/T (Preliminary)
Using oscillator adjustment function Access R2023K/T random, synchronized with external clock that relation R2023K/T, synchronized with periodic interrupt pulse mode. Access R2023K/T more than times each second average. more details, please contact Ricoh.
evaluate clock gain loss
oscillator adjustment circuit configured change time counts second basis settings oscillation adjustment register once seconds seconds. oscillation adjustment circuit does effect frequency 32768Hz-clock pulse output from 32KOUT pin. Therefore, after writing oscillation adjustment register, cannot measure clock error with probing 32KOUT clock pulses. measure clock error follows: Output clock pulse Pulse Mode with interrupt (0,0,x,x,0,0,1,1) Control Register address After setting oscillation adjustment register, clock period changes every 20seconds every seconds) like next page figure.
clock pulse times time
Measure interval with frequency counter. recommended measurement. Calculate typical period from Calculate time error from
frequency counter with more digits
R2023K/T (Preliminary)
Power-on Reset, Oscillation Halt Sensing, Supply Voltage Monitoring
PON, XST, VDET
power-on reset circuit configured reset control register1, clock adjustment register when power from oscillation halt sensing circuit configured record halt oscillation 32.768-kHz clock pulses. supply voltage monitoring circuit configured record drop supply voltage below threshold voltage 1.3V. Each function monitor bit. I.e. power-on reset circuit, oscillation halt sensing circuit, VDET supply voltage monitoring circuit. VDET bits activated "H". However, activated "L". VDET accept only writing accepts writing when power-up from VDET indefinite. functions these three monitor bits shown table below. Monitoring power-on reset function Address High only
Monitoring oscillation halt sensing function Address Indefinite
Function
Address Activated When power from accept writing
VDET drop supply voltage below threshold voltage 1.3V Address High only
Both
relationship between PON, VDET shown table below.
VDET
Conditions supply voltage oscillation Halt oscillation, drop supply voltage below threshold voltage Halt oscillation drop supply voltage below threshold voltage, drop drop supply voltage below threshold voltage halt oscillation Drop supply voltage below threshold voltage halt oscillation Drop supply voltage
Condition oscillator, back-up status Halt oscillation cause condensation etc. Halt oscillation cause drop back-up battery voltage Normal condition
halt oscillation, drop back-up battery voltage Power-up from
R2023K/T (Preliminary)
Threshold voltage (2.1V 1.35V) 32768Hz Oscillation Power-on reset flag (PON) Oscillation halt sensing flag (XST) supply voltage monitor flag (VDET) VDET0 XST1 PON0 VDET0 XST1 PON1 VDET0 XST1 PON0
Internal initialization period sec.)
Internal initialization period sec.)
When control register DEV, WALE, DALE, /24, CLEN2 TEST, CT2, CT1, CT0, VDSL, VDET, CLEN1 CTFG, WAFG, DAFG bits reset oscillation adjustment register, control register control register also power-on from volts. Considerations Using Oscillation Halt Sensing Circuit sure prevent oscillation halt sensing circuit from malfunctioning preventing following: Instantaneous power-down Condensation quartz crystal unit On-board noise quartz crystal unit Applying individual pins voltage exceeding their respective maximum ratings particular, note that fail presence applied supply voltage illustrated below such events backup battery installation. Further, give special considerations prevent excessive chattering oscillation halt sensing circuit.
R2023K/T (Preliminary)
Voltage Monitoring Circuit
supply monitoring circuit configured conduct sampling operation during interval 7.8ms second check drop supply voltage below threshold voltage 1.3v VDSL setting (the default setting) respectively, Control Register thus minimizing supply current requirements illustrated timing chart below. This circuit suspends sampling operation once VDET Control Register supply voltage monitor useful back-up battery checking.
1.6v 1.3v
Internal initialization period 2sec.)
7.8ms
Sampling timing supply voltage VDET Address PON0 VDET0 VDET0
R2023K/T (Preliminary)
Alarm Periodic Interrupt
R2023K/T incorporates alarm interrupt circuit periodic interrupt circuit that configured generate alarm signals periodic interrupt signals output from INTRA INTRB described below. Alarm Interrupt Circuit alarm interrupt circuit configured generate alarm signals output from INTRA INTRB which driven (enabled) upon occurrence match between current time read time counters (the day-of-week, hour, minute counters) alarm time preset alarm registers (the Alarm_W registers intended day-of-week, hour, minute digit settings Alarm_D registers intended hour minute digit settings). Alarm_W output from INTRB pin, Alarm_D output from INTRA pin. Periodic Interrupt Circuit periodic interrupt circuit configured generate either clock pulses pulse mode interrupt signals level mode output from INTRA depending CT2, CT1, settings control register above types interrupt signals monitored flag bits (i.e. WAFG, DAFG, CTFG bits Control Register enabled disabled enable bits (i.e. WALE, DALE, CT2, CT1, bits Control Register listed table below. Flag bits WAFG Address DAFG Address CTFG Address Enable bits WALE Address DALE Address CT2=CT1=CT0=0 (These setting disable Periodic nterrupt) Address Output INTRB
Alarm_W
Alarm_D
INTRA
Peridic interrupt
INTRA
power-on, when WALE, DALE, CT2, CT1, bits Control Register INTRA INTRB driven high (disabled). When types interrupt signals output simultaneously from INTRA pin, output from INTRA becomes waveform their negative logic.
Example: Combined Output INTRA Under Control ALARM_D Periodic Interrupt Alarm_D Periodic Interrupt INTRA
this event, which type interrupt signal output from INTRA confirmed reading DAFG, CTFG settings Control Register
Alarm Interrupt
alarm interrupt circuit controlled enable bits (i.e. WALE DALE bits Control Register flag bits (i.e. WAFG DAFG bits Control Register enable bits used enable
R2023K/T (Preliminary)
this circuit when disable when When intended reading, flag bits used monitor alarm interrupt signals. When intended writing, flag bits will cause event when will drive high (disable) alarm interrupt circuit when enable bits will affected even when flag bits this event, therefore, alarm interrupt circuit will continue function until driven (enabled) upon next occurrence match between current time preset alarm time. alarm function presetting desired alarm time alarm registers (the Alarm_W Registers day-of-week digit settings both Alarm_W Registers Alarm_D Registers hour minute digit settings) with WALE DALE bits once then Control Register Note that WALE DALE bits should once order disable alarm interrupt circuit upon coincidental occurrence match between current time preset alarm time process setting alarm function.
Interval (1min.) during which match between current time preset alarm time occurs
INTRB (INTRA)
WALE1 current time WALE0 preset alarm time (DALE) (DALE) WALE1 (DALE) current time preset alarm time
INTRB (INTRA)
WALE1 current time preset alarm time (DALE) WAFG0 (DAFG) current time preset alarm time
After setting WALE(DALW) Alarm registers current time, WALE(DALE) INTRB INTRA will driven immediately, INTRB INTRA will driven next alarm setting time.
Periodic Interrupt
Setting periodic selection bits (CT2 CT0) enables periodic interrupt CPU. There waveform modes: pulse mode level mode. pulse mode, output waveform duty cycle around 50%. level mode, output cyclically driven and, when CTFG output return High (OFF). Wave form mode Pulse Mode Pulse Mode Level Mode Level Mode Level Mode Level Mode Description Interrupt Cycle Falling Timing OFF(H) Fixed 2Hz(Duty50%) 1Hz(Duty50%) Once second (Synchronized with Second counter increment) Once minute seconds every Minute) Once hour minutes Seconds every hour) Once month hours, minutes, seconds first every month) (Default)
R2023K/T (Preliminary)
Pulse Mode: 2-Hz 1-Hz clock pulses output synchronization with increment second counter illustrated timing chart below.
CTFG INTRA Approx. 92µs (Increment second counter) Rewriting second counter
pulse mode, increment second counter delayed approximately from falling edge clock pulses. Consequently, time readings immediately after falling edge clock pulses appear behind time counts real-time clocks approximately second. Rewriting second counter will reset other time counters less than second, driving INTRA low. Level Mode: Periodic interrupt signals output with selectable interrupt cycle settings second, minute, hour, month. increment second counter synchronized with falling edge periodic interrupt signals. example, periodic interrupt signals with interrupt cycle setting second output synchronization with increment second counter illustrated timing chart below.
CTFG INTRA Setting CTFG (Increment second counter) (Increment second counter) Setting CTFG (Increment second counter)
*1), When oscillation adjustment circuit used, interrupt cycle will fluctuate once 20sec. follows: Pulse Mode: period output pulses will increment decrement maximum ±3.784ms. example, 1-Hz clock pulses will have duty cycle ±0.3784%. Level Mode: periodic interrupt cycle second will increment decrement maximum ±3.784
R2023K/T (Preliminary)
32-kHz CLOCK OUTPUT
R2023K/T, 32.768-kHz clock pulses output from 32KOUT when either CLEN1 Control Register CLEN2 Control Register when CLKC high. condition satisfied, output low.
CLEN1 Address 0(Default) CLEN2 Address 0(Default)
CLKC input
32KOUT (CMOS push-pull output) Clock pulses
32KOUT output synchronized with CLEN1 CLEN2 CLKC settings illustrated timing chart below.
CLKC CLEN1 CLEN2 setting 32KOUT
Max.62.0µs
R2023K/T (Preliminary)
Typical Applications
Typical Power Circuit Configurations
Sample circuit configuration R1163xxx1B series regulator with reverse current protection circuit. should pull-up system power supply voltage, should connect system power supply VSS. Please select VOUT voltage equal power supply voltage that interfaces R2023K/T SRAM.
System Power Supply
VOUT
Install bypass capacitors high-frequency low-frequency applications parallel close vicinity R2023K/T.
R1163xxx1B SRAM etc. Primary Battery
Sample circuit configuration
OSCIN OSCOUT 32768Hz System power supply
Primary Battery
OSCIN OSCOUT 32768Hz
System power supply
Secondary Battery
R2023K/T (Preliminary)
Connection INTRA INTRB
INTRA INTRB follows N-channel open drain output logic contains protective diode power supply side. such, connected pull-up resistor 5.5v regardless supply voltage.
System power supply
INTRA INTRB OSCIN OSCOUT 32768Hz
Backup power supply
Depending whether INTRA INTRB used during battery backup, should connected pull-up resistor following different positions: Position left diagram when used during battery backup. Position left diagram when used during battery backup.
Connection 32KOUT
32KOUT CMOS output, supply voltage R2023K/T devices connected should same. When device powered down, 32KOUT output should disabled. When CLKC connected system power supply through pull-up resistor, pull-up resistor should 10k, 32KOUT should connect host device through resistor (approx. 10k)
CLKC 32KOUT
R3111 XXXXC
Power Supply CLKC 32KOUT
Power Supply
Approx.10K Back-up Power Supply Back-up Power supply
R2023K/T (Preliminary)
Typical Characteristics
Test circuit
<Under Constructing>
OSCIN CGOUT 32768Hz OSCOUT CDOUT 32KOUT Frequency Counter
X'tal 32.768kHz (R1=50k typ) (CL=6pF 9pF) Topt 25°C Output pins Open
Timekeeping Current Supply Voltage (with 32kHz clock output) (Output=Open, Topt=25°C)
Timekeeping Current IDD(uA)
Timekeeping Current Supply Voltage (with 32kHz clock output) (Output=Open, Topt=25°C)
Timekeeping Current IDD(uA)
Supply Vlotage VDD(v)
Supply Voltage VDD(v)
(CGout, CDout)=(5pF, 5pF)
(CGout, CDout)=(5pF, 5pF) (CGout, CDout)=(0pF, 0pF)
(CGout, CDout)=(0pF, 0pF)
Access Current Clock Frequency (CLKC=VSS, Output pins=Open, Topt=25°C, CGout=CDout=0pF)
Access Current IDD(uA)
Timekeeping Current Operating Temperature (VDD=3v, Output pins=Open, CGout=CDout=0pF)
Timekeeping Current IDD(uA)
VDD=5v
VDD=3v
Clock Frequency (kHz)
with 32kHz clock output
with 32kHz clock output
Operating Temperature Topt(Celcius)
R2023K/T (Preliminary)
Oscillation Frequency Deviation External (VDD=3v, Topt=25°C, CGout=CDout=0pF standard)
Oscillation Frequency Deviation (ppm)
Oscillation Frequency Deviation Supply Voltage (Topt=25°C,VDD=3v standard)
Oscillation Frequency Deviation (ppm)
-100
CDout=0pF
CDout=5pF
Supply Voltage
External (pF)
Oscillation Frequency Deviation Operating Temperature (VDD=3V, Topt=25°C standard)
Oscillation Frequency Deviation (ppm)
(SCL pin) (Topt=25°C)
-100 -120 Operating TemperatureTopt(Celsius)
(mA)
VDD=5v VDD=3v VDD=1.5v
INTRA INTRB pin) (Topt=25°C)
IOL(mA)
VDD=5v VDD=3v VDD=1.5v
VOL(v)
R2023K/T (Preliminary)
Typical Software-based Operations
Initialization Power-on
Start Power-on
PON=1?
VDET=0?
Oscillation Adjustment Register Control Register etc.
Warning Back-up Battery Run-down
After power-on from volt, start oscillation process internal initialization require time span 2seconds, that access should done after lapse this time span more. setting Control Register indicates power-on from backup battery from further details, "P.37 PON, VDET". This step required when supply voltage monitoring circuit used. This step involves ordinary initialization including Oscillation Adjustment Register interrupt cycle settings, etc.
Writing Time Calendar Data
When writing clock calendar counters, insert Stop Condition until times from second year have been written prevent error writing time. (Detailed "P.28 Data Transmission under Special Condition". writing second counter will reset divider units lower than second digits. Take care that process from Start Condition Stop Condition will complete within 0.5sec. (Detailed "P.28 Data Transmission under Special Condition". R2023K/T also initialized power-on process writing time calendar data.
Start Condition
Write Time Counter Calendar Counter
Stop Condition
R2023K/T (Preliminary)
Reading Time Calendar Data
Ordinary Process Reading Time Calendar Data
When reading clock calendar counters, insert Stop Condition until times from second year have been written prevent error writing time. (Detailed "P.28 Data Transmission under Special Condition". Take care that process from Start Condition Stop Condition will complete within 0.5sec. (Detailed "P.28 Data Transmission under Special Condition".
Start Condition
Read from Time Counter Calendar Counter
Stop Condition
Basic Process Reading Time Calendar Data with Periodic Interrupt Function
Periodic Interrupt Cycle Selection Bits
Generate Interrupt
CTFG=1?
Read from Time Counter Calendar Counter
Other Interrupt Processes
This step intended select level mode waveform mode periodic interrupt function. This step must completed within second. This step intended CTFG Control Register cancel interrupt CPU.
Control Register (X1X1X011)
R2023K/T (Preliminary)
Applied Process Reading Time Calendar Data with Periodic Interrupt Function
Time data need read from time counters when used such ordinary purposes time count indication. This applied process used read time calendar data with substantial reductions load involved such reading. Time Indication "Day-of-Month, Day-of-week, Hour, Minute, Second" Format:
Control Register (XXXX0100) Control Register (X1X1X011)
Generate interrupt Other interrupts Processes
CTFG=1?
Sec.=00?
This step intended select level mode waveform mode periodic interrupt function. This step must completed within sec. This step intended read time data from time counters only first session reading time data after writing time data. This step intended CTFG Control Register cancel interrupt CPU.
previous Min.,Hr., Day, Day-of-week data
Read Min.,Hr.,Day, Day-of-week
Control Register (X1X1X011)
R2023K/T (Preliminary)
Interrupt Process
Periodic Interrupt
Periodic Interrupt Cycle Selection Bits
Generate Interrupt
This step intended select level mode waveform mode periodic interrupt function. This step intended CTFG Control Register cancel interrupt CPU.
Other Interrupt Processes
CTFG=1?
Conduct Periodic Interrupt
Control Register (X1X1X011)
Alarm Interrupt
WALE DALE0
Alarm Min., Hr., Day-of-week Registers
WALE DALE1
Generate Interrupt
This step intended once disable alarm interrupt circuit setting WALE DALE bits anticipation coincidental occurrence match between current time preset alarm time process setting alarm interrupt function. This step intended enable alarm interrupt function after completion alarm interrupt settings. This step intended once cancel alarm interrupt function writing settings "X,1,X, 1,X,1,0,1" "X,1,X,1,X,1,1,0" Alarm_W Registers Alarm_D Registers, respectively.
WAFG DAFG=1?
Other Interrupt
Processes
Conduct Alarm Interrupt
Control Register (X1X1X101)
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