SDRAM Unbuffered SODIMM 200pin Unbuffered SODIMM based 128Mb E-di
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64MB, 128MB Unbuffered SODIMM
SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based 128Mb E-die (x16) with 64-bit
Revision August. 2003
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Revision History
Revision (December, 2002) First release Revision (Febrary, 2003) 64MB SODIMM M470L0914ET0 Revision (March, 2003) Complete 128Mb current spec. Revision (August, 2003) Corrected typo.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
184Pin Unbuffered DIMM based 128Mb E-die (x16)
Ordering Information
Part Number M470L0914ET0-C(L)B3/A2/B0 M470L1714ET0-C(L)B3/A2/B0 Density 64MB 128MB Organization
Component Composition 8Mx16 (K4H281638E) 8Mx16 (K4H281638E)
Height 1,250mil 1,250mil
Operating Frequencies
B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
Feature
Power supply Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V Double-data-rate architecture; data transfers clock cycle Bidirectional data strobe(DQS) Differential clock inputs(CK aligns transition with transition Programmable Read latency (clock) Programmable Burst length Programmable Burst type (sequential interleave) Edge aligned data output, center aligned data input Auto Self refresh, 7.8us refresh interval(8K/64ms refresh) Serial presence detect with EEPROM Height 1,250 (mil), single (64MB), double (128MB) sided
SAMSUNG ELECTRONICS CO., Ltd. reserves right change products specifications without notice.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Configurations (Front side/back side)
Front VREF DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18 DQ19 DQ24 DQ25 DQS3 Front DQ27 DQS8 /CK2 CKE1 *A12 A10/AP /CS0 *DU(A13) DQ32 DQ33 Front DQ34 DQ35 DQ40 DQ41 DQS5 DQ42 DQ43 DQ48 DQ49 DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VDDSPD Back VREF DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22 DQ23 DQ28 DQ29 Back
Back DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 /CK1 DQ52 DQ53 DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
DQ31 *DU/(RESET) CKE0 DU(BA2) /RAS /CAS /CS1 *122 DQ36 DQ37
Note These pins used this module. Pins reserved module, used module. 95,122 8Mx16 based module used 16Mx8 based module. Pins reserved modules.
Description
Name DQ63 DQS0 DQS7 CK0,CK0 CK2, CKE0 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input address strobe Column address strobe Write enable Name VDDQ VREF VDDSPD Function Data mask Power supply (2.5V) Power Supply DQS(2.5V) Ground Power supply reference Serial EEPROM Power Serial data Serial clock Address EEPROM connection
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
6MB, Module (M470L0914ET0) (Populated bank SDRAM Module) Functional Block Diagram
DQS0 LDQS DQS4 LDQS
DQS1
UDQS
DQS5
UDQS
DQS2
LDQS
DQS6
LDQS
DQS3
UDQS
DQS7
UDQS
CKE0 VDDSPD VDD/VDDQ
BA0-BA1: SDRAMs A0-A11: SDRAMs RAS: SDRAMs CAS: SDRAMs CKE: SDRAMs SDRAMs Clock Input CK0/CK0 CK1/CK1 CK2/CK2 Clock Wiring SDRAMs SDRAMs SDRAMs CK0/1/2 CK0./1/2 Card Edge D1/D3/Cap Cap/Cap/Cap Serial R=120 *Clock Wiring D0/D1/Cap Cap/Cap/Cap
VREF VDDID
Strap: Note
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/CS relationships must maintained shown. DQS, DM/DQS resistors: Ohms.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
128MB, Module (M470L1714ET0) (Populated bank SDRAM Module) Functional Block Diagram
DQS0 DQS1 DQS2 DQS3
CKE0 CKE1 VDDSPD VDD/VDDQ
LDQS UDQS LDQS UDQS
BA0-BA1: SDRAMs A0-A11: SDRAMs RAS: SDRAMs CAS: SDRAMs CKE: SDRAMs CKE: SDRAMs SDRAMs
LDQS UDQS LDQS UDQS
DQS4 DQS5 DQS6 DQS7
LDQS UDQS LDQS UDQS
R=120 CK0/1/2 CK0/1/2 Card Edge *Clock Wiring
LDQS UDQS LDQS UDQS
D0/D2/Cap
Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2 SDRAMs SDRAMs SDRAMs
D1/D3/Cap D4/D6/Cap D5/D7/Cap
Serial
VREF
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/CS relationships must maintained shown. DQS, DM/DQS resistors: Ohms.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Absolute Maximum Ratings
Parameter Voltage relative Voltage VDDQ supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG Value -0.5 -1.0 +150 component
Unit
Note Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted recommend operation condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
Operating Conditions
Parameter
Recommended operating conditions(Voltage referenced VSS=0V, TA=0 70°C)
Symbol
VDDQ VREF VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio)
0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -16.8 16.8
0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6
Unit
Note
Supply voltage(for device with nominal 2.5V) Supply voltage Reference voltage Termination voltage(system) Input logic high voltage Input logic voltage Input Voltage Level, inputs Input Differential Voltage, inputs Matching: Pullup Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT 0.84V Output High Current(Normal strengh driver) ;VOUT 0.84V Output High Current(Half strengh driver) ;VOUT 0.45V Output High Current(Half strengh driver) ;VOUT 0.45V
Note 1.VREF expected equal 0.5*VDDQ transmitting device, track variations level same. Peak-to peak noise VREF exceed +/-2% value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF magnitude difference between input level input level ratio pullup current pulldown current specified same temperature voltage, over entire temperature voltage range, device drain source voltages from 0.25V 1.0V. given output, represents maximum difference between pullup pulldown drivers process variation. full variation ratio maximum minimum pullup pulldown current will exceed device drain source voltages from 1.0.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
SDRAM spec table
M470L0914ET0 64MB Module
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal power IDD7A B3(DDR333@CL=2.5) 1020 1000 1580 A2(DDR266@CL=2) 1460 B0(DDR266@CL=2.5) 1460
(VDD=2.7V, 10°C) Unit Optional Notes
Module calculated basis component differently measured according loading cap.
M470L1714ET0 128MB Module
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal power IDD7A B3(DDR333@CL=2.5) 1100 1220 1500 1480 1320 2060 A2(DDR266@CL=2) 1080 1340 1280 1200 1880 B0(DDR266@CL=2.5) 1080 1340 1280 1200 1880
(VDD=2.7V, 10°C) Unit Optional Notes
Module calculated basis component differently measured according loading cap.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Operating Conditions
Parameter/Condition Input High (Logic Voltage, signals Input (Logic Voltage, signals. Input Differential Voltage, inputs Input Crossing Point Voltage, inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.5*VDDQ-0.2 VREF 0.31 VREF 0.31 VDDQ+0.6
Unit
Note
0.5*VDDQ+0.2
Note magnitude difference between input level input value expected equal 0.5*VDDQ transmitting device must track variations level same. These parameters should tested actual components checked either simulation. input specificatims refation Vref envelope that been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter Input capacitance(A0 A11, BA1,RAS,CAS,WE Input capacitance(CKE0, CKE1) Input capacitance(CS0, CS1) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7) Data input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2
(VDD=2.5V, VDDQ=2.5V, 25°C, f=1MHz) M470L0914ET0 M470L1714EMin Unit
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Timming Parameters Specifications
Parameter
cycle time Refresh cycle time active time delay precharge time active active delay Write recovery time Last data Read command Col. address Col. address delay Clock cycle time Clock high level width Clock level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge ouput data edge Read Preamble Read Postamble valid DQS-in DQS-in setup time DQS-in hold time falling edge rising-setup time falling edge from rising-hold time DQS-in high level width DQS-in level width DQS-in cycle time Address Control Input setup time(fast) Address Control Input hold time(fast) Address Control Input setup time(slow) Address Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise fall) CL=2.0 CL=2.5
Symbol
tRFC tRAS tRCD tRRD tWTR tCCD tDQSCK tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tSL(I) tSL(IO) tSL(O) tSLMR
(DDR333@CL=2.5))
0.45 0.45 -0.6 -0.7 0.75 0.25 0.35 0.35 0.75 0.75 -0.7 -0.7 0.67 +0.7 +0.7 0.55 0.55 +0.6 +0.7 0.45 1.25
(DDR266@CL=2.0)
0.45 0.45 -0.75 -0.75 0.75 0.25 0.35 0.35 -0.75 -0.75 0.67 +0.75 +0.75 0.55 0.55 +0.75 +0.75 1.25 120K
(DDR266@CL=2.5))
0.45 0.45 -0.75 -0.75 0.75 0.25 0.35 0.35 -0.75 -0.75 0.67 +0.75 +0.75 0.55 0.55 +0.75 +0.75 1.25 120K
Unit
V/ns V/ns V/ns
Note
i,5.7~9 i,5.7~9
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
(DDR333@CL=2.5)) (DDR266@CL=2.0)
Mode register cycle time setup time hold time Control Address input pulse width input pulse width Power down exit time Exit self refresh non-Read command Exit self refresh read command Refresh interval time Output valid window Clock half period Data hold skew factor write postamble time Active Read with Auto precharge command Autoprecharge write recovery Precharge time tMRD tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQHS tWPST tRAP tDAL (tWR/tCK) (tRP/tCK) 0.45 0.45 1.75 -tQHS tCLmin tCHmin 0.55 (tWR/tCK) (tRP/tCK)
(DDR266@CL=2.0) (DDR266@CL=2.5))
1.75 -tQHS 0.75 (tWR/tCK) (tRP/tCK) 1.75 -tQHS tCLmin tCHmin 0.75 (tWR/tCK) (tRP/tCK)
Parameter
Symbol
Unit
Note
1.75 -tQHS tCLmin tCHmin
0.75
tCLmin tCHmin
System Characteristics following specification parameters required systems using DDR333& DDR266 devices ensure proper system performance. these characteristics system simulation purposes guaranteed design.
Table Input Slew Rate DQS,
CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 DDR266 Units V/ns Notes
Table Input Setup Hold Time Derating Slew Rate
Input Slew Rate V/ns V/ns V/ns +100 Units Notes
Table Input/Output Setup Hold Time Derating Slew Rate
Input Slew Rate V/ns V/ns V/ns +150 +150 Units Notes
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Table Input/Output Setup Hold Derating Rise/Fall Delta Slew Rate
Delta Slew Rate V/ns 0.25 V/ns V/ns +100 +100 Units Notes
Table Output Slew Rate Characteristice (X4, Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes a,c,d,f,g,h b,c,d,f,g,h
Table Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes a,c,d,f,g,h b,c,d,f,g,h
Table Output Slew Rate Matching Ratio Characteristics
CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup Pulldown) DDR333 DDR266 Notes
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Component Notes
transitions occur same access time windows valid data transitions. these parameters referenced specific voltage level specify when device output longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, performance (bus turnaround) will degrade accordingly. specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. when writes were previ ously progress bus, will tran sitioning from High- logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum eight AUTO REFRESH commands posted given SDRAM device. command/address input slew rate V/ns command/address input slew rate V/ns V/ns slew rate V/ns These parameters guarantee device timing, they necessarily tested each device. They guaranteed device design tester correlation. Slew Rate measured between VOH(ac) VOL(ac). (tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH).For example, period, less half period jitter (tJIT(HP)) clock source, less half period jitter crosstalk (tJIT(crosstalk)) into clock traces. tQHS, where: minimum half clock period given cycle defined clock high clock (tCH, tCL). tQHS accounts pulse duration distortion on-chip clock circuits; worst case push-out tansition followed worst case pull-in next transition, both which are, separately, data skew output pattern effects, pchannel n-channel variation output drivers. tDQSQ Consists data skew output pattern effects, p-channel n-channel variation output drivers given cycle. tDAL (tWR/tCK) (tRP/tCK) each terms above, already integer, round next highest integer. Example: DDR266B CL=2.5 tCK=7.5ns tDAL 7.5ns) tDAL clocks
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
System Notes Pullup slew rate characteristized under test conditions shown Figure
Test point Output VSSQ Figure Pullup slew rate test load
Pulldown slew rate measured under test conditions shown Figure
VDDQ Output Test point Figure Pulldown slew rate test load
Pullup slew rate measured between (VDDQ/2 Pulldown slew rate measured between (VDDQ/2 Pullup Pulldown slew rate conditions pattern data, including outputs switching only output switching. Example typical slew rate, switching minmum slew rate, bits switching from either high low, high. remaining bits remain same previous state. Evaluation conditions Typical Ambient), VDDQ 2.5V, typical process Minimum Ambient), VDDQ 2.3V, slow slow process Maximum Ambient), VDDQ 2.7V, fast fast process ratio pullup slew rate pulldown slew rate specified same temperature voltage, over entire temperature voltage range. given output, represents maximum difference between pullup pulldown drivers process variation. Verified under typical conditions qualification purposes. TSOPII package divices only. Only intended operation Mbps pin. derating factor will used increase case where input slew rate below 0.5V/ns shown Table Input slew rate based lesser slew rates detemined either VIH(AC) VIL(AC) VIH(DC) VIL(DC), similarly rising transitions. derating factor will used increase case where slew rates differ, shown Tables Input slew rate based larger AC-AC delta rise, fall rate DC-DC delta rise, Input slew rate based lesser slew rates determined either VIH(AC) VIL(AC) VIH(DC) VIL(DC), similarly rising transitions. delta rise/fall rate calculated {1/(Slew Rate1)} {1/(Slew Rate2)} example Slew Rate V/ns slew Rate V/ns, then delta rise, fall rate 0.5ns/V Using table given, this would result need increase Table used increase case where slew rate below V/ns. slew rate based lesser lesser slew rate slew rate. inut slew rate based lesser slew rates deter mined either VIH(ac) VIL(ac) VIH(DC) VIL(DC), similarly rising transitions. DQS, input slew rate specified prevent double clocking data preserve setup hold times. Signal transi tions through region must monotony.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Command Truth Table
COMMAND Register Register Extended Mode Register Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn BA0,1 A10/AP Note
CODE CODE
Address
Column Address Column Address
Bank Active Addr. Read Column Address Write Column Address Burst Stop Precharge Bank Selection Banks Entry Exit Entry Precharge Power Down Mode Exit operation (NOP) defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
Active Power Down
Note Code Operand Code. Program keys. (@EMRS/MRS) EMRS/ issued only banks precharge state. command issued clock cycles after EMRS MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. "High" "Low" read, write, active precharge, bank selected. "Low" "High" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled rising falling edges Data-in masked both edges (Write latency This combination defined function, which means Operation(NOP)" SDRAM.
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Physical Dimensions (M470L0914ET0)
Units Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
0.17 (4.20) 0.096 (2.40)
1.896 (47.40)
0.07 (1.80)
0.150 (3.80 Max) (4.00 Min) (4.00 Min) 0.157 0.157 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail
Detail
Tolerances ±.006(.15) unless otherwise specified used device 8Mx16 SDRAM, TSOPII SDRAM Part K4H281638E-T***
Rev. August. 2003
64MB, 128MB Unbuffered SODIMM
Physical Dimensions (M470L1714ET0)
Units Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
0.17 (4.20) 0.096 (2.40)
1.896 (47.40)
0.07 (1.80)
0.150 (3.80 Max) (4.00 Min) (4.00 Min) 0.157 0.157 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.01 (0.25) 0.024 (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail
Detail
Tolerances ±.006(.15) unless otherwise specified used devices 8Mx16 SDRAM, TSOPII. SDRAM Part K4H281638E-T***
Rev. August. 2003
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