SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

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ICS87972I
SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fully integrated LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync Selectable crystal oscillator interface LVCMOS/LVTTL reference clock inputs CLK0, CLK1 accept following input levels: LVCMOS LVTTL Output frequency range: 8.33MHz 125MHz range: 200MHz 480MHz Output skew: 550ps (maximum) Cycle-to-cycle jitter: ±100ps (typical) Full 3.3V supply voltage -40°C 85°C ambient operating temperature compatible with MPC972 Compatible with PowerPCand PentiumMicroprocessors
GENERAL DESCRIPTION
HiPerClockS
ICS87972I skew, LVCMOS/LVTTL Clock Generator member HiPerClockSfamily High Performance Clock Solutions from ICS. ICS87972I three selectable inputs provides LVCMOS/LVTTL outputs.
ICS87972I highly flexible device. Using crystal oscillator input, used generate clocks system. these clocks same frequency device configured generate three different frequencies among three output banks. Using single ended inputs, ICS87972I used zero delay buffer/multiplier/divider clock distribution applications. three output banks feedback output each have their output dividers which allows device generate multitude different bank frequency ratios output-to-input frequency ratios. addition, outputs Bank (QC2, QC3) selected inverting non-inverting. output frequency range 8.33MHz to125MHz. Input frequency range 5MHz 120MHz. ICS87972I also QSYNC output which used system synchronization purposes. monitors Bank Bank outputs goes period faster clock prior coincident rising edges Bank Bank clocks. QSYNC then goes high again when coincident rising edges Bank Bank occur. This feature used primarily applications where Bank Bank running different frequencies, particularly useful when they running non-integer multiples another. Example Applications: System Clock generator: 16.66 Crystal generate eight 33.33MHz copies four 100MHz copies PCI-X. Line Card Multiplier: Multiply 19.44MHz from back plane 77.76MHz line Card ASICs Serdes. Zero Delay buffer Synchronous memory: twelve 100MHz copies from memory controller reference clock memory chips memory module with zero delay.
ASSIGNMENT
FSEL_FB0 EXT_FB GNDO GNDO GNDO VDDO VDDO
FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 VDDO GNDO VDDO GNDO VCO_SEL
GNDI
FSEL_FB1 QSYNC GNDO VDDO FSEL_C0 FSEL_C1 VDDO GNDO INV_CLK
ICS87972I
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2 PLL_SEL
REF_SEL CLK_SEL
CLK0 CLK1 XTAL1 XTAL2 VDDA
52-Lead LQFP 10mm 10mm 1.4mm package body package View
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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
XTAL1 XTAL2
VCO_SEL PLL_SEL REF_SEL CLK0 CLK1 CLK_SEL EXT_FB PHASE DETECTOR
SYNC SYNC SYNC SYNC
SYNC SYNC SYNC SYNC
FSEL_FB2
nMR/OE POWER-ON RESET SYNC PULSE
SYNC
SYNC SYNC
FSEL_A0:1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2
SYNC
QSYNC
DATA GENERATOR
FRZ_CLK OUTPUT DISABLE CIRCUITRY
FRZ_DATA
INV_CLK
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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
XTAL1 XTAL2 CLK0 CLK1 CLK_SEL REF_SEL
RANGE 200MHz 480MHz
FSEL_A[0:1]
FSEL_
SYNC SYNC SYNC SYNC
EXT_FB
FSEL_B[0:1]
VCO_SEL
PLL_SEL
FSEL_
SYNC SYNC SYNC SYNC
FSEL_C[0:1]
FSEL_
SYNC
SYNC SYNC
INV_CLK FSEL_FB[0:2]
FRZ_CLK FRZ_DATA
FSEL_
OUTPUT DISABLE CIRCUITRY SYNC
QSYNC
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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Power Input Input Input Input Description
TABLE DESCRIPTIONS
Number Name GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2, FSEL_FB1, FSEL_FB0 PLL_SEL Power supply ground. Master reset output enable. When HIGH, enables outputs. When Pullup LOW, resets outputs tristate resets output divide circuitr Enables disables outputs. LVCMOS LVTTL interface levels. Pullup Clock input freeze circuitr LVCMOS LVTTL interface levels. Configuration data input freeze circuitr Pullup LVCMOS LVTTL interface levels. Pullup Select pins control Feedback Divide value. LVCMOS LVTTL interface levels.
Input
REF_SEL CLK_SEL CLK0, CLK1 XTAL1, XTAL2 VDDA INV_CLK GNDO QC3, QC2, QC1, VDDO FSEL_C1, FSEL_C0 QSYNC EXT_FB QB3, QB2, QB1, FSEL_B1, FSEL_B0 FSEL_A1, FSEL_A0 QA3, QA2, QA1, VCO_SEL
Input Input Input Input Power Input Power Output Power Input Output Power Output Input Output Input Input Output Input
Selects between reference clocks input output Pullup dividers. When HIGH, selects PLL. When LOW, bypasses reference clocks. LVCMOS LVTTL interface levels. Selects between ystal reference clock. Pullup When LOW, selects CLK0 CLK1. When HIGH, selects ystal inputs. LVCMOS LVTTL interface levels. Clock select input. When LOW, selects CLK0. Pullup When HIGH, selects CLK1. LVCMOS LVTTL interface levels. Pullup Reference clock inputs. LVCMOS LVTTL interface levels. ystal oscillator interface. XTAL1 input. XTAL2 output. Analog supply pin. Inver clock select outputs. Pullup LVCMOS LVTTL interface levels. Power supply ground. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins. Pullup Select pins Bank outputs. LVCMOS LVTTL interface levels. Synchronization output Bank Bank Refer Figure Timing Diagrams. LVCMOS LVTTL interface levels. Core supply pins. Feedback clock output. LVCMOS LVTTL interface levels. Pullup External feedback. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Pullup Select pins Bank outputs. LVCMOS LVTTL interface levels. Pullup Select pins Bank outputs. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Selects VCO. When HIGH, selects Pullup When LOW, selects LVCMOS LVTTL interface levels.
NOTE: Pullup refers internal input resistors. table Characteristics, typical values.
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Test Conditions Minimum Typical VDDA, VDD, VDDO 3.465V Maximum Units
TABLE CHARACTERISTICS
Symbol RPULLUP ROUT Parameter Input Capacitance Input Pullup Resistor Power Dissipation Capacitance (per output) Output Impedance
TABLE OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_A1 FSEL_A0 Outputs Inputs FSEL_B1 FSEL_B0 Outputs Inputs FSEL_C1 FSEL_C0 Outputs
TABLE FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs FSEL_FB2 FSEL_FB1 FSEL_FB0 Outputs
TABLE CONTROL INPUT SELECT FUNCTION TABLE
Control VCO_SEL REF_SEL CLK_SEL PLL_SEL nMR/OE INV_CLK Logic VCO/2 CLK0 CLK1 CLK0 BYPASS Master Reset/Output Non-Inver QC2, Logic XTAL CLK1 Enable Enable Outputs Inver QC2,
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MODE
fVCO
QSYNC
MODE
QSYNC
MODE
QC(÷2) QA(÷4) QSYNC
MODE
QC(÷2) QA(÷8) QSYNC
MODE
QC(÷2) QA(÷8) QSYNC
MODE
QA(÷6) QC(÷8) QSYNC
MODE
QA(÷12) QC(÷2) QSYNC
FIGURE TIMING DIAGRAMS
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4.6V -0.5V -0.5V VDDO 0.5V 42.3°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current power pins Test Conditions Minimum 3.135 2.935 3.135 Typical Maximum 3.465 3.465 3.465 Units
NOTE: Special thermal handling required some configurations.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage Input Current Output High Voltage Output Voltage -20mA 20mA Test Conditions Minimum Typical Maximum ±120 Units
TABLE INPUT FREQUENCY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter CLK0, CLK1; NOTE Input Frequency XTAL1, XTAL2 Test Conditions Minimum Typical Maximum Units
FRZ_CLK NOTE Input frequency depends feedback divide ratio ensure "clock feedback divide" range 200MHz 480MHz.
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Test Conditions Minimum Typical Maximum Units
TABLE CRYSTAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Test Conditions fMAX Output Frequency Static Phase Offset; NOTE CLK0 CLK1 Frequency 50MHz -270 -330 Minimum Typical Maximum ±100 0.8V 0.15 tPERIOD/2 tPERIOD/2 tPERIOD/2 Units
tsk(o) tjit(cc)
fVCO tLOCK tPZL, tPZH tPLZ, tPHZ
Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Range Lock Time; NOTE Output Rise/Fall Time; NOTE Output Pulse Width Output Enable Time; NOTE Output Disable TIme; NOTE
NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE These parameters guaranteed characterization. tested production. NOTE This parameter defined accordance with JEDEC Standard
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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO 1.65V±5%
SCOPE LVCMOS
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC,
jit(cc) tcycle -tcycle
1000 Cycles
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
CLK0, CLK1
(where random sample, mean average sampled cycles measured controlled edges)
OUTPUT SKEW
STATIC PHASE OFFSET
2.4V 0.5V
2.4V 0.5V
QA0:QA3, QB0:QB3, QC0:QC3, QSYNC,
Clock Outputs
OUTPUT RISE/FALL TIME
87972DYI
tPeriod
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tsk(o)
EXT_FB
mean Static Phase Offset
VDDO
PERIOD
PERIOD
VDDO
tcycle
tcycle
VDDO
ICS87972I
SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
USING OUTPUT FREEZE CIRCUITRY
OVERVIEW
enable power states within system, each output ICS87972I (Except QFB) individually frozen (stopped logic state) using simple serial interface shift register. serial interface chosen eliminate need each output have Output Enable pin, which would dramatically increase count package cost. Common sources system that used drive ICS87972I serial interface FPGA's ASICs. FRZ_CLK signal. place output freeze state, logic must written respective freeze enable shift register. unfreeze output, logic must written respective freeze enable bit. Outputs will become enabled/ disabled until data bits shifted into shift register. When data bits shifted register, next rising edge FRZ_CLK will enable disable outputs. that following 12th register logic "0", used start next cycle; otherwise, device will wait won't start next cycle until sees logic bit. Freezing unfreezing output clock synchronous (see timing diagram below). When going into frozen state, output clock will time would normally LOW, freeze logic will keep output until unfrozen. Likewise, when coming frozen state, output will HIGH only when would normally HIGH. This logic, therefore, prevents runt pulses when going into frozen state.
PROTOCOL
Serial interface consists pins, FRZ_Data (Freeze Data) FRZ_CLK (Freeze Clock). Each outputs which frozen freeze enable shift register. sequence started supplying logic start followed 12NRZ freeze enable bits. period each FRZ_DATA equals period FRZ_CLK signal. FRZ_DATA serial transmission should timed ICS87972I sample each FRZ_DATA with rising edge
FRZ_DATA
QSYNC
FRZ_CLK
FIGURE
FREEZE DATA INPUT PROTOCOL
FREEZE Internal
Internal
FIGURE OUTPUT DISABLE TIMING
87972DYI
Latched
Clocked
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POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87972I provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W
47.1°C/W 36.4°C/W
42.0°C/W 34.0°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87972I 8364
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PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.22 0.22 MINIMUM NOMINAL -1.40 0.32 0.30 12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC -0.10 0.13 1.60 0.15 1.45 0.38 0.33 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Marking ICS87972DYI ICS87972DYI Package Lead LQFP Lead LQFP Tape Reel Count tray Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87972DYI ICS87972DYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87972DYI
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ICS87972I
SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET Description Change Description Table added pins Block Diagram added missing dividers Data Generator. Revised Package Outline diagram. Characteristics changed limit from 25pF typical 18pf max. Power Supply Table changed limit from 215mA max. 250mA max. Application Information: Added section, "Power Supply Filtering Techniques". Characteristics changed from max. typical. Corrected Freeze Data labeling Figure Power Supply Table changed minimum VDDA from 3.135V 2.935V. Crystal Table changed from Date 9/9/02 10/18/02 12/5/02
Table
Page
3/24/03
5/8/03 6/27/03
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SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ful

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