Analog Multichannel, 12-bit, MSPS channels1 Fully differential single-
|
|
|
Top Searches for this datasheet
Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI® ADuC7019/20/21/22/24/25/26/27
Analog Multichannel, 12-bit, MSPS channels1 Fully differential single-ended modes VREF analog input range 12-bit voltage output DACs outputs available1 On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source 41.78 with programmable divider Memory flash/EE memory, SRAM In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals UART, I2C® SPI® serial 40-pin GPIO port1 general-purpose timers Wake-up watchdog timers Power supply monitor Three-phase, 16-bit generator1 Programmable logic array (PLA) External memory interface, Power Specified operation Active mode: MHz; 41.78 Packages temperature range From 40-lead LFCSP 80-pin LQFP1 Fully specified -40°C +125°C operation Tools Low-cost QuickStartdevelopment system Full third-party support
Industrial control automation systems Smart sensors, precision instrumentation Base station systems, optical networking
FUNCTIONAL BLOCK DIAGRAM
ADC0 ADC11 TEMP SENSOR CMP0 CMP1 CMPOUT VREF THREEPHASE GPIO BANDGAP 1MSPS 12-BIT 12-BIT 12-BIT DAC0
DAC1
ADuC7026
12-BIT 12-BIT
DAC2
DAC3
XCLKI XCLKO
ARM7TDMI-BASED WITH ADDITIONAL PERIPHERALS SRAM FLASH/EEPROM SERIAL UART, SPI,
PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L
Figure
Depending part model. Ordering Guide more information.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices.Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. rights reserved.
04955-001
GENERAL PURPOSE TIMERS
JTAG
EXT. MEMORY INTERFACE
ADuC7019/20/21/22/24/25/26/27 TABLE CONTENTS
Features Applications. Functional Block Diagram General Description Detailed Block Diagram Specifications. Timing Specifications Absolute Maximum Ratings. Caution. Configurations Function Descriptions ADuC7024/ADuC7025 ADuC7026/ADuC7027 Typical Performance Characteristics Terminology Specifications Specifications. Overview ARM7TDMI Core. Thumb Mode (T). Long Multiply (M). EmbeddedICE Exceptions Registers Interrupt Latency. Memory Organization Memory Access. Flash/EE Memory. SRAM Memory Mapped Registers Circuit Overview. Transfer Function. Typical Operation. MMRs Interface. Converter Operation. Driving Analog Inputs Calibration. Temperature Sensor Bandgap Reference. Nonvolatile Flash/EE Memory Programming. Security Flash/EE Control Interface Execution Time from SRAM Flash/EE. Reset Remap Other Analog Peripherals. DAC. Power Supply Monitor Comparator Oscillator PLL-Power Control. Digital Peripherals. Three-Phase PWM. General-Purpose Serial Port Mux. UART Serial Interface. Serial Peripheral Interface. Compatible Interfaces Programmable Logic Array (PLA).
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Processor Reference Peripherals Interrupt System.73 Timers.74 External Memory Interfacing Hardware Design Considerations Power Supplies.82 Grounding Board Layout Recommendations Clock Oscillator.83 Power-on Reset Operation.84 Typical System Configuration Development Tools PC-Based Tools In-Circuit Serial Downloader Outline Dimensions.86 Ordering Guide
REVISION HISTORY
10/05-Revision Initial Version
Rev. Page
ADuC7019/20/21/22/24/25/26/27 GENERAL DESCRIPTION
ADuC7019/20/21/22/24/25/26/27 fully integrated, MSPS, 12-bit data acquisition systems incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs Flash/EE memory single chip. consists single-ended inputs. additional four inputs available multiplexed with four output pins. four outputs only available certain models (ADuC7019, ADuC7020, ADuC7021, ADuC7024, ADuC7026). However, many cases where present, this still used additional input, giving maximum input channels. operate single-ended differential input modes. input voltage VREF. Low-drift bandgap reference, temperature sensor, voltage comparator complete peripheral set. ADuC7019/20/21/22/24/25/26/27 also integrate four buffered voltage output DACs on-chip. output range programmable three voltage ranges. devices operate from on-chip oscillator generating internal high frequency clock 41.78 MHz. This clock routed through programmable clock divider from which core clock operating frequency generated. microcontroller core ARM7TDMI, 16-bit/32-bit RISC machine, which offers MIPS peak performance. Eight kilobytes SRAM kilobytes nonvolatile Flash/EE memory provided on-chip. ARM7TDMI core views memory registers single linear array. On-chip factory firmware supports in-circuit serial download UART serial interface ports, while nonintrusive emulation also supported JTAG interface. These features incorporated into low-cost QuickStartDevelopment System supporting this MicroConverter® family. parts operate from specified over industrial temperature range -40°C +125°C. When operating 41.78 MHz, power dissipation typically ADuC7019/20/21/22/24/25/26/27 available variety memory models packages.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
DETAILED BLOCK DIAGRAM
DACGND
REFGND
DACV
GNDREF
ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADCNEG TEMP SENSOR 12-BIT 1MSPS
ADuC7026*
CONTROL CONTROL
12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC
DACREF
IOGND
IOGND
AGND
AGND
DGND
IOVDD
IOVDD
AVDD
AVDD
LVDD
DAC0*/ADC12
DAC1*/ADC13
DAC2*/ADC14
DAC3*/ADC15
P3.0/AD0/PWM0H/PLAI[8]
62KBYTES FLASH/EE (31k BITS) ARM7TDMI THREEPHASE
P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] P3.6/AD6/PWMTRIP/PLAI[14]
BM/P0.0/CMPOUT/PLAI[7]/MS2
8192 BYTES USER CMPOUT/IRQ BITS)
CORE
WAKEUP/ TIMER POWER SUPPLY MONITOR
DOWNLOADER VREF VREF
P3.7/AD7/PWMSYNC /PLAI[15]
BAND REFERENCE PROG. CLOCK DIVIDER
XCLKO
JTAG EMULATOR
XCLKI
P0.7/ECLK/XCLK/SPM8/PLAO[4]
P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] PROG. LOGIC ARRAY
SPI/I2C SERIAL INTERFACE
UART SERIAL PORT
SERIAL PORT MULTIPLEXER
INTERRUPT CONTROLLER
IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 IRQ1/P0.5/ADCBUSY /PLAO[2]/MS0
P1.4/SPM4/PLAI[4]/IRQ2
P1.5/SPM5/PLAI[5]/IRQ3
P0.6/T1/MRST/PLAO[3]/AE
P2.1/WS/PWM0H/PLAO[6]
P2.2/RS/PWM0L/PLAO[7]
P1.0/T1/SPM0/PLAI[0]
P2.4/PWM0H/MS0
P2.6/PWM1H/MS2
P1.1/SPM1/PLAI[1]
P1.2/SPM2/PLAI[2]
P1.3/SPM3/PLAI[3]
P1.6/SPM6/PLAI[6]
P1.7/SPM7/PLAO[0]
P4.0/AD8/PLAO[8]
P4.1/AD9/PLAO[9]
P2.0/SPM9/PLAO[5]/CONVSTART
P0.3/TRST/A16/ADC BUSY
P4.2/AD10/PLAO[10]
P4.3/AD11/PLAO[11]
P4.4/AD12/PLAO[12]
P4.5/AD13/PLAO[13]
Figure
Rev. Page
04955-002
*SEE SELECTION TABLE FEATURE AVAILABILITY DIFFERENT MODELS.
P0.2/PWM2L/BHE
P0.1/PWM2H/BLE
P2.5/PWM0L/MS1
P2.7/PWM1L/MS3
P2.3/AE
ADuC7019/20/21/22/24/25/26/27 SPECIFICATIONS
AVDD IOVDD VREF internal reference, fCORE 41.78 MHz, 40°C 125°C, unless otherwise noted. Table
Parameter CHANNEL SPECIFICATIONS Power-Up Time Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Code Distribution ENDPOINT ERRORS Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range Input Impedance CHANNEL SPECIFICATIONS ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Gain Error Mismatch ±0.6 ±1.0 ±0.5 +0.7/-0.6 ±1.5 +1/-0.9 Unit Bits sine wave, fSAMPLE MSPS Includes distortion noise components Test Conditions/Comments acquisition clocks fADC/2
internal reference external reference internal reference external reference input voltage
Measured adjacent channels
±VREF/2 VREF
ppm/°C
During acquisition 0.47 from VREF AGND 25°C
0.625 AVDD
25°C
Bits
Guaranteed monotonic internal reference full scale DAC0
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Parameter ANALOG OUTPUTS Output Voltage Range_0 Output Voltage Range_1 Output Voltage Range_2 Output Impedance CHARACTERISTICS Voltage Output Settling Time Digital Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis4, Response Time TEMPERATURE SENSOR Voltage Output 25°C Voltage Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET GLITCH IMMUNITY RESET PIN3 WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance Data Retention DIGITAL INPUTS Logic Input Current (Leakage Current) Logic Input Current Input Capacitance LOGIC INPUTS3 VINL, Input Voltage VINH, Input High Voltage LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Voltage CRYSTAL INPUTS XCLKI XCLKO Logic Inputs, XCLKI Only VINL, Input Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance DACREF DACVDD AGND AVDD Unit nV-sec Test Conditions/Comments DACREF range: DACGND DACVDD
change major carry
Hysteresis turned CMPHYST CMPCON register overdrive configured response time (CMPRES
-1.3 2.79 3.07 ±3.5 2.36 10,000 ±0.2
mV/°C cycles years digital outputs excluding XCLKI XCLKO ISOURCE ISINK selectable trip points selected nominal trip point voltage
55°C digital inputs excluding XCLKI XCLKO logic inputs excluding XCLKI XCLKO
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Parameter INTERNAL OSCILLATOR CLOCK RATE From Internal Oscillator From External Crystal Using External Clock START-UP TIME Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Propagation Delay Element Propagation Delay POWER REQUIREMENTS Power Supply Voltage Range AVDD AGND IOVDD IOGND Analog Power Supply Currents AVDD Current DACVDD Current Digital Power Supply Current IOVDD Current Normal Mode 32.768 41.78 0.05 0.05 3.06 1.58 41.78 Unit Test Conditions/Comments
85°C 125°C Core clock 41.78
From input output
idle mode
IOVDD Current Pause Mode IOVDD Current Sleep Mode Additional Power Supply Currents
1000
Code executing from Flash/EE (41.78 clock) (41.78 clock) 85°C 125°C MSPS 62.5 kSPS
channel specifications guaranteed during normal MicroConverter core operation. Apply input channels. Measured using factory default values ADCOF ADCGN. production tested supported design and/or characterization data production release. Measured using factory default values ADCOF ADCGN using external AD845 input buffer stage shown Figure Based external system components, user need execute system calibration remove external endpoint errors achieve these specifications (see Calibration section). input signal centered common-mode voltage (VCM) long this value within voltage input range specified. When using external reference input pin, internal reference must disabled setting REFCON memory mapped register linearity calculated using reduced code range 3995. gain error calculated using reduced code range internal VREF. Endurance qualified JEDEC Standard method A117 measured -40°C, +25°C, +85°C, +125°C. Retention lifetime equivalent junction temperature (TJ) 55°C JEDEC Standard method A117. Retention lifetime derates with junction temperature. Test carried with maximum eight output level. Power supply current consumption measured normal, pause, sleep modes under following conditions: Normal Mode: supply, Pause Mode: supply, Sleep Mode: supply. IOVDD power supply current decreases typically during flash/EE erase cycle. ADuC7020/21/22, this current must added AVDD current.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
TIMING SPECIFICATIONS
Table External Memory Write Cycle
Parameter TMS_AFTER_CLKH TADDR_AFTER_CLKH TAE_H_AFTER_MS THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TWR_L_AFTER_AE_L TDATA_AFTER_WR_L TWR_H_AFTER_CLKH THOLD_DATA_AFTER_WR_H TBEN_AFTER_AE_L TRELEASE_MS_AFTER_WR_H (XMxPAR[14:12] (!XMxPAR[10]) (!XMxPAR[8]) (!XMxPAR[10] !XMxPAR[8]) (XMxPAR[7:4] (!XMxPAR[8]) (!XMxPAR[8] UCLK Unit
TMS_AFTER_CLKH TAE_H_AFTER_MS THOLD_DATA_AFTER_WR_H THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TADDR_AFTER_CLKH A/D[15:0] FFFF 9ABC TDATA_AFTER_WR_L 5678 TBEN_AFTER_AE_L BEN0 BEN1
04955-052
TWR_L_AFTER_AE_L
TRELEASE_MS_AFTER_WR_H TWR_H_AFTER_CLKH
9ABE
1234
Figure External Memory Write Cycle
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Table External Memory Read Cycle
Parameter TMS_AFTER_CLKH TADDR_AFTER_ CLKH TAE_H_AFTER_MS THOLD_ADDR_AFTER_AE_L TRD_L_AFTER_AE_L TDATA_AFTER_RD_L TRD_H_AFTER_CLKH THOLD_DATA_AFTER_RD_H TRELEASE_MS_AFTER_RD_H (XMxPAR[14:12] (!XMxPAR[10]) (!XMxPAR[10] !XMxPAR[9]) (XMxPAR[3:0] (!XMxPAR[9]) UCLK Unit
ECLK TMS_AFTER_CLKH TAE_H_AFTER_MS TRD_L_AFTER_AE_L THOLD_DATA_AFTER_RD_H TDATA_AFTER_RD_L TADDR_AFTER_CLKH A/D[15:0] BEN1 BEN0
04955-053
TRELEASE_MS_AFTER_RD_H TRD_H_AFTER_CLKH
THOLD_ADDR_AFTER_AE_L CDEF D14A 234A 89AB
FFFF
234B
Figure External Memory Read Cycle
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Table Timing Fast Mode (400 kHz)
Parameter tSHD tDSU tDHD tRSU tPSU tBUF tSUP
Description SCLOCK pulse width SCLOCK high pulse width1 Start condition hold time Data setup time Data hold time Setup time repeated start Stop condition setup time Bus-free time between stop condition start condition Rise time both CLOCK SDATA Fall time both CLOCK SDATA Pulse width spike suppressed
Slave
Master 1360 1140 251350 12.51350
Unit
tHCLK depends clock divider bits PLLCON MMR. tHCLK tUCLK/2CD.
tBUF
SDATA (I/O)
tSUP
tDSU tPSU tSHD
SCLK STOP START CONDITION CONDITION
tDHD
tDSU tRSU
tDHD
S(R) REPEATED START
Figure Compatible Interface Timing
Rev. Page
04955-054
tSUP
ADuC7019/20/21/22/24/25/26/27
Table Master Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD
Description SCLOCK pulse width SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
(SPIDIV tHCLK (SPIDIV tHCLK
tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tHCLK depends clock divider bits PLLCON MMR. tHCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY SCLOCK (POLARITY
tDAV
MOSI
BITS
MISO
BITS
04955-055
tDSU tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Table Master Mode Timing (PHASE Mode
Parameter tDAV tDOSU tDSU tDHD
Description SCLOCK pulse width SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
(SPIDIV tHCLK (SPIDIV tHCLK
tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tHCLK depends clock divider bits PLLCON MMR. tHCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY
SCLOCK (POLARITY
tDOSU
MOSI
tDAV
BITS
MISO
BITS
tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
04955-056
tDSU
ADuC7019/20/21/22/24/25/26/27
Table Slave Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD tSFS
Description SCLOCK edge SCLOCK pulse width SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time high after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR. tHCLK tUCLK/2CD.
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDAV
MISO
BITS
MOSI
BITS
04955-057
tDSU tDHD
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Table Slave Mode Timing (PHASE Mode
Parameter tDAV tDSU tDHD tDOCS tSFS
Description SCLOCK edge SCLOCK pulse width SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after edge high after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tUCLK tUCLK 12.5 12.5 12.5 12.5
Unit
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR. tHCLK tUCLK/2CD.
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDAV tDOCS
MISO
BITS
MOSI
BITS
04955-058
tDSU tDHD
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7019/20/21/22/24/25/26/27 ABSOLUTE MAXIMUM RATINGS
AGND REFGND DACGND GNDREF; 25°C, unless otherwise noted. Table
Parameter AVDD IOVDD AGND DGND IOVDD IOGND, AVDD AGND Digital Input Voltage IOGND Digital Output Voltage IOGND VREF AGND Analog Inputs AGND Analog Output AGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Thermal Impedance (40-pin CSP) Thermal Impedance (64-pin CSP) Thermal Impedance (64-pin LQFP) Thermal Impedance (80-pin LQFP) Peak Solder Reflow Temperature SnPb Assemblies sec) Pb-Free Assemblies sec) Rating -0.3 +0.3 -0.3 +0.3 -0.3 -0.3 +5.3 -0.3 IOVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -40°C +125°C -65°C +150°C 125°C 26°C/W 24°C/W 47°C/W 38°C/W 240°C 260°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only absolute maximum rating applied time.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
ADuC7019/20/21/22/24/25/26/27 CONFIGURATIONS FUNCTION DESCRIPTIONS
ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2]
ADC3/CMP1 ADC4 GNDREF DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 BM/P0.0/CMPOUT/PLAI[7]
INDICATOR
ADuC7019/ ADuC7020
VIEW (Not Scale)
P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2]
ADC4 ADC5 ADC6 ADC7 GNDREF DAC0/ADC12 DAC1/ADC13 BM/P0.0/CMPOUT/PLAI[7]
INDICATOR
ADuC7021
VIEW (Not Scale)
P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2]
P0.6/T1/MRST/PLAO[3] IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY IRQ0/P0.4/PWMTRIP/PLAO[1]
04955-064
P0.6/T1/MRST/PLAO[3] IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY IRQ0/P0.4/PWMTRIP/PLAO[1]
Figure ADuC7019/ADuC7020 Configuration
Figure ADuC7021 Configuration
ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3]
ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
INDICATOR
ADuC7022
VIEW (Not Scale)
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
Figure ADuC7022 Configuration
Rev. Page
04955-066
04955-065
ADuC7019/20/21/22/24/25/26/27
Table Function Descriptions
7019/20 7021 7022 Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Description Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Comparator Positive Input. Single-Ended Differential Analog Input (Buffered Input ADuC7019) Comparator Negative Input. Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Ground Voltage Reference ADC. optimal performance, analog power supply should separated from IOGND DGND. DAC0 Voltage Output Single-Ended Differential Analog Input DAC1 Voltage Output Single-Ended Differential Analog Input DAC2 Voltage Output Single-Ended Differential Analog Input DAC3 Voltage Output ADuC7020. ADuC7019, capacitor needs connected between this AGND/Single-Ended Differential Analog Input Test Mode Select, JTAG Test Port Input. Debug download access. Test Data JTAG Test Port Input. Debug download access. Multifunction Pin: Boot Mode. ADuC7019/20/21/22 enter serial download mode reset execute code pulled high reset through resistor General-Purpose Input-Output Port Voltage Comparator Output Programmable Logic Array Input Element Multifunction Pin, Driven After Reset: General-Purpose Output Port Timer1 Input Power-On Reset Output Programmable Logic Array Output Element Test Clock, JTAG Test Port Input. Debug download access. Test Data Out, JTAG Test Port Output. Debug download access. Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. Output On-Chip Voltage Regulator. Must connected 0.47 capacitor DGND. Ground Core Logic. General-Purpose Input-Output Port Test Reset, JTAG Test Port Input. Debug download access ADCBUSY Signal Output. Reset Input, Active Low. Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port Trip External Input Programmable Logic Array Output Element Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port ADCBUSY Signa Output Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART Programmable Logic Array Output Element Start Conversion Input Signal ADC. Serial Port Multiplexed: General-Purpose Input-Output Port Output External Clock Signal Input Internal Clock Generator Circuits UART Programmable Logic Array Output Element
Rev. Page
BM/P0.0/CMPOUT/PLAI[7]
P0.6/T1/MRST/PLAO[3]
IOGND IOVDD LVDD DGND P0.3/TRST/ADCBUSY IRQ0/P0.4/PWMTRIP/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
P2.0/SPM9/PLAO[5]/CONVSTART
P0.7/ECLK/XCLK/SPM8/PLAO[4]
ADuC7019/20/21/22/24/25/26/27
7019/20 7021 7022 Mnemonic XCLKO XCLKI P1.7/SPM7/PLAO[0] Description Output from Crystal Oscillator Inverter. Input Crystal Oscillator Inverter Input Internal Clock Generator Circuits. Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C0 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port Timer1 Input UART, I2C0 Programmable Logic Array Input Element General-Purpose Input-Output Port Programmable Logic Array Output Element Internal Voltage Reference. Must connected 0.47 capacitor when using internal reference. Analog Ground. Ground reference point analog circuitry. Analog Power.
P1.6/SPM6/PLAI[6]
P1.5/SPM5/PLAI[5]/IRQ3
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3]
P1.2/SPM2/PLAI[2]
P1.1/SPM1/PLAI[1]
P1.0/T1/SPM0/PLAI[0]
P4.2/PLAO[10] VREF AGND AVDD
Rev. Page
ADuC7019/20/21/22/24/25/26/27
ADuC7024/ADuC7025
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV AVDD AGND DACGND VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3]
INDICATOR
ADuC7024/ ADuC7025
VIEW (Not Scale)
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
Figure ADuC7024/ADuC7025 64-Lead Configuration
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3]
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV AVDD AGND DACGND VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1]
INDICATOR
ADuC7024/ ADuC7025
VIEW (Not Scale)
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART
IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2]
04955-067
04955-068
Figure ADuC7024/ADuC7025 64-Lead LQFP Configuration
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Table Function Descriptions (ADuC7024/ADuC7025 64-Lead ADuC7024/ADuC7025 64-Lead LQFP)
Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] Description Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Ground Voltage Reference ADC. optimal performance, analog power supply should separated from IOGND DGND. Bias Point Negative Analog Input Pseudo Differential Mode. Must connected ground signal convert. This bias point must between DAC0 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7025). DAC1 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7025). JTAG Test Port Input, Test Mode Select. Debug download access. JTAG Test Port Input, Test Data Debug download access General-Purpose Input-Output Port Programmable Logic Array Output Element General-Purpose Input-Output Port Programmable Logic Array Output Element Multifunction Pin: Boot Mode. ADuC7024/ADuC7025 enter download mode reset executes code pulled high reset through resistor General-Purpose Input-Output Port Voltage Comparator Output Programmable Logic Array Input Element Multifunction Pin, Driven After Reset: General-Purpose Output Port Timer1 Input Power-On Reset Output Programmable Logic Array Output Element JTAG Test Port Input, Test Clock. Debug download access. JTAG Test Port Output, Test Data Out. Debug download access. Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. Output On-Chip Voltage Regulator. Must connected 0.47 capacitor DGND. Ground Core Logic. General-Purpose Input-Output Port Phase High-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port Phase Low-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port Phase High-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port Phase Low-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port JTAG Test Port Input, Test Reset. Debug download access ADCBUSY Signal Output. Reset Input, Active Low. General-Purpose Input-Output Port Phase High-Side Output Programmable Logic Array Input General-Purpose Input-Output Port Phase Low-Side Output Programmable Logic Array Input Element Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port Trip External Input Programmable Logic Array Output Element Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port ADCBUSY Signal Output Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART Programmable Logic Array Output Element Start Conversion Input Signal ADC.
Rev. Page
P0.6/T1/MRST/PLAO[3]
IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADCBUSY P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]
IRQ1/P0.5/ADCBUSY/PLAO[2]
P2.0/SPM9/PLAO[5]/CONVSTART
ADuC7019/20/21/22/24/25/26/27
Mnemonic P0.7/ECLK/XCLK/SPM8/PLAO[4] Description Serial Port Multiplexed: General-Purpose Input-Output Port Output External Clock Signal Input Internal Clock Generator Circuits UART Programmable Logic Array Output Element Output from Crystal Oscillator Inverter. Input Crystal Oscillator Inverter Input Internal Clock Generator Circuits. General-Purpose Input-Output Port Safety Programmable Logic Array Input Element General-Purpose Input-Output Port Synchronization Input Output Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. General-Purpose Input-Output Port Programmable Logic Array Output Element General-Purpose Input-Output Port Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C0 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port Timer1 Input UART, I2C0 Programmable Logic Array Input Element General-Purpose Input-Output Port Programmable Logic Array Output Element General-Purpose Input-Output Port Programmable Logic Array Output Element General-Purpose Input-Output Port Programmable Logic Array Output Element General-Purpose Input-Output Port Programmable Logic Array Output Element Internal Voltage Reference. Must connected 0.47 capacitor when using internal reference. External Voltage Reference DACs. Range: DACGND DACVDD. Ground DAC. Typically connected AGND. Analog Ground. Ground reference point analog circuitry. Analog Power. Power Supply DACs. Typically connected AVDD. Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Comparator Positive Input. Single-Ended Differential Analog Input Comparator Negative Input.
XCLKO XCLKI P3.6/PWMTRIP/PLAI[14] P3.7/PWMSYNC/PLAI[15] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/PLAO[8] P4.1/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0]
P4.2/PLAO[10] P4.3/PLAO[11] P4.4/PLAO[12] P4.5/PLAO[13] VREF DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Rev. Page
ADuC7019/20/21/22/24/25/26/27
ADuC7026/ADuC7027
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 ADC11 DACV AVDD AVDD AGND AGND DACGND DACREF VREF REFGND P4.5/AD13/PLAO[13] P4.4/AD12/PLAO[12] P4.3/AD11/PLAO[11] P4.2/AD10/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2
INDICATOR
ADuC7026/ ADuC7027
VIEW (Not Scale)
P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/AD9/PLAO[9] P4.0/AD8/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P2.2/RS/PWM0L/PLAO[7] P2.1/WS/PWM0H/PLAO[6] P2.7/PWM1L/MS3 P3.7/AD7/PWMSYNC /PLAI[15] P3.6/AD6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY /PLAO[2]/MS0
P0.6/T1/MRST/PLAO[3]/AE P0.2/PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADC BUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1
Figure ADuC7026/ADuC7027 Configuration
Table Function Descriptions (ADuC7026/ADuC7027)
Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Description Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Ground Voltage Reference ADC. optimal performance, analog power supply should separated from IOGND DGND. Bias Point Negative Analog Input Pseudo Differential Mode. Must connected ground signal convert. This bias point must between DAC0 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7027). DAC1 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7027). DAC2 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7027). DAC3 Voltage Output Single-Ended Differential Analog Input (DAC outputs present ADuC7027).
Rev. Page
04955-069
ADuC7019/20/21/22/24/25/26/27
Mnemonic P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2 Description JTAG Test Port Input, Test Mode Select. Debug download access. JTAG Test Port Input, Test Data Debug download access. General-Purpose Input-Output Port Phase High-Side Output External Memory Byte Enable. General-Purpose Input-Output Port External Memory Access Enable. General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element Multifunction Pin: Boot Mode. ADuC7026/27 enters UART download mode reset executes code pulled high reset through resistor General-Purpose Input-Output Port Voltage Comparator Output/Programmable Logic Array Input Element External Memory Select Multifunction Pin, Driven After Reset: General-Purpose Output Port Timer1 Input Power-On Reset Output Programmable Logic Array Output Element JTAG Test Port Input, Test Clock. Debug download access. JTAG Test Port Output, Test Data Out. Debug download access. General-Purpose Input-Output Port Phase Low-Side Output External Memory Byte High Enable. Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. Output On-Chip Voltage Regulator. Must connected 0.47 capacitor DGND. Ground Core Logic. General-Purpose Input-Output Port External Memory Interface Phase High-Side Output/Programmable Logic Array Input Element General-Purpose Input-Output Port External Memory Interface Phase Low-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port External Memory Interface Phase High-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port External Memory Interface Phase Low-Side Output Programmable Logic Array Input Element General-Purpose Input-Output Port Phase High-Side Output External Memory Select General-Purpose Input-Output Port JTAG Test Port Input, Test Reset. Debug download access ADCBUSY Signal Output. General-Purpose Input-Output Port Phase Low-Side Output External Memory Select General-Purpose Input-Output Port Phase High-Side Output External Memory Select Reset Input, Active Low. General-Purpose Input-Output Port External Memory Interface Phase High-Side Output Programmable Logic Array Input General-Purpose Input-Output Port External Memory Interface Phase Low-Side Output Programmable Logic Array Input Element Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port Trip External Input Programmable Logic Array Output Element External Memory Select Multifunction Pin: External Interrupt Request Active High General-Purpose Input-Output Port ADCBUSY Signal Output Programmable Logic Array Output Element External Memory Select Serial Port Multiplexed: General-Purpose Input-Output Port UART Programmable Logic Array Output Element Start Conversion Input Signal ADC.
P0.6/T1/MRST/PLAO[3]/AE
P0.2/ PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADCBUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0
P2.0/SPM9/PLAO[5]/CONVSTART
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Mnemonic P0.7/ECLK/XCLK/SPM8/ PLAO[4] Description Serial Port Multiplexed: General-Purpose Input-Output Port Output External Clock Signal Input Internal Clock Generator Circuits UART Programmable Logic Array Output Element Output from Crystal Oscillator Inverter. Input Crystal Oscillator Inverter Input Internal Clock Generator Circuits. General-Purpose Input-Output Port External Memory Interface Safety Programmable Logic Array Input Element General-Purpose Input-Output Port External Memory Interface Synchronization Programmable Logic Array Input Element General-Purpose Input-Output Port Phase Low-Side Output External Memory Select General-Purpose Input-Output Port External Memory Write Strobe Phase HighSide Output Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Read Strobe Phase LowSide Output Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element Ground GPIO. Typically connected DGND. Supply GPIO Input On-Chip Voltage Regulator. General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART,SPI Programmable Logic Array Input Element External Interrupt Request Active High. Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C1 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port UART, I2C0 Programmable Logic Array Input Element Serial Port Multiplexed: General-Purpose Input-Output Port Timer1 Input UART, I2C0 Programmable Logic Array Input Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element General-Purpose Input-Output Port External Memory Interface Programmable Logic Array Output Element Ground Reference. Typically connected AGND. Internal Voltage Reference. Must connected 0.47 capacitor when using internal reference. External Voltage Reference DACs. Range: DACGND DACVDD. Ground DAC. Typically connected AGND. Analog Ground. Ground reference point analog circuitry. Analog Power. Power Supply DACs. Typically connected AVDD.
XCLKO XCLKI P3.6/AD6/PWMTRIP/PLAI[14] P3.7/AD7/PWMSYNC/PLAI[15] P2.7/PWM1L/MS3 P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3
P1.4/SPM4/PLAI[4]/IRQ2
P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0]
P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] REFGND VREF DACREF DACGND AGND AVDD DACVDD
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Mnemonic ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 Description Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Single-Ended Differential Analog Input Comparator Positive Input. Single-Ended Differential Analog Input Comparator Negative Input.
Rev. Page
ADuC7019/20/21/22/24/25/26/27 TYPICAL PERFORMANCE CHARACTERISTICS
(LSB)
774kSPS
774kSPS
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
04955-075
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
04955-074
Figure Typical Error, kSPS
Figure Typical Error, kSPS
1MSPS
1MSPS
(LSB)
-0.2 -0.4 -0.6
04955-077
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
04955-076
-0.8 -1.0 1000 2000 CODES 3000 4000
Figure Typical Error, MSPS
-0.1 -0.2 -0.3 -0.1 -0.2
Figure Typical Error, MSPS
-0.3 -0.4 EXTERNAL REFERENCE
04955-071
(LSB)
(LSB)
(LSB)
-0.6 EXTERNAL REFERENCE -0.7 -0.8 -0.9 -1.0
-0.5 -0.6 -0.7 -0.8
04955-072
-0.9 -1.0
Figure Typical Worst Case Error VREF, kSPS
Figure Typical Worst Case Error VREF, kSPS
Rev. Page
(LSB)
-0.5
ADuC7019/20/21/22/24/25/26/27
9000 8000 7000
6000
FREQUENCY
(dB)
5000 4000 3000
2000
04955-073
1000
1161
1162
1163
EXTERNAL REFERENCE
Figure Code Histogram Plot
Figure Typical Dynamic Performance VREF
1500
774kSPS,
69.3dB, -80.8dB, PHSN -83.4dB
1450 1400 1350
1300
CODE
(dB)
-100 -120
1250 1200 1150 1100
04955-078
1050 1000 TEMPERATURE (°C)
-160
FREQUENCY (kHz)
Figure Dynamic Performance, kSPS
Figure On-Chip Temperature Sensor Voltage Output Temperature
39.8 39.7 39.6 39.5
(mA)
1MSPS,
70.4dB, -77.2dB, PHSN -78.9dB
(dB)
-100 -120 -140 -160
04955-079
39.4 39.3 39.2 39.1 39.0 38.9
04955-080
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure Dynamic Performance, MSPS
Figure Current Consumption Temperature
Rev. Page
04955-060
-140
04955-070
(dB)
ADuC7019/20/21/22/24/25/26/27
12.05 12.00 11.95 11.90 11.85
(mA)
(mA)
11.80 11.75 11.70 11.65
04955-081
11.60 11.55 TEMPERATURE (°C)
TEMPERATURE (°C)
Figure Current Consumption Temperature
7.85 7.80
Figure Current Consumption Temperature Sleep Mode
37.4
37.2 7.75 7.70
(mA) (mA)
37.0
7.65 7.60 7.55 7.50
36.8
36.6
36.4
04955-082
7.45 7.40
TEMPERATURE (°C)
36.2
62.25
125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS)
1000.00
Figure Current Consumption Temperature
Figure Current Consumption Speed
Rev. Page
04955-084
04955-083
ADuC7019/20/21/22/24/25/26/27 TERMINOLOGY
SPECIFICATIONS
Integral Nonlinearity maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition full scale, point above last code transition. Differential Nonlinearity difference between measured ideal change between adjacent codes ADC. Offset Error deviation first code transition (0000 000) (0000 001) from ideal, that LSB. Gain Error deviation last code transition from ideal voltage (full scale LSB) after offset error been adjusted out. Signal (Noise Distortion) Ratio measured ratio signal (noise distortion) output ADC. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02 1.76) Thus, 12-bit converter, this Total Harmonic Distortion ratio harmonics fundamental.
SPECIFICATIONS
Relative Accuracy Otherwise known endpoint linearity, relative accuracy measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error. Voltage Output Settling Time amount time takes output settle within level full-scale input change.
Rev. Page
ADuC7019/20/21/22/24/25/26/27 OVERVIEW ARM7TDMI CORE
ARM7 core 32-bit reduced instruction computer (RISC). uses single 32-bit instruction data. length data bits, bits, bits. length instruction word bits. ARM7TDMI ARM7 core with four additional features: support thumb (16-bit) instruction set. support debug. support long multiplications. includes embeddedICE module support embedded system debugging. When breakpoint watchpoint encountered, processor halts enters debug state. Once debug state, processor registers inspected well Flash/EE, SRAM, memory mapped registers.
EXCEPTIONS
supports five types exceptions privileged processing mode each type. five types exceptions are: Normal interrupt IRQ. This provided service general-purpose interrupt handling internal external events. Fast interrupt FIQ. This provided service data transfer communication channel with latency. priority over IRQ. Memory abort. Attempted execution undefined instruction. Software interrupt instruction (SWI). This used make call operating system.
THUMB MODE
instruction 32-bits long. ARM7TDMI processor supports second instruction that been compressed into 16-bits, called thumb instruction set. Faster execution from 16-bit memory greater code density usually achieved using thumb instruction instead instruction set, which makes ARM7TDMI core particularly suitable embedded applications. However, thumb mode limitations: Thumb code usually uses more instructions same job. result, code usually best maximizing performance time-critical code. thumb instruction does include some instructions needed exception handling, which automatically switches core code exception handling.
Typically, programmer defines interrupt IRQ, higher priority interrupt, that faster response time, programmer define interrupt FIQ.
REGISTERS
ARM7TDMI total registers: general-purpose registers status registers. Each operating mode dedicated banked registers. When writing user-level programs, general-purpose 32-bit registers R14), program counter (R15) current program status register (CPSR) usable. remaining registers only used system-level programming exception handling. When exception occurs, some standard registers replaced with registers specific exception mode. exception modes have replacement banked registers stack pointer (R13) link register (R14) represented Figure fast interrupt mode more registers R12) fast interrupt processing. This means interrupt processing begin without need save restore these registers, thus save critical time interrupt handling process.
ARM7TDMI user guide details core architecture, programming model, both thumb instruction sets.
LONG MULTIPLY
ARM7TDMI instruction includes four extra instructions that perform 32-bit 32-bit multiplication with 64-bit result, 32-bit 32-bit multiplication-accumulation (MAC) with 64-bit result. These results achieved fewer cycles than required standard ARM7 core.
EMBEDDEDICE
EmbeddedICE provides integrated on-chip support core. EmbeddedICE module contains breakpoint watchpoint registers that allow code halted debugging purposes. These registers controlled through JTAG test port.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
(PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE USER MODE SYSTEM MODES ONLY
time longest instruction complete (the longest instruction LDM) that loads registers including time data abort entry time entry.
this time, ARM7TDMI executes instruction 0x1C (FIQ interrupt vector address). maximum total time processor cycles, which just under system using continuous 41.78 processor clock. maximum interrupt request (IRQ) latency calculation similar, must allow fact that higher priority could delay entry into handling routine arbitrary length time. This time reduced cycles command used. Some compilers have option compile without using this command. Another option part THUMB mode, where time reduced cycles. minimum latency interrupts total five cycles, which consist shortest time request take through synchronizer, plus time enter exception mode. Note that ARM7TDMI always runs (32-bit) mode when privileged modes, example, when executing interrupt service routines.
CPSR
SPSR_FIQ MODE
SPSR_SVC MODE
SPSR_ABT
USER MODE
ABORT MODE
MODE
UNDEFINED MODE
Figure Register Organization
More information relative programmer's model ARM7TDMI core architecture found following documents from ARM: DDI0029G, ARM7TDMI Technical Reference Manual DDI0100E, Architecture Reference Manual
INTERRUPT LATENCY
worst case latency fast interrupt request (FIQ) consists following: longest time request take pass through synchronizer
Rev. Page
04955-007
ADuC7019/20/21/22/24/25/26/27 MEMORY ORGANIZATION
ADuC7019/20/21/22/24/25/26/27 incorporate separate blocks memory: SRAM on-chip Flash/EE memory. Sixty-two kilobytes on-chip Flash/EE memory available user, remaining reserved factory configured boot page. These blocks mapped shown Figure
0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x40000FFFF EXTERNAL MEMORY REGION 0x40000000 RESERVED 0x30000FFFF EXTERNAL MEMORY REGION 0x30000000 RESERVED 0x20000FFFF EXTERNAL MEMORY REGION 0x20000000 RESERVED 0x10000FFFF EXTERNAL MEMORY REGION 0x10000000 RESERVED 0x0008FFFF FLASH/EE 0x00080000 RESERVED 0x00011FFF
04955-008
FLASH/EE MEMORY
total Flash/EE memory organized bits bits user space bits reserved on-chip kernel). page size this Flash/EE memory bytes. Sixty-two kilobytes Flash/EE memory available user code nonvolatile data memory. There distinction between data program code shares same space. real width Flash/EE memory bits, which means that mode (32-bit instruction), accesses Flash/EE necessary each instruction fetch. therefore recommended thumb mode when executing from Flash/EE memory optimum access speed. maximum access speed Flash/EE memory 41.78 thumb mode 20.89 full mode. More details about Flash/EE access time outlined later Execution Time from SRAM Flash/EE section this datasheet.
0x00010000 0x0000FFFF RE-MAPPABLE MEMORY SPACE (FLASH/EE SRAM) 0x00000000
SRAM
SRAM
Eight kilobytes SRAM available user, organized bits, that words. code directly from SRAM 41.78 MHz, given that SRAM array configured 32-bit wide memory array. More details about SRAM access time outlined later Execution Time from SRAM Flash/EE section this datasheet.
Figure Physical Memory
Note that default, after reset, Flash/EE memory mirrored address possible remap SRAM address clearing REMAP MMR. This remap function described more detail Flash/EE Memory section.
MEMORY MAPPED REGISTERS
memory mapped register (MMR) space mapped into upper pages memory array, accessed indirect addressing through ARM7 banked registers. space provides interface between on-chip peripherals. registers, except core registers, reside area. shaded locations shown Figure unoccupied reserved locations, should accessed user software. Table shows full memory map. access time reading from writing depends advanced microcontroller architecture (AMBA) used access peripheral. processor AMBA busses: advanced high performance (AHB) used system modules, advanced peripheral (APB) used lower performance peripheral. Access cycle, access cycles. peripherals ADuC7019/20/21/22/24/25/26/27 except Flash/EE memory, GPIOs, PWM.
MEMORY ACCESS
ARM7 core sees memory linear array byte location where different blocks memory mapped outlined Figure ADuC7019/20/21/22/24/25/26/27 memory organizations configured little endian format, which means that least significant byte located lowest byte address, most significant byte highest byte address.
BYTE BYTE BITS BYTE BYTE 0x00000004 0x00000000
04955-009
0xFFFFFFFF
Figure Little Endian Format
Rev. Page
ADuC7019/20/21/22/24/25/26/27
0xFFFFFFFF 0xFFFFFC3C
Table Complete List
0xFFFFFC00 0xFFFFF820 0xFFFFF800 0xFFFFF46C
FLASH CONTROL INTERFACE
GPIO
0xFFFFF400 0xFFFF0B54
0xFFFF0B00 0xFFFF0A14
0xFFFF0A00 0xFFFF0948
Address Name Byte address base 0xFFFF0000 0x0000 IRQSTA 0x0004 IRQSIG 0x0008 IRQEN 0x000C IRQCLR 0x0010 SWICFG 0x0100 FIQSTA 0x0104 FIQSIG1 0x0108 FIQEN 0x010C FIQCLR
Access Type
Default Value 0x00000000 0x00XXX000 0x00000000 0x00000000 0x00000000 0x00000000 0x00XXX000 0x00000000 0x00000000
Page
I2C1
0xFFFF0900 0xFFFF0848
I2C0
0xFFFF0800 0xFFFF0730
UART
0xFFFF0700 0xFFFF0620
System control address base 0xFFFF0200 0x00 0x0220 REMAP 0x0230 RSTSTA 0x01 0x0234 RSTCLR 0x00 Timer address base 0xFFFF0300 0x0300 T0LD 0x0304 T0VAL 0x0308 T0CON 0x030C T0CLRI 0x0320 T1LD 0x0324 T1VAL 0x0328 T1CON 0x032C T1CLRI 0x0330 T1CAP 0x0340 T2LD 0x0344 T2VAL 0x0348 T2CON 0x034C T2CLRI 0x0360 T3LD 0x0364 T3VAL 0x0368 T3CON 0x036C T3CLRI base address 0xFFFF0400 0x0404 POWKEY1 0x0408 POWCON 0x040C POWKEY2 0x0410 PLLKEY1 0x0414 PLLCON 0x0418 PLLKEY2
0xFFFF0600 0xFFFF0538
0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0310
BANDGAP REFERENCE
POWER SUPPLY MONITOR
OSCILLATOR CONTROL
WATCHDOG TIMER
WAKE TIMER
GENERAL PURPOSE TIMER
0x0000 0xFFFF 0x0000 0xFF 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x00000000 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x0000 0xFFFF 0x0000 0x00
TIMER
0xFFFF0300 0xFFFF0238 0xFFFF0220 0xFFFF0110 0xFFFF0000
REMAP SYSTEM CONTROL
04955-010
INTERRUPT CONTROLLER
Figure Memory Mapped Registers
0x0000 0x0003 0x0000 0x0000 0x21 0x0000
address base 0xFFFF0440 0x0440 PSMCON 0x0444 CMPCON Reference address base 0xFFFF0480 0x048C REFCON
0x0008 0x0000
0x00
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Access Address Name Byte Type address base 0xFFFF0500 0x0500 ADCCON 0x0504 ADCCP 0x0508 ADCCN 0x050C ADCSTA 0x0510 ADCDAT 0x0514 ADCRST 0x0530 ADCGN 0x0534 ADCOF address base 0xFFFF0600 0x0600 DAC0CON 0x0604 DAC0DAT 0x0608 DAC1CON 0x060C DAC1DAT 0x0610 DAC2CON 0x0614 DAC2DAT 0x0618 DAC3CON 0x061C DAC3DAT UART base address 0xFFFF0700 0x0700 COMTX COMRX COMDIV0 0x0704 COMIEN0 COMDIV1 0x0708 COMIID0 0x070C COMCON0 0x0710 COMCON1 0x0714 COMSTA0 0x0718 COMSTA1 0x071C COMSCR 0x0720 COMIEN1 0x0724 COMIID1 0x0728 COMADR 0x072C COMDIV2 Default Value 0x0600 0x00 0x01 0x00 0x00000000 0x00 0x0200 0x0200 Page Access Address Name Byte Type I2C0 base address 0xFFFF0800 0x0800 I2C0MSTA 0x0804 I2C0SSTA 0x0808 I2C0SRX 0x080C I2C0STX 0x0810 I2C0MRX 0x0814 I2C0MTX 0x0818 I2C0CNT 0x081C I2C0ADR 0x0824 I2C0BYTE 0x0828 I2C0ALT 0x082C I2C0CFG 0x0830 I2C0DIV 0x0838 I2C0ID0 0x083C I2C0ID1 0x0840 I2C0ID2 0x0844 I2C0ID3 0x0848 I2C0CCNT 0x084C I2C0FSTA I2C1 base address 0xFFFF0900 0x0900 I2C1MSTA 0x0904 I2C1SSTA 0x0908 I2C1SRX 0x090C I2C1STX 0x0910 I2C1MRX 0x0914 I2C1MTX 0x0918 I2C1CNT 0x091C I2C1ADR 0x0924 I2C1BYTE 0x0928 I2C1ALT 0x092C I2C1CFG 0x0930 I2C1DIV 0x0938 I2C1ID0 0x093C I2C1ID1 0x0940 I2C1ID2 0x0944 I2C1ID3 0x0948 I2C1CCNT 0x094C I2C1FSTA base address 0xFFFF0A00 0x0A00 SPISTA 0x0A04 SPIRX 0x0A08 SPITX 0x0A0C SPIDIV 0x0A10 SPICON Default Value 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000 Page
0x00 0x00000000 0x00 0x00000000 0x00 0x00000000 0x00 0x00000000
0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x60 0x00 0x00 0x04 0x01 0xAA 0x0000
0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000
0x00 0x00 0x00 0x1B 0x0000
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Address Name Byte base address 0xFFFF0B00 0x0B00 PLAELM0 0x0B04 PLAELM1 0x0B08 PLAELM2 0x0B0C PLAELM3 0x0B10 PLAELM4 0x0B14 PLAELM5 0x0B18 PLAELM6 0x0B1C PLAELM7 0x0B20 PLAELM8 0x0B24 PLAELM9 0x0B28 PLAELM10 0x0B2C PLAELM11 0x0B30 PLAELM12 0x0B34 PLAELM13 0x0B38 PLAELM14 0x0B3C PLAELM15 0x0B40 PLACLK 0x0B44 PLAIRQ 0x0B48 PLAADC 0x0B4C PLADIN 0x0B50 PLADOUT 0x0B54 PLALCK Access Type Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x00000000 0x00000000 0x00000000 0x00000000 0x00 Page Access Address Name Byte Type GPIO base address 0xFFFFF400 0xF400 GP0CON 0xF404 GP1CON 0xF408 GP2CON 0xF40C GP3CON 0xF410 GP4CON 0xF420 GP0DAT 0xF424 GP0SET 0xF428 GP0CLR 0xF42C GP0PAR 0xF430 GP1DAT 0xF434 GP1SET 0xF438 GP1CLR 0xF43C GP1PAR 0xF440 GP2DAT 0xF444 GP2SET 0xF448 GP2CLR 0xF450 GP3DAT 0xF454 GP3SET 0xF458 GP3CLR 0xF45C GP3PAR 0xF460 GP4DAT 0xF464 GP4SET 0xF468 GP4CLR Flash/EE base address 0xFFFFF800 0xF800 FEESTA 0xF804 FEEMOD 0xF808 FEECON 0xF80C FEEDAT 0xF810 FEEADR 0xF818 FEESIGN 0xF81C FEEPRO 0xF820 FEEHIDE base address 0xFFFFFC00 0xFC00 PWMCON 0xFC04 PWMSTA 0xFC08 PWMDAT0 0xFC0C PWMDAT1 0xFC10 PWMCFG 0xFC14 PWMCH0 0xFC18 PWMCH1 0xFC1C PWMCH2 0xFC20 PWMEN 0xFC24 PWMDAT2
Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x20000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x00222222 0x000000XX 0x000000XX 0x000000XX
Page
External memory base address 0xFFFFF000 0xF000 XMCFG 0x00 0xF010 XM0CON 0x00 0xF014 XM1CON 0x00 0xF018 XM2CON 0x00 0xF01C XM3CON 0x00 0xF020 XM0PAR 0x70FF 0xF024 XM1PAR 0x70FF 0xF028 XM2PAR 0x70FF 0xF02C XM3PAR 0x70FF
0x20 0x0000 0x07 0xXXXX 0x0000 0xFFFFFF 0x00000000 0xFFFFFFFF
0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
Depends level external interrupt pins (P0.4, P0.5, P1.4, P1.5). Depends model.
Rev. Page
ADuC7019/20/21/22/24/25/26/27 CIRCUIT OVERVIEW
analog-to-digital converter (ADC) incorporates fast, multi-channel, 12-bit ADC. operate from supplies capable providing throughput MSPS when clock source 41.78 MHz. This block provides user with multichannel multiplexer, differential track-andhold, on-chip reference, ADC. consists 12-bit successive approximation converter based around capacitor DACs. Depending input signal configuration, operate three different modes: Fully differential mode, small balanced signals Single-ended mode, single-ended signals Pseudo differential mode, single-ended signals, taking advantage common-mode rejection offered pseudo differential input
TRANSFER FUNCTION
Pseudo Differential Single-Ended Modes
pseudo differential single-ended mode, input range VREF. output coding straight binary pseudo differential single-ended modes with FS/4096, V/4096 0.61 when VREF ideal code transitions occur midway between successive integer values (that LSB, LSB, LSB, LSB). ideal input/output transfer characteristic shown Figure
1111 1111 1111 1111 1111 1110 1111 1111 1101
OUTPUT CODE
1111 1111 1100 1LSB 4096
converter accepts analog input range VREF when operating single-ended mode pseudo differential mode. fully differential mode, input signal must balanced around common-mode voltage VCM, range AVDD, with maximum amplitude VREF (see Figure 36).
AVDD 2VREF 2VREF
0000 0000 0011 0000 0000 0010 0000 0000 0001 1LSB VOLTAGE INPUT 1LSB
04955-012
0000 0000 0000
Figure Transfer Function Pseudo Differential Mode Single-Ended Mode
04955-011
2VREF
Fully Differential Mode
amplitude differential signal difference between signals applied VIN+ VIN- pins (that VIN+ VIN-). maximum amplitude differential signal therefore -VREF +VREF (that VREF). This regardless common mode (CM). common mode average signals, example, (VIN+ VIN-)/2, therefore voltage that inputs centered This results span each input being VREF/2. This voltage externally range varies with VREF (see Driving Analog Inputs section). output coding twos complement fully differential mode with VREF/4096 V/4096 1.22 when VREF designed code transitions occur midway between successive integer values (that LSB, LSB, LSB, LSB). ideal input/output transfer characteristic shown Figure
Figure Examples Balanced Signals Fully Differential Mode
high precision, drift, factory calibrated reference provided on-chip. external reference also connected described later Bandgap Reference section. Single continuous conversion modes initiated software. external CONVSTART pin, output generated from on-chip PLA, Timer0 Timer1 overflow, also used generate repetitive trigger conversions. voltage output from on-chip bandgap reference proportional absolute temperature also routed through front-end multiplexer, effectively additional channel input. This facilitates internal temperature sensor channel, which measures temperature accuracy ±3°C.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
SIGN 1111 1111 1110 1111 1111 1100 1111 1111 1010 1LSB
TRIAL WRITE
VREF 4096
CLOCK
OUTPUT CODE
0000 0000 0010 0000 0000 0000 1111 1111 1110
CONVSTART
ADCBUSY
0000 0000 0100 0000 0000 0010
04955-013
ADCDAT
DATA
Figure Transfer Function Differential Mode
INTERRUPT
TYPICAL OPERATION
Once configured control channel selection registers, converts analog input provides 12-bit result data register. bits sign bits. 12-bit result placed from shown Figure Again, should noted that fully differential mode, result represented twos complement format, pseudo differential singleended mode, result represented straight binary format.
04955-014
Figure Timing
ADuC7019
ADuC7019 identical ADuC7020 except buffered channel, ADC3, only three DACs. output buffer fourth internally connected ADC3 channel shown Figure
ADuC7019
ADC3 DAC3 ADC15
04955-016
1MSPS 12-BIT
12-BIT
SIGN BITS
12-BIT RESULT
Figure Result Format
Figure ADC3 Buffered Input
same format used simplifying software.
Current Consumption
standby mode, that powered converting, typically consumes internal reference adds During conversion, extra current multiplied sampling frequency kHz). Figure shows current consumption versus sampling frequency ADC.
Note that DAC3 output must connected capacitor AGND. This channel should used measure voltages only. calibration might necessary this channel.
MMRS INTERFACE
controlled configured eight MMRs described this section.
Timing
Figure gives details timing. Users have control clock speed number acquisition clocks ADCCON MMR. default, acquisition time eight clocks clock divider two. number extra clocks (such trial write) which gives sampling rate kSPS. conversion temperature sensor, acquisition time automatically clocks clock divider
ADCCON Register
Name ADCCON Address 0xFFFF0500 Default Value 0x0600 Access
ADCCON control register that allows programmer enable peripheral, select mode operation (either single-ended, pseudo differential fully differential mode), conversion type. This described Table
Rev. Page
04955-015
0000 0000 0000 0LSB +VREF 1LSB -VREF 1LSB VOLTAGE INPUT (VIN+ VIN-)
ADCSTA
ADCSTA
ADuC7019/20/21/22/24/25/26/27
Table ADCCON Designations
Value Description Reserved. clock speed. fADC/1. This divider provided obtain MSPS with external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. acquisition time. clocks. clocks. clocks (default value). clocks. Enable start conversion. user start type conversion command. Cleared user disable start conversion (clearing this does stop when continuously converting). Enable ADCBUSY. user enable ADCBUSY pin. Cleared user disable ADCBUSY pin. power control. user place normal mode (the must powered least before converts correctly). Cleared user place power-down mode. Conversion mode. Single-ended mode. Differential mode. Pseudo differential mode. Reserved. Conversion type. Enable CONVSTART conversion input. Enable Timer1 conversion input. Enable Timer0 conversion input. Single software conversion; sets after conversion (Bit ADCCON should cleared after starting single software conversion avoid further conversions triggered CONVSTART pin). Continuous software conversion. conversion. Reserved.
ADCCP Register
Name ADCCP Address 0xFFFF0504 Default Value 0x00 Access
ADCCP positive channel selection register. This described Table Table ADCCP1 Designation
Value Description Reserved Positive channel selection bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Temperature sensor AGND (self-diagnostic feature) Internal reference (self-diagnostic feature) AVDD/2 Reserved
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others
channel availability depends part model. Ordering Guide details.
Other
Rev. Page
ADuC7019/20/21/22/24/25/26/27
ADCCN Register
Name ADCCN Address 0xFFFF0508 Default Value 0x01 Access
ADCRST resets digital interface ADC. Writing value this register resets registers their default value.
ADCCN negative channel selection register. This described Table Table ADCCN Designation
Value Description Reserved Negative channel selection bits ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Internal reference (self-diagnostic feature) Reserved
ADCGN Register
Name ADCGN Address 0xFFFF0530 Default Value 0x0200 Access
ADCGN 10-bit gain calibration register.
ADCOF Register
Name ADCOF Address 0xFFFF0534 Default Value 0x0200 Access
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others
ADCOF 10-bit offset calibration register.
CONVERTER OPERATION
incorporates successive approximation (SAR) architecture involving charge-sampled input stage. This architecture operate three different modes: differential, pseudo differential, single-ended.
Differential Mode
ADuC7019/20/21/22/24/25/26/27 each contain successive approximation based capacitive DACs. Figure Figure show simplified schematics acquisition conversion phase, respectively. comprised control logic, SAR, capacitive DACs. Figure (the acquisition phase), closed Position comparator held balanced condition, sampling capacitor arrays acquire differential signal input.
CAPACITIVE AIN0 AIN11 CHANNEL- CAPACITIVE
04955-017
ADCSTA Register
Name ADCSTA Address 0xFFFF050C Default Value 0x00 Access
ADCSTA status register that indicates when conversion result ready. ADCSTA register contains only bit, ADCReady (Bit representing status ADC. This conversion, generating interrupt. cleared automatically reading ADCDAT MMR. When performing conversion, status read externally ADCBUSY pin. This high during conversion. When conversion finished, ADCBUSY goes back low. This information available P0.5 (see General-Purpose section) enabled ADCCON register.
CHANNEL+
COMPARATOR
CONTROL LOGIC
VREF
Figure Acquisition Phase
ADCDAT Register
Name ADCDAT Address 0xFFFF0510 Default Value 0x00000000 Access
ADCDAT data result register. Hold 12-bit result shown Figure
ADCRST Register
Name ADCRST Address 0xFFFF0514 Default Value 0x00 Access
When starts conversion, shown Figure opens, then move Position This causes comparator become unbalanced. Both inputs disconnected once conversion begins. control logic charge redistribution DACs used subtract fixed amounts charge from sampling capacitor arrays bring comparator back into balanced condition. When comparator rebalanced, conversion complete. control logic generates ADC's output code. output impedances sources driving VIN+ VIN- pins must matched; otherwise, inputs have different settling times, resulting errors.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
CAPACITIVE AIN0 AIN11 CHANNEL- CAPACITIVE
04955-018
CHANNEL+
COMPARATOR
CONTROL LOGIC
capacitors, Figure typically primarily attributed capacitance. resistors lumped components made resistance switches. value these resistors typically about capacitors, ADC's sampling capacitors typically have capacitance
AVDD
VREF
Figure Conversion Phase
Pseudo Differential Mode
pseudo differential mode, Channel- linked VIN- ADuC7019/20/21/22/24/25/26/27. switches between (Channel-) (VREF). VIN- must connected ground voltage. input signal VIN+ then vary from VIN- VREF VIN-. Note that VIN- must chosen that VREF VIN- exceed AVDD.
CAPACITIVE AIN0 AIN11 VIN- CAPACITIVE
04955-019
AVDD
04955-021
CHANNEL+
COMPARATOR
Figure Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed
CONTROL LOGIC
VREF CHANNEL-
Figure Pseudo Differential Mode
Single-Ended Mode
single-ended mode, always connected internally ground. VIN- floating. input signal range VIN+ VREF.
CAPACITIVE AIN0 AIN11 CHANNEL- CHANNEL+ COMPARATOR
applications, removing high frequency components from analog input signal recommended using low-pass filter relevant analog input pins. applications where harmonic distortion signal-to-noise ratio critical, analog input should driven from impedance source. Large source impedances significantly affect performance ADC. This necessitate input buffer amplifier. choice function particular application. Figure Figure give example front end.
ADuC702x
ADC0 0.01F
04955-061
CONTROL LOGIC
Figure Buffering Single-Ended/Pseudo Differential Input
ADuC702x
CAPACITIVE
04955-020
ADC0 VREF
04955-062
ADC1
Figure Single-Ended Mode
Analog Input Structure
Figure shows equivalent circuit analog input structure ADC. four diodes provide protection analog inputs. Care must taken ensure that analog input signals never exceed supply rails more than This would cause these diodes become forward biased start conducting into substrate. These diodes conduct without causing irreversible damage part.
Figure Buffering Differential Inputs
When amplifier used drive analog input, source impedance should limited values lower than maximum source impedance depends amount total harmonic distortion (THD) that tolerated. increases source impedance increases performance degrades.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
DRIVING ANALOG INPUTS
Internal external reference used ADC. differential mode operation, there restrictions common-mode input signal (VCM), which dependent reference value supply voltage used ensure that signal remains within supply rails. Table gives some calculated some conditions. Table Ranges
AVDD VREF 2.048 1.25 2.048 1.25 1.25 1.024 0.75 1.25 1.024 0.75 2.05 2.276 2.55 1.75 1.976 2.25 Signal Peak-to-Peak 2.048 1.25 2.048 1.25
TEMPERATURE SENSOR
ADuC7019/20/21/22/24/25/26/27 provide voltage output from on-chip bandgap references proportional absolute temperature. This voltage output also routed through front-end multiplexer (effectively additional channel input) facilitating internal temperature sensor channel, measuring temperature accuracy ±3°C.
BANDGAP REFERENCE
Each ADuC7019/20/21/22/24/25/26/27 provides on-chip bandgap reference which used DAC. This internal reference also appears VREF pin. When using internal reference, 0.47 capacitor must connected from external VREF AGND ensure stability fast response during conversions. This reference also connected external (VREF) used reference other circuits system. external buffer required because drive capability VREF output. programmable option also allows external reference input VREF pin.
CALIBRATION
default, factory values written offset (ADCOF) gain coefficient registers (ADCGN) yield optimum performance terms end-point errors linearity standalone operation part. (See Specifications section.) system calibration required, possible modify default offset gain coefficients improve end-point errors, note that modification factory ADCOF ADCGN values degrade linearity performance. system offset error correction, channel input stage must tied AGND. continuous software conversion loop must implemented modifying value ADCOF until result (ADCDAT) reads code Offset error correction done digitally resolution 0.25 range ±3.125% VREF. system gain error correction, channel input stage must tied VREF. continuous software conversion loop must implemented modify value ADCOF until result (ADCDAT) reads code 4094 4095. Similar offset calibration, gain calibration resolution 0.25 with range VREF.
REFCON Register
Name REFCON Address 0xFFFF048C Default Value 0x00 Access
bandgap reference interface consists 8-bit REFCON described Table Table REFCON Designations
Description Reserved. Internal reference power-down enable. user place internal reference power-down mode external reference. Cleared user place internal reference normal mode conversions. Internal reference output enable. user connect internal reference VREF pin. reference used external component needs buffered. Cleared user disconnect reference from VREF pin.
Rev. Page
ADuC7019/20/21/22/24/25/26/27 NONVOLATILE FLASH/EE MEMORY
ADuC7019/20/21/22/24/25/26/27 incorporate Flash/EE memory technology on-chip provide user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory programmed in-system byte level, although must first erased. erase performed page blocks. result, flash memory often more correctly referred Flash/EE memory. Overall, Flash/EE memory represents step closer ideal memory device that includes nonvolatility, in-circuit programmability, high density, cost. Incorporated ADuC7019/20/21/22/24/25/26/27, Flash/EE memory technology allows user update program code space incircuit, without need replace time programmable (OTP) devices remote operating nodes. Each ADuC7019/20/21/22/24/25/26/27 contains array Flash/EE memory. lower available user upper contain permanently embedded firmware, allowing in-circuit serial download. These embedded firmware also contain power-on configuration routine that downloads factory calibrated coefficients various calibrated peripherals (such ADC, temperature sensor, bandgap references). This embedded firmware hidden from user code.
SECURITY
Flash/EE memory available user read write protected. FEEPRO/FEEHIDE (see Table protects from being read through JTAG also parallel programming mode. other bits this register protect writing flash memory. Each protects four pages, that Write protection activated types access.
Three Levels Protection
Protection removed writing directly into FEEHIDE MMR. This protection does remain after reset. Protection writing into FEEPRO MMR. only takes effect after save protection command reset. FEEPRO protected avoid direct access. saved once must entered again modify FEEPRO. mass erase sets back also erases user code. Flash permanently protected using FEEPRO particular value key: Entering again modify FEEPRO register allowed.
PROGRAMMING
Flash/EE memory programmed in-circuit, using serial download mode JTAG mode provided.
Sequence Write
Write FEEPRO corresponding page protected. Enable protection setting FEEMOD (Bit must Write 32-bit FEEADR, FEEDAT. write command FEECON; wait read successful monitoring FEESTA. Reset part.
Serial Downloading (In-Circuit Programming)
ADuC7019/20/21/22/24/25/26/27 facilitate code download standard UART serial port port. parts enter serial download mode after reset power cycle pulled through external resistor. Once serial download mode, user download code full Flash/EE memory while device in-circuit target application hardware. executable serial download provided part development system serial downloading UART. application note available www.analog.com/microconverter describing protocol serial downloading UART I2C.
remove modify protection, same sequence used with modified value FEEPRO. chosen value then memory protection cannot removed. Only mass erase unprotects part, also erases user code. sequence write illustrated following example (this protects writing pages Flash):
FEEPRO=0xFFFFFFFD; FEEMOD=0x48; FEEADR=0x1234; FEEDAT=0x5678; FEECON= 0x0C; //Protect pages //Write enable //16 value //16 value Write command
JTAG Access
JTAG protocol uses on-chip JTAG interface facilitate code download debug. application note available www.analog.com/microconverter describing protocol JTAG. possible write single Flash/EE location address twice. single address written more than twice, then data within Flash/EE memory corrupted. That possible walk zeros only byte wise.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
same sequence should followed protect part permanently with FEEADR FEEDAT
FEECON Register
Name FEECON Address 0xFFFFF808 Default Value 0x07 Access
FLASH/EE CONTROL INTERFACE
Serial, parallel, JTAG programming Flash/EE control interface, which includes eight MMRs outlined this section.
FEECON 8-bit command register. commands described Table Table Command Codes FEECON
Code 0x00 0x011 0x021 0x031 Command Null Single Read Single Write Erase-Write Description Idle state. Load FEEDAT with 16-bit data. Indexed FEEADR. Write FEEDAT address pointed FEEADR. This operation takes Erase page indexed FEEADR write FEEDAT location pointed FEEADR. This operation takes Compare contents location pointed FEEADR data FEEDAT. result comparison returned FEESTA Erase page indexed FEEADR. Erase user space. kernel protected. This operation takes 2.48 seconds. prevent accidental execution, command sequence required execute this instruction. Command Sequence Executing Mass Erase section. Default command. write allowed. This operation takes cycles. Write handle maximum data bits takes maximum Automatically erases page indexed write; writes pages without running erase command. This command takes erase page data write. Reserved. Give signature Flash/EE 24-bit FEESIGN MMR. This operation takes 32,778 clock cycles. This command only once. value FEEPRO saved removed only with mass erase (0x06) key. Reserved. Reserved. operation; interrupt generated.
FEESTA Register
Name FEESTA Address 0xFFFFF800 Default Value 0x20 Access
FEESTA read-only register that reflects status flash control interface described Table Table FEESTA Designations
Description Reserved. Burst command enable. when command burst command: 0x07, 0x08, 0x09. Cleared when other command. Reserved. Flash interrupt status bit. automatically when interrupt occurs, that when command complete Flash/EE interrupt enable FEEMOD register set. Cleared when reading FEESTA register. Flash/EE controller busy. automatically when controller busy. Cleared automatically when controller busy. Command fail. automatically when command completes unsuccessfully. Cleared automatically when reading FEESTA register. Command pass. MicroConverter when command completes successfully. Cleared automatically when reading FEESTA register.
0x041
Single Verify
0x051 0x061
Single Erase Mass Erase
0x07 0x08 0x09
Burst Read Burst ReadWrite Erase Burst Read-Write
FEEMOD Register
Name FEEMOD Address 0xFFFFF804 Default Value 0x0000 Access 0x0A 0x0B Reserved Signature
FEEMOD sets operating mode flash control interface. Table shows FEEMOD designations. Table FEEMOD Designations
Description Reserved. Reserved. This should always Reserved. These bits should always except when writing keys. Sequence Write section. Flash/EE interrupt enable. user enable Flash/EE interrupt. interrupt occurs when command complete. Cleared user disable Flash/EE interrupt. Erase/write command protection. user enable erase write commands. Cleared protect Flash against erase/write command. Reserved. These bits should always
0x0C
Protect
0x0D 0x0E 0x0F
Reserved Reserved Ping
FEECON always reads 0x07 immediately after execution these commands.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
FEEDAT Register
Name FEEDAT Address 0xFFFFF80C Default Value 0xXXXX Access
EXECUTION TIME FROM SRAM FLASH/EE
Execution from SRAM
Fetching instructions from SRAM takes clock cycle access time SRAM clock cycle minimum. However, instruction involves reading writing data memory, extra cycle must added data SRAM three cycles data Flash/EE), cycle execute instruction, cycles 32-bit data from Flash/EE. control flow instruction branch instruction, example) takes cycle fetch also takes cycles fill pipeline with instructions.
FEEDAT 16-bit data register.
FEEADR Register
Name FEEADR Address 0xFFFFF810 Default Value 0x0000 Access
FEEADR another 16-bit address register.
FEESIGN Register
Name FEESIGN Address 0xFFFFF818 Default Value 0xFFFFFF Access
Execution from Flash/EE
Because Flash/EE width bits access time 16-bit words execution from Flash/EE cannot done cycle done from SRAM when Also, some dead times needed before accessing data value bits. mode, where instructions bits, cycles needed fetch instruction when thumb mode, where instructions bits, cycle needed fetch instruction. Timing identical both modes when executing instructions that involve using Flash/EE data memory. instruction executed control flow instruction, extra cycle needed decode address program counter then four cycles needed fill pipeline. data-processing instruction involving only core register does require extra clock cycle. However, involves data Flash/EE, extra clock cycle needed decode address data, cycles needed 32-bit data from Flash/EE. extra cycle must also added before fetching another instruction. Data transfer instructions more complex summarized Table Table Execution Cycles ARM/Thumb Mode
Instructions LDM/PUSH STR2 STRH STRM/POP
FEESIGN 24-bit code signature.
FEEPRO Register
Name FEEPRO Address 0xFFFFF81C Default Value 0x00000000 Access
FEEPRO provides immediate protection. does require software keys. description Table
FEEHIDE Register
Name FEEHIDE Address 0xFFFFF820 Default Value 0xFFFFFFFF Access
FEEHIDE provides protection following subsequent reset MMR. requires software key. description Table Table FEEPRO FEEHIDE Designations
Description Read protection. Cleared user protect code. user allow reading code. Write protection pages 120, pages 116, pages Cleared user protect pages writing. user allow writing pages.
Command Sequence Executing Mass Erase
FEEDAT=0x3CFF; FEEADR 0xFFC3; FEEMOD= FEEMOD|0x8; //Erase enable FEECON=0x06; //Mass erase command
Fetch Cycles
Dead Time
Data Access
Dead Time
number data load store multiple load/store instruction 16). SWAP instruction combines instruction with only fetch, giving total cycles plus
Rev. Page
ADuC7019/20/21/22/24/25/26/27
RESET REMAP
exception vectors situated bottom memory array, from address 0x00000000 address 0x00000020 shown Figure
0xFFFFFFFF
Reset Operation
There four kinds reset: external, power-on, watchdog expiation, software force. RSTSTA register indicates source last reset, RSTCLR allows clearing RSTSTA register. These registers used during reset exception service routine identify source reset. RSTSTA null, reset external.
REMAP Register
KERNEL INTERRUPT SERVICE ROUTINES 0x0008FFFF FLASH/EE 0x00080000
Name REMAP
Address 0xFFFF0220
Default Value 0xXX1
Access
Depends model.
Table REMAP Designations
0x00011FFF INTERRUPT SERVICE ROUTINES SRAM 0x00010000
Name
MIRROR SPACE EXCEPTION VECTOR ADDRESSES 0x00000020 0x00000000 0x00000000
04955-022
Figure Remap Exception Execution
Remap
default, after reset, Flash/EE mirrored bottom memory array. remap function allows programmer mirror SRAM bottom memory array, which facilitates execution exception routines from SRAM instead from Flash/EE. This means exceptions executed twice fast, being executed 32-bit mode, SRAM being 32-bit wide instead 16-bit wide Flash/EE memory.
Description Read-Only Bit. Indicates size Flash/EE memory available. this set, only Flash/EE memory available. Read-Only Bit. Indicates size SRAM memory available. this set, only SRAM available. Reserved. Remap Bit. user remap SRAM address 0x00000000. Cleared automatically after reset remap Flash/EE memory address 0x00000000.
RSTSTA Register
Name RSTSTA Address 0xFFFF0230 Default Value 0x01 Access
Remap Operation
When reset occurs ADuC7019/20/21/22/24/25/26/27, execution starts automatically factory programmed internal configuration code. This kernel hidden cannot accessed user code. ADuC7019/20/21/22/24/25/26/27 normal mode high), then they execute power-on configuration routine kernel then jump reset vector address, 0x00000000, execute user's reset exception routine. Because Flash/EE mirrored bottom memory array reset, reset interrupt routine must always written Flash/EE. remap done from Flash/EE setting REMAP register. Precaution must taken execute this command from Flash/EE, above address 0x00080020, from bottom array this replaced SRAM. This operation reversible. Flash/EE remapped address 0x00000000 clearing REMAP MMR. Precaution must again taken execute remap function from outside mirrored area. kind reset remaps Flash/EE memory bottom array.
Table RSTSTA Designations
Description Reserved. Software Reset. user force software reset. Cleared setting corresponding RSTCLR. Watchdog Timeout. automatically when watchdog timeout occurs. Cleared setting corresponding RSTCLR. Power-On Reset. automatically when power-on reset occurs. Cleared setting corresponding RSTCLR.
RSTCLR Register
Name RSTCLR Address 0xFFFF0234 Default Value 0x00 Access
Rev. Page
ADuC7019/20/21/22/24/25/26/27 OTHER ANALOG PERIPHERALS
ADuC7019/20/21/22/24/25/26/27 incorporate two, three, four 12-bit voltage output DACs on-chip depending model. Each rail-to-rail voltage output buffer capable driving kF/100 Each three selectable ranges: VREF (internal bandgap reference), DACREF, AVDD. DACREF equivalent external reference DAC. signal range AVDD.
DACxDAT Registers
Name DAC0DAT DAC1DAT DAC2DAT DAC3DAT Address 0xFFFF0604 0xFFFF060C 0xFFFF0614 0xFFFF061C Default Value 0x00000000 0x00000000 0x00000000 0x00000000 Access
Table DAC0DAT Designations
Description Reserved. 12-bit data DAC0. Reserved.
MMRs Interface
Each configurable independently through control register data register. These registers identical four DACs. Only DAC0CON (see Table DAC0DAT (see Table described detail this section.
Using DACs
on-chip architecture consists resistor string followed output buffer amplifier, functional equivalent which shown Figure
AVDD VREF DACREF DAC0 OUTPUT BUFFER BYPASSED FROM
DACxCON Registers
Name DAC0CON DAC1CON DAC2CON DAC3CON Address 0xFFFF0600 0xFFFF0608 0xFFFF0610 0xFFFF0618 Default Value 0x00 0x00 0x00 0x00 Access
Table DAC0CON Designations
Value Name DACCLK Description Reserved. Update Rate. user update using Timer1. Cleared user update using HCLK (core clock). Clear Bit. user enable normal operation. Cleared user reset data register zero. Reserved. This should left Reserved. This should left Range Bits. Power-Down Mode. output tri-state. DACREF Range. VREF (2.5 Range. AVDD Range.
04955-023
DACCLR
Figure Structure
illustrated Figure reference source each user selectable software. either AVDD, VREF, DACREF. 0-to-AVDD mode, output transfer function spans from voltage AVDD pin. 0-to-DACREF mode, output transfer function spans from voltage DACREF pin. 0-to-VREF mode, output transfer function spans from internal reference, VREF. output buffer amplifier features true rail-to-rail output stage implementation. This means that, unloaded, each output capable swinging within less than both AVDD ground. Moreover, DAC's linearity specification (when driving resistive load ground) guaranteed through full transfer function except codes 100, and, 0-to-AVDD mode only, codes 3995 4095.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Linearity degradation near ground caused saturation output amplifier, general representation effects (neglecting offset gain error) illustrated Figure dotted line Figure indicates ideal transfer function, solid line represents what transfer function might look like with endpoint nonlinearities saturation output amplifier. Note that Figure represents transfer function 0-to-AVDD mode only. 0-to-VREF 0-to-DACREF modes (with VREF AVDD DACREF AVDD), lower nonlinearity similar. However, upper portion transfer function follows "ideal" line right (VREF this case, AVDD), showing signs endpoint linearity errors.
AVDD AVDD 100mV
POWER SUPPLY MONITOR
power supply monitor regulates IOVDD supply ADuC7019/20/21/22/24/25/26/27. indicates when IOVDD supply drops below supply trip points. monitor function controlled PSMCON register. enabled IRQEN FIQEN register, then monitor interrupts core using PSMI PSMCON MMR. This immediately cleared once goes high. This monitor function allows user save working registers avoid possible data loss supply brown-out conditions. also ensures that normal code execution does resume until safe supply level been established.
PSMCON Register
Name PSMCON Address 0xFFFF0440 Default Value 0x0008 Access
Table PSMCON Descriptions
100mV 0x000 0xFFF
04955-024
Name
Figure Endpoint Nonlinearities Amplifier Saturation
endpoint nonlinearities conceptually illustrated Figure worse function output loading. Most ADuC7019/20/21/22/24/25/26/27's data sheet specifications assume resistive load ground output. output forced source sink more current, nonlinear regions bottom (respectively) Figure become larger. With larger current demands, this significantly limit output voltage swing.
PSMEN
PSMI
Description Comparator Bit. This read-only directly reflects state comparator. Read indicates that IOVDD supply above selected trip point powerdown mode. Read indicates IOVDD supply below selected trip point. This should before leaving interrupt service routine. Trip Point Selection Bits. 2.79 3.07 Power Supply Monitor Enable Bit. enable power supply monitor circuit. Clear disable power supply monitor circuit. Power Supply Monitor Interrupt Bit. This high MicroConverter once when goes low, indicating supply. PSMI used interrupt processor. Once returns high, PSMI cleared writing this location. write effect. There timeout delay; PSMI immediately cleared once goes high.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
COMPARATOR
ADuC7019/20/21/22/24/25/26/27 integrate voltage comparators. positive input multiplexed with ADC2 negative input options: ADC3 DAC0. output comparator configured generate system interrupt, routed directly programmable logic array, start conversion, external pin, CMPOUT, shown Figure Table CMPCON Descriptions
Value Name Description Reserved. Comparator Enable Bit. user enable comparator. Cleared user disable comparator. Comparator Negative Input Select Bits. AVDD/2. ADC3 Input. DAC0 Output. Reserved. Comparator Output Configuration Bits. Reserved. Reserved. Output CMPOUT. IRQ. Comparator Output Logic State Bit. When low, comparator output high positive input (CMP0) above negative input (CMP1). When high, comparator output high positive input below negative input. Response Time. Comparator Hysteresis Bit. user have hysteresis about Cleared user have hysteresis. Comparator Output Rising Edge Interrupt. automatically when rising edge occurs monitored voltage (CMP0). Cleared user writing this bit. Comparator Output Falling Edge Interrupt. automatically when falling edge occurs monitored voltage (CMP0). Cleared user.
CMPEN
CMPIN
ADC2/CMP0 ADC3/CMP1 DAC0
CMPOC
P0.0/CMPOUT
Figure Comparator
Hysteresis
Figure shows input offset voltage hysteresis terms defined. Input offset voltage (VOS) difference between center hysteresis range ground level. This either positive negative. hysteresis voltage (VH) width hysteresis range.
COMPOUT
04955-025
CMPOL
CMPRES
COMP0
04955-063
CMPHYST
Figure Comparator Hysteresis Transfer Function
Comparator Interface
comparator interface consists 16-bit MMR, CMPCON, which described Table
CMPORI
CMPCON Register
Name CMPCON Address 0xFFFF0444 Default Value 0x0000 Access CMPOFI
Rev. Page
ADuC7019/20/21/22/24/25/26/27
OSCILLATOR PLL-POWER CONTROL
Clocking System
Each ADuC7019/20/21/22/24/25/26/27 integrates 32.768 oscillator, clock divider, PLL. locks onto multiple (1275) internal oscillator external 32.768 crystal provide stable 41.78 clock system. allow power saving, core operate this frequency, binary submultiples default core clock clock divided 5.22 MHz. core clock frequency also come from external clock ECLK described Figure core clock outputted ECLK when using internal oscillator external crystal.
External Crystal Selection
switch external crystal, clear OSEL PLLCON (see Table 32). noisy environments, noise might couple external crystal pins could loose lock momentarily. interrupt provided interrupt controller. core clock halted immediately this interrupt only serviced once lock been restored. case crystal loss, watchdog timer should used. During initialization, test RSTSTA determine reset came from watchdog timer.
External Clock Selection
switch external clock P0.7, configure P0.7 Mode MDCLK bits External clock providing tolerance
WATCHDOG TIMER
INT. 32kHz* OSCILLATOR
CRYSTAL OSCILLATOR
XCLKO XCLKI
Power Control System
WAKEUP TIMER POWER OCLK 32.768kHz 41.78MHz MDCLK UCLK ANALOG PERIPHERALS P0.7/XCLK
choice operating modes available ADuC7019/20/ 21/22/24/25/26/27. Table describes what part powered different modes indicates power-up time. Table gives some typical values total current consumption (analog digital supply currents) different modes depending clock divider bits. turned off. Note that these values also include current consumption regulator other parts test board which these values measured.
CORE
/2CD HCLK
04955-026
*32.768kHz
P0.7/ECLK
Figure Clocking System
selection clock source PLLCON register. default, part uses internal oscillator feeding PLL.
Table Operating Modes
Mode Active Pause Sleep Stop Core Peripherals XTAL/T2/T3 IRQ0 IRQ3 Start-up/Power-on Time 1.58
Table Typical Current Consumption 25°C
PC[2-0] Mode Active Pause Sleep Stop 33.1 22.7 21.2 13.3 13.8 6.45 3.85
Rev. Page
ADuC7019/20/21/22/24/25/26/27
MMRs Keys
operating mode, clocking mode, programmable clock divider controlled MMRs, PLLCON (see Table POWCON (see Table 33). PLLCON controls operating mode clock system, while POWCON controls core clock frequency power-down mode. prevent accidental programming, certain sequence (see Table followed write PLLCON POWCON registers. Table POWCON Designations
Value Name Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 IRQ3 Timer2 wake-up ADuC7019/20/21/22/24/25/26/27. Stop mode. IRQ0 IRQ3 wakeup ADuC7019/20/21/22/24/25/ 26/27. Reserved. Reserved. clock divider bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. 2.61 MHz. 1.31 MHz. kHz. kHz.
PLLKEYx Registers
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access Others
PLLCON Register
Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access
POWKEYx Registers
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access
Table PLLCON POWCON Write Sequence
POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access
PLLCON PLLKEY1 0xAA PLLCON 0x01 PLLKEY2 0x55
POWCON POWKEY1 0x01 POWCON User Value POWKEY2 0xF4
Table PLLCON Designations
Value Name OSEL Description Reserved. input selection. user internal oscillator. default. Cleared user external crystal. Reserved. Clocking modes. Reserved. PLL. Default configuration. Reserved. External clock P0.7 pin.
MDCLK
Rev. Page
ADuC7019/20/21/22/24/25/26/27 DIGITAL PERIPHERALS
THREE-PHASE
Each ADuC7019/20/21/22/24/25/26/27 provides flexible programmable, three-phase pulse-width modulation (PWM) waveform generator. programmed generate required switching patterns drive three-phase voltage source inverter induction motor control (ACIM). Note that only active high patterns produced. generator produces three pairs signals output pins (PWM0H, PWM0L, PWM1H, PWM1L, PWM2H, PWM2L). output signals consist three high-side drive signals three low-side drive signals. switching frequency dead time generated patterns programmable using PWMDAT0 PWMDAT1 MMRs. addition, three duty-cycle control registers (PWMCH0, PWMCH1, PWMCH2) directly control duty cycles three pairs signals. Each output signals enabled disabled separate output enable bits PWMEN register. addition, three control bits PWMEN register permit crossover signals pair. crossover mode, signal destined high-side switch diverted complementary low-side output. signal destined low-side switch diverted corresponding high-side output signal. many applications, there need provide isolation barrier gate-drive circuits that turn power devices inverter. general, there common isolation techniques, optical isolation using opto-couplers, transformer isolation using pulse transformers. controller permits mixing output signals with high frequency chopping signal permit easy interface such pulse transformers. features this gate-drive chopping mode controlled PWMCFG register. 8-bit value within PWMCFG register directly controls chopping frequency. High frequency chopping independently enabled high-side low-side outputs using separate control bits PWMCFG register. generator operate distinct modes, single update mode double update mode. single update mode, duty cycle values programmable only once period, that resulting patterns symmetrical about midpoint period. double update mode, second updating duty cycle values implemented midpoint period. double update mode, also possible produce asymmetrical patterns that produce lower harmonic distortion three-phase inverters. This technique permits closed-loop controllers change average voltage applied machine windings faster rate. result, faster closed-loop bandwidths achieved. operating mode block selected control PWMCON register. single update mode, PWMSYNC pulse produced start each period. double update mode, additional PWMSYNC pulse produced midpoint each period. block also provide internal synchronization pulse PWMSYNC that synchronized switching frequency. single update mode, pulse produced start each period. double update mode, additional pulse produced mid-point each period. width pulse programmable through PWMDAT2 register. block also accept external synchronization pulse PWMSYNC pin. selection external synchronization internal synchronization PWMCON register. SYNC input timing synchronized internal peripheral clock, which selected PWMCON register. external synchronization pulse from chip asynchronous internal peripheral clock (typical case), external PWMSYNC considered asynchronous should synchronized. synchronization logic adds latency jitter from external pulse actual outputs. size pulse PWMSYNC must greater than core clock periods. signals produced ADuC7019/20/21/22/24/ 25/26/27 shut dedicated asynchronous shutdown pin, PWMTRIP. When brought low, PWMTRIP instantaneously places outputs state (high). This hardware shutdown mechanism asynchronous that associated disable circuitry does through clocked logic. This ensures correct shutdown even event core clock loss. Status information about system available user PWMSTA register. particular, state PWMTRIP available, well status that indicates whether operation first half second half period.
Rev. Page
ADuC7019/20/21/22/24/25/26/27
40-Pin Package Devices
40-pin package devices, outputs directly accessible, described General-Purpose section. channel brought GPIO shown this example:
PWMCON 0x1; PWMDAT0 0x055F; enables switching freq
Output Control Unit. This block redirect outputs three-phase timing unit each channel either high-side low-side output. addition, output control unit allows individual enabling/disabling each output signals. Gate Drive Unit. This block generate high frequency chopping frequency subsequent mixing with signals. Shutdown Controller. This block takes care shutdown PWMTRIP generates correct reset signal timing unit.
Configure Port Pins GP4CON 0x300; P4.2 output GP3CON 0x1; P3.0 configured output PWM0 //(internally) PWM0 onto P4.2 PLAELM8 0x0035; PLAELM10 0x0059; P3.0 (PWM output) input element from element
PWMSYNC pulse control unit generates internal synchronization pulse also controls whether external PWMSYNC used not. controller driven ADuC7019/20/21/22/24/ 25/26/27 core clock frequency capable generating interrupts core. interrupt generated occurrence PWMSYNC pulse, other generated occurrence shutdown action.
Description Block
functional block diagram controller shown Figure generation output signals pins PWM0H PWM2L controlled four important blocks: Three-Phase Timing Unit. core controller, generates three pairs complemented deadtime-adjusted, center-based signals.
CONFIGURATION REGISTERS DUTY CYCLE REGISTERS PWMCON PWMDAT0 PWMCH0 PWMDAT1 PWMCH1 PWMDAT2 PWMCH2
PWMEN
PWMCFG
SHUTDOWN CONTROLLER CORE CLOCK INTERRUPT CONTROLLER
THREE-PHASE TIMING UNIT
OUTPUT CONTROL UNIT
GATE DRIVE UNIT
PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L
SYNC PWMSYNC PWMTRIP
04955-027
Figure Overview Controller
Rev. Page
ADuC7019/20/21/22/24/25/26/27
Three-Phase Timing Unit Switching Frequency (PWMDAT0 MMR)
switching frequency controlled period register, PWMDAT0. fundamental timing unit controller tCORE 1/fCORE where fCORE core frequency MicroConverter. PWMDAT1 register 10-bit register with maximum value 0x3FF 1023), which corresponds maximum programmed dead time TD(max) 1023 tCORE 1023 48.97 core clock 41.78 Obviously, dead time programmed zero writing PWMDAT1 register.
Operating Mode (PWMCON, PWMSTA MMRs)
Therefore, 41.78 fCORE, fundamental time increment value written PWMDAT0 register effectively number fCORE clock increments period. required PWMDAT0 value function desired switching frequency (fPWN) given PWMDAT0 fCORE/(2 fPWM) Therefore, switching period, written PWMDAT0 tCORE largest value that written 16-bit PWMDAT0 65535, which corresponds minimum switching frequency fPWM(min) 41.78 106/(2 65535) 318.75 Note that PWMDAT0 value defined should used. single update mode, single PWMSYNC pulse produced each period. rising edge this signal marks start cycle, used latch values from configuration registers (PWMDAT0 PWMDAT1) duty cycle registers (PWMCH0, PWMCH1, PWMCH2) into three-phase timing unit. addition, PWMEN register latched into output control unit rising edge PWMSYNC pulse. effect, this means that characteristics resulting duty cycles signals updated only once period start each cycle. result symmetrical patterns about midpoint switching period. double update mode, there additional PWMSYNC pulse produced midpoint each period. rising edge this PWMSYNC pulse again used latch values configuration registers, duty cycle registers, PWMEN register. result, possible alter both characteristics (switching frequency dead time) well output duty cycles midpoint each cycle. Consequently, also possible produce switching patterns that longer symmetrical about midpoint period (asymmetrical patterns). double update mode, necessary know whether operation point time either first half second half cycle. This information provided PWMSTA register, which cleared during operation first half each period (between rising edge original PWMSYNC pulse rising edge PWMSYNC pulse introduced double update mode). PWMSTA register during operation second half each period. This status allows user make determination particular half-cycle during implementation PWMSYNC interrupt service routine, required. previously discussed, controller ADuC7019/20/21/22/24/25/26/27 operate distinct modes, single update mode double update mode. operating mode controller determined state PWMCON register. this cleared, operates single update mode. Setting places double update mode. default operating mode single update mode.
Switching Dead Time (PWMDAT1 MMR)
second important parameter that must initial configuration block switching dead time. This short delay time introduced between turning signal (0H, example) turning complementary signal (0L). This short time delay introduced permit power switch turned this case, completely recover blocking capability before complementary switch turned This time delay prevents potentially destructive short-circuit condition from developing across link capacitor typical voltage source inverter. dead time controlled 10-bit, read/write PWMDAT1 register. There only dead-time register that controls dead time inserted into three pairs output signals. dead time, related value PWMDAT1 register PWMDAT1 tCORE Therefore, PWMDAT1 value 0x00A 10), introduces delay between turn-off signal (0H, example) turn-on complementary signal (0L). amount dead time therefore programmed increments 2tCORE 41.78 core clock).
Rev. Page
ADuC7019/20/21/22/24/25/26/27
advantage double update mode that lower harmonic voltages produced process faster control bandwidths possible. However, given switching frequency, PWMSYNC pulses occur twice rate double update mode. Because duty cycle values must computed each PWMSYNC interrupt service routine, there larger computational burden core double update mode. Both switching edges moved equal amount (PWMDAT1 tCORE) preserve symmetrical output
Other recent searches
ZHL-450-75 - ZHL-450-75 ZHL-450-75 Datasheet
SN74AHC541 - SN74AHC541 SN74AHC541 Datasheet
SN54AHC541 - SN54AHC541 SN54AHC541 Datasheet
PACDN006 - PACDN006 PACDN006 Datasheet
OPA2694 - OPA2694 OPA2694 Datasheet
MAZ3000 - MAZ3000 MAZ3000 Datasheet
KDZ16B - KDZ16B KDZ16B Datasheet
K7N323645M - K7N323645M K7N323645M Datasheet
K7N321845M - K7N321845M K7N321845M Datasheet
AOU412 - AOU412 AOU412 Datasheet
AOU412L - AOU412L AOU412L Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
