General Purpose, 16-bit Flash Microcontrollers 2005 Microchip Tec
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PIC24FJ128GA Family Data Sheet
General Purpose, 16-bit Flash Microcontrollers
2005 Microchip Technology Inc.
DS39747A
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance WiperLock trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2005, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2005 Microchip Technology Inc.
PIC24FJ128GA FAMILY
General Purpose, 16-bit Flash Microcontrollers
High-Performance CPU:
Modified Harvard Architecture MIPS operation internal oscillator: option Multiple divide options 17-bit 17-bit Single-Cycle Hardware Fractional/Integer Multiplier 32-bit 16-bit Hardware Divider 16-bit Working Register Array compiler Optimized Instruction Architecture: base instructions Flexible addressing modes Linear Program Memory Addressing Mbytes Linear Data Memory Addressing Kbytes Address Generation Units separate Read Write Addressing Data Memory
Analog Features:
10-bit, 16-channel Analog-to-Digital Converter (A/D): ksps conversion rate Conversion available during Sleep Idle Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:
3-wire/4-wire SPImodules, supporting Frame modes with 4-level FIFO Buffer I2Cmodules support Multi-Master/Slave mode 7-bit/10-bit Addressing UART modules: Supports RS-232, RS-485 Supports IrDA® with on-chip hardware endec Auto-Wake-up Start Auto-Baud Detect 4-level FIFO buffer Parallel Master Slave Port (PMP/PSP): Supports 8-bit 16-bit data Supports address lines Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Five 16-bit Timers/Counters with Programmable prescaler Five 16-bit Capture Inputs Five 16-bit Compare/PWM Outputs High-Current Sink/Source select pins: mA/18 Configurable Open-Drain Output Digital pins External Interrupt Sources
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V Flash Program Memory with 1,000 (typical) Erase/Write Cycle Endurance Self-Reprogrammable under Software Control Selectable Power Management modes: Sleep, Idle Alternate Clock modes Fail-Safe Clock Monitor operation: Detects clock failure switches on-chip, low-power oscillator On-Chip Regulator JTAG Boundary Scan Programming Support Power-on Reset (POR), Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip, Low-Power Oscillator reliable operation In-Circuit Serial Programming(ICSPTM) In-Circuit Emulation (ICE) pins
Compare/ Output
Comparators
Device
Pins
Program Memory (Bytes) 128K 128K 128K
PMP/PSP
Capture Input
UART
SRAM (Bytes)
Timers 16-bit
SPI
I2C
10-bit (ch)
PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ128GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ128GA008 PIC24FJ64GA010 PIC24FJ96GA010 PIC24FJ128GA010
2005 Microchip Technology Inc.
DS39747A-page
JTAG
PIC24FJ128GA FAMILY
Diagrams
64-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS//INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC24FJXXGA006 PIC24FJXXXGA006
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PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
2005 Microchip Technology Inc.
PIC24FJ128GA FAMILY
Diagrams (Continued)
80-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/INT1/RE8 TDO/INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24FJXXGA008 PIC24FJXXXGA008
2005 Microchip Technology Inc.
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS U2CTS/C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
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PIC24FJ128GA FAMILY
Diagrams (Continued))
100-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
PIC24FJXXGA010 PIC24FJXXXGA010
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15/TDO INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 RA4/TDI SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 CN21/U1RTS/BCLK1/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
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Table Contents
Device Overview CPU. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. Ports 10.0 Timer1 11.0 Timer2/3 Timer4/5 12.0 Input Capture. 13.0 Output Compare. 14.0 Serial Peripheral Interface (SPITM) 15.0 Inter-Integrated Circuit (I2CTM) 16.0 Universal Asynchronous Receiver Transmitter (UART) 17.0 Parallel Master Port. 18.0 Real-Time Clock Calendar 19.0 Programmable Cyclic Redundancy Check (CRC) Generator 20.0 10-bit High-Speed Converter. 21.0 Comparator Module. 22.0 Comparator Voltage Reference. 23.0 Special Features 24.0 Instruction Summary 25.0 Development Support. 26.0 Electrical Characteristics 27.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
2005 Microchip Technology Inc.
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device specific information following devices: PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 devices PIC24FJ128GA family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal low-power oscillator during operation, allowing user incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
This family introduces line Microchip devices: 16-bit RISC microcontroller family with broad peripheral feature enhanced computational performance. PIC24FJ128GA family offers migration option those high-performance applications which outgrowing their 8-bit platforms, don't require numerical processing power digital signal processor.
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.3
OSCILLATOR OPTIONS FEATURES
Central PIC24 devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24 core offers wide range enhancements, such 16-bit data 24-bit address paths, with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages such Operational performance MIPS
devices PIC24FJ128GA family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes, using crystals ceramic resonators. External Clock modes, offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier, available external oscillator modes oscillator, which allows clock speeds MHz. separate internal oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
1.1.4 EASY MIGRATION
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating next larger device. This true when moving between devices with same count, even jumping from 64-pin 80-pin 100-pin devices. PIC24 family pin-compatible with devices dsPIC33 family, shares some compatibility with pinout schema PIC18 dsPIC30. This extends ability applications grow from relatively simple powerful complex, still select Microchip device.
Details Individual Family Members
Devices PIC24FJ128GA family available 64-pin, 80-pin 100-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other ways: Flash program memory Kbytes PIC24FJ64GA devices, Kbytes PIC24FJ96GA devices Kbytes PIC24FJ128GA devices). Available pins ports pins ports 64-pin devices, pins ports 80-pin devices pins ports 100-pin devices).
Other Special Features
other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ128GA family devices, sorted function, shown Table 1-2. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
Communications: PIC24FJ128GA family incorporates range serial communication peripherals handle range application requirements. devices equipped with independent UARTs with built-in IrDA encoder/decoders. There also independent modules, independent modules that support both Master Slave modes operation. Parallel Master/Enhanced Parallel Slave Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit 16-bit data transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application. 10-bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds.
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TABLE 1-1: DEVICE FEATURES PIC24FJ128GA FAMILY
PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 128K 44,032 PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ64GA010 PIC24FJ96GA010 32,768 100-pin TQFP
Features
Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources (Soft Vectors/NMI Traps) Ports Total Pins Timers: Total number (16-bit) 32-bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: Enhanced UART SPI(3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan 10-bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) Instruction Packages Ports 22,016 32,768 128K 44,032
32,768 8192 (39/4) Ports Ports 128K 44,032 22,016 22,016
POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, Repeat Hardware Traps, (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 64-pin TQFP 80-pin TQFP
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
FIGURE 1-1: PIC24FJ128GA FAMILY GENERAL BLOCK DIAGRAM
Interrupt Controller
Data
PORTA(1) Data Latch Program Counter Repeat Stack Control Control Logic Logic Data PORTB Address Latch PORTC(1) RC1:RC4, RC12:RC15 RB0:RB15 RA0:RA7, RA9:RA10, RA14:15
Table Data Access Control Block
Address Latch Program Memory Data Latch
Read Write
Address
Inst Latch Literal Data
PORTD(1) RD0:RD15
Inst Register Instruction Decode Control Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) 16-bit
PORTE(1) RE0:RE9
Divide Support 17x17 Multiplier
Array PORTF(1) RF0:RF8, RF12:RF13
OSC2/CLKO OSC1/CLKI
Timing Generation FRC/LPRC Oscillators Precision Band Reference
PORTG(1) RG0:RG9, RG12:RG15
ENVREG Voltage Regulator
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3
Timer4/5
RTCC
10-bit
Comparators
PMP/PSP
IC1-5
PWM/ OC1-5
CN1-22(1)
SPI1/2
I2C1/2
UART1/2
Note
pins features implemented device pinout configurations. Table port descriptions. functionality provided when on-board voltage regulator enabled.
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TABLE 1-2:
Function 64-pin AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS
Number Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Positive Supply Analog Modules. Ground Reference Analog Modules. UART1 IrDA® Baud Clock. UART2 IrDA® Baud Clock. Comparator Negative Input. Comparator Positive Input. Comparator Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. Analog Inputs. Description
input buffer Analog level input/output
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
TABLE 1-2:
Function 64-pin CN18 CN19 CN20 CN21 CVREF EMUC1 EMUD1 EMUC2 EMUD2 ENVREG INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Output Compare Fault Input. Output Compare Fault Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data. In-Circuit Debugger ICSPProgramming Clock. In-Circuit Debugger ICSP Programming Data. Master Clear (Device Reset) Input. This line brought cause Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. Enable On-Chip Voltage Regulator. Input Capture Inputs. Description Interrupt-on-Change Inputs.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2:
Function 64-pin PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMCS2 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select Strobe/Address Parallel Master Port Chip Select Strobe/Address Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes). Description Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
TABLE 1-2:
Function 64-pin RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description
input buffer Analog level input/output
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TABLE 1-2:
Function 64-pin RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13 Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description
input buffer Analog level input/output
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
TABLE 1-2:
Function 64-pin RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer
Description PORTG Digital I/O.
Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2:
Function 64-pin U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCAP VDDCORE VREFVREF+ Legend: 80-pin 100-pin
PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Input Buffer Description UART1 Clear Send Input. UART1 Request Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear Send Input. UART2 Request Send Output. UART Receive Input. UART2 Transmit Output. Positive Supply Peripheral Digital Logic pins. External Filter Capacitor Connection (regulator enabled). Positive Supply Microcontroller Core Logic (regulator disabled). Comparator Reference Voltage (Low) Input. Comparator Reference Voltage (High) Input. Ground Reference Logic pins.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
2005 Microchip Technology Inc.
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NOTES:
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2005 Microchip Technology Inc.
PIC24FJ128GA FAMILY
PIC24 16-bit (data) modified Harvard architecture with enhanced instruction set, 23-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24 devices have sixteen 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported either directly through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements. most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three-parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports signed, unsigned mixed mode 16-bit 16-bit 8-bit 8-bit integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism, selection iterative divide instructions, support 32-bit 16-bit) divided 16-bit integer signed unsigned division. divide operations require cycles complete interruptible cycle boundary. PIC24 vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 2-1.
Programmer's Model
programmer's model PIC24 shown Figure 2-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 2-1. registers associated with programmer's model memory mapped.
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FIGURE 2-1:
Table Data Access Control Block Interrupt Controller Data Data Latch Program Counter Loop Stack Control Control Logic Logic Data Address Latch
PIC24 CORE BLOCK DIAGRAM
RAGU WAGU
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-bit
Peripheral Modules
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TABLE 2-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working register array 23-bit Program Counter STATUS register Stack Pointer Limit Value register Table Memory Page Address register Program Space Visibility Page Address register REPEAT Loop Count register Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
Divider Working Registers
(WREG)
Multiplier Registers
Frame Pointer Stack Pointer Working/Address Registers
SPLIM TBLPAG PSVPAG RCOUNT
Stack Pointer Limit
Program Counter
Data Table Page Address Program Space Visibility Page Address REPEAT Loop Counter STATUS Register (SR)
Core Control Register (CORCON)
IPL3
Registers bits shadowed PUSH.S POP.S instructions.
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Control Registers
STATUS REGISTER
R/W-0 Lower Byte: R/W-0(1) IPL2(2) 15-9 Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte sized data) low-order (for word sized data) result occurred carry-out from low-order result occurred IPL2:IPL0: Interrupt Priority Level Status bits(2) interrupt priority level (15). User interrupts disabled. interrupt priority level (14) Interrupt Priority Level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level Note Status bits read-only when NSTDIS (INTCON1<15>) bits concatenated with IPL3 (CORCON<3>) form interrupt priority level. value parentheses indicates when IPL3 REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant result occurred carry-out from Most Significant result occurred Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0(1) IPL1
REGISTER 2-1:
Upper Byte:
R/W-0(1) IPL0(2)
R/W-0
R/W-0
R/W-0
R/W-0
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REGISTER 2-2:
Upper Byte:
CORCON: CORE CONTROL REGISTER
Lower Byte: 15-4
R/C-0 IPL3
R/W-0
Unimplemented: Read IPL3: Interrupt Priority Level Status interrupt priority level greater than interrupt priority level less Note: User interrupts disabled when IPL3 PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read Legend: Readable Value Writable Unimplemented bit, read cleared unknown
Arithmetic Logic Unit (ALU)
PIC24 bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location.
PIC24 incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division.
2.3.1
MULTIPLIER
contains high-speed 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
2005 Microchip Technology Inc.
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2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT
divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operation with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide PIC24 supports both single-bit single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support register direct addressing both operand source result destination. full summary instructions that shift operation provided below Table 2-2.
quotient divide instructions ends remainder 16-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m+1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
TABLE 2-2:
Instruction ASRF ASRW ASRK LSRF LSRW LSRK
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register bit. Arithmetic shift right content register bit. Arithmetic shift right source register bits, value held register referenced within instruction. Arithmetic shift right source register bits. Shift value literal. Shift left source register bit. Shift left content file register bit. Shift left source register bits, value held register referenced instruction. Shift left source register bits. Shift value literal. Logical shift right source register bit. Logical shift right content register bit. Logical shift right source register bits, value held register referenced within instruction. Logical shift right source register bits. Shift value literal.
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MEMORY ORGANIZATION
Harvard architecture devices, PIC24 microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24FJ128GA family devices shown Figure 3-1.
Program Address Space
program address memory space PIC24FJ128GA family devices instructions. space addressable 24-bit value derived from
FIGURE 3-1:
PROGRAM SPACE MEMORY PIC24FJ128GA FAMILY DEVICES
PIC24FJ64GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words Flash Config Words Flash Config Words Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's)
PIC24FJ96GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ128GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Memory Space
User Flash Program Memory (32K instructions)
User Flash Program Memory (44K instructions)
00ABFEh 00AC00h 00FFFEh 010000h 0157FEh 015800h
7FFFFEh 800000h
Reserved
Reserved
Reserved
Configuration Memory Space
Device Configuration Registers
Device Configuration Registers
Device Configuration Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
FEFFFEh FF0000h FFFFFEh
Note:
Memory areas shown scale.
2005 Microchip Technology Inc.
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3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
program memory space organized word addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 3-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ128GA family devices, words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ128GA family shown Table 3-1. Their location memory shown with other memory vectors Figure 3-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 23.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS
PIC24 devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h, with actual address start code 000002h. PIC24 devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
TABLE 3-1:
FLASH CONFIGURATION WORDS PIC24FJ128GA FAMILY DEVICES
Program Memory words) Configuration Word Addresses 00ABFCh: 00ABFEh 00FFFCh: 00FFFEh 0157FCh: 0157FEh
Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA
FIGURE 3-2:
Address
PROGRAM MEMORY ORGANIZATION
most significant word least significant word 000000h 000002h 000004h 000006h Instruction Width Address (lsw Address)
000001h 000003h 000005h 000007h
00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0')
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Data Address Space
PIC24 core separate 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 3-3. Effective Addresses (EAs) data memory space bits wide, point bytes within data space. This gives data space address range Kbytes, words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ128GA family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
3.2.1
DATA SPACE WIDTH
data memory space organized byte addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes each word have even addresses, while Most Significant Bytes have addresses.
FIGURE 3-3:
DATA SPACE MEMORY PIC24FJ128GA FAMILY DEVICES
Address 0001h 07FFh 0801h Address 0000h 07FEh 0800h Space Near Data Space
Space
Implemented Data 1FFFh 2001h 27FFh 2801h
Data 1FFEh 2000h 07FEh 0800h Unimplemented Read 7FFFh 8001h 7FFFh 8000h
Program Space Visibility Area
FFFFh
FFFEh
Note:
Data memory areas shown scale.
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3.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PICmicro® devices improve data space memory usage efficiency, PIC24 instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing zero-extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
3.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space addressable indirectly. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
3.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24 core peripheral modules controlling operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 3-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 3-30.
TABLE 3-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers I2CA/D RTC/Comp UART System Capture SPI- NVM/PMD xx40 xx60 Compare xx80 xxA0 Interrupts xxC0 xxE0
000h 100h 200h 300h 400h 500h 600h 700h
Legend: implemented SFRs this block
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TABLE 3-3:
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Program Counter, Word Repeat Loop Counter IPL2 IPL1 Disable Interrupts Counter IPL0 IPL3 Program Counter, High Byte Table Page Address Pointer Program Memory Visibility Page Address Pointer
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
File Name
Addr
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
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WREG5
000A
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
002E
0030
TBLPAG
0032
PSVPAG
0034
RCOUNT
0036
0042
CORCON
0044
DISICNT
0052
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ128GA FAMILY
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TABLE 3-4:
AD1IF INT2IF PMPIF AD1IE INT2IE PMPIE T1IP1 T2IP1 U1RXIP1 CNIP1 T4IP1 U2TXIP1 IC5IP1 CRCIP1 CRCIP0 U2ERIP2 U2ERIP1 RTCIP2 RTCIP1 INT4IP2 INT4IP1 MI2C2P2 MI2C2P1 MI2C2P0 INT4IP0 RTCIP0 U2ERIP0 IC5IP0 IC4IP2 IC4IP1 IC4IP0 U2TXIP0 U2RXIP2 U2RXIP1 U2RXIP0 T4IP0 OC4IP2 OC4IP1 OC4IP0 OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 INT3IP2 U1ERIP2 CNIP0 CMIP2 CMIP1 CMIP0 MI2C1P2 AD1IP2 AD1IP1 MI2C1P1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 INT3IP1 U1ERIP1 U1RXIP0 SPI1IP2 SPI1IP1 SPI1IP0 SPF1IP2 SPF1IP1 T2IP0 OC2IP2 OC2IP1 OC2IP0 IC2IP2 IC2IP1 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 INT3IP0 U1ERIP0 T1IP0 OC1IP2 OC1IP1 OC1IP0 IC1IP2 IC1IP1 IC1IP0 INT4IE INT3IE CRCIE OC5IE IC5IE IC4IE IC3IE T5IE T4IE OC4IE OC3IE INT1IE CNIE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE T1IE CRCIF U2ERIF OC1IE CMIE MI2C2IE U2ERIE INT0IP2 T3IP2 U1TXIP2 SI2C1P2 INT1IP2 T5IP2 SPF2IP2 INT4IF INT3IF MI2C2IF OC5IF IC5IF IC4IF IC3IF T5IF T4IF OC4IF OC3IF INT1IF CNIF CMIF MI2C1IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 T3IP1 U1TXIP1 SI2C1P1 INT1IP1 T5IP1 SPF2IP1 U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT4EP INT3EP INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 SI2C1P0 INT1IP0 T5IP0 SPF2IP0 Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 4440 0040 0040 0440 0440 0400 4440
INTERRUPT CONTROLLER REGISTER
File Name
Addr
INTCON1
0080
NSTDIS
INTCON2
0082
ALTIVT
DISI
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IFS0
0084
IFS1
0086
U2TXIF
U2RXIF
IFS2
0088
IFS3
008A
RTCIF
IFS4
008C
IEC0
0094
IEC1
0096
U2TXIE
U2RXIE
IEC2
0098
IEC3
009A
RTCIE
IEC4
009C
IPC0
00A4
T1IP2
IPC1
00A6
T2IP2
IPC2
00A8
U1RXIP2
IPC3
00AA
PIC24FJ128GA FAMILY
IPC4
00AC
CNIP2
IPC5
00AE
IPC6
00B0
T4IP2
IPC7
00B2
U2TXIP2
IPC8
00B4
IPC9
00B6
IC5IP2
IPC10
00B8
IPC11
00BA
IPC12
00BC
IPC13
00BE
IPC15
00C2
IPC16
00C4
CRCIP2
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Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-5:
CN13IE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN21IE CN20IE CN19IE CN18IE CN17IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE CN16IE CN0PUE
REGISTER
Resets 0000 0000 0000 0000
File Name
Addr
CNEN1
0060
CN15IE
CN14IE
CNEN2
0062
CNPU1
0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
CNPU2
006A
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2005 Microchip Technology Inc.
Timer1 Register Period Register TSIDL Timer2 Register Timer3 Holding Register (For 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TSIDL Timer4 Register Timer5 Holding Register (For 32-bit operations only) Timer5 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 TGATE TCKPS1 TCKPS0 TSYNC
TABLE 3-6:
TIMER REGISTER
Resets xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000
File Name
Addr
TMR1
0100
0102
T1CON
0104
TMR2
0106
TMR3HLD
0108
TMR3
010A
010C
010E
T2CON
0110
T3CON
0112
TMR4
0114
TMR5HLD
0116
TMR5
0118
011A
011C
T4CON
011E
T5CON
0120
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ128GA FAMILY
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TABLE 3-7:
Input Capture Register Input Capture Register Input Capture Register Input Capture Register Input Capture Register ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Resets xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000
INPUT CAPTURE REGISTER
File Name
Addr
IC1BUF
0140
IC1CON
0142
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Output Compare Secondary Register Output Compare Register Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM2 OCM1 OCM0 OCSIDL OCFLT OCTSEL OCM2 OCM1 OCM0 Resets xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx Output Compare Register OCSIDL OCFLT OCTSEL OCM2 OCM1 OCM0 xxxx 0000 Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
OUTPUT COMPARE REGISTER
File Name
Addr
OC1RS
0180
PIC24FJ128GA FAMILY
OC1R
0182
OC1CON
0184
OC2RS
0186
OC2R
0188
OC2CON
018A
OC3RS
018C
OC3R
018E
OC3CON
0190
OC4RS
0192
OC4R
0194
OC4CON
0196
OC5RS
0198
OC5R
019A
OC5CON
019C
2005 Microchip Technology Inc.
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-9:
Address Mask Address Register GCSTAT ADD10 IWCOL I2COV I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN RSEN Baud Rate Generator Transmit Register Receive Register Resets 0000 00FF 0000 1000 0000 0000 0000
I2C1 REGISTER
File Name
Addr
I2C1RCV
0200
I2C1TRN
0202
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I2CSIDL GCSTAT ADD10 IWCOL I2CPOV SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT Resets 0000 00FF 0000 ACKEN Address Register Address Mask RCEN RSEN 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator
I2C1BRG
0204
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT
TRSTAT
I2C1ADD
020A
I2C1MSK
020C
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-10:
I2C2 REGISTER
File Name
Addr
I2C2RCV
0210
I2C2TRN
0212
I2C2BRG
0214
I2C2CON
0216
I2CEN
PIC24FJ128GA FAMILY
I2C2STAT
0218
ACKSTAT
TRSTAT
I2C2ADD
021A
I2C2MSK
021C
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2005 Microchip Technology Inc.
TABLE 3-11:
USIDL UTXISEL0 Baud Rate Generator Prescaler Receive Register Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL Resets 0000 0110 xxxx 0000 0000
UART1 REGISTER
File Name
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
UTXINV
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USIDL UTXISEL0 Baud Rate Generator Prescaler Transmit Register Receive Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000 SPISIDL SPIFPOL DISSCK DISSDO MODE16 SSEN SPIBEC2 SPIBEC1 SPIBEC0 SPIROV MSTEN SPRE2 SPRE1 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000 SPI1 Transmit Receive Buffer SPISIDL SPIFPOL DISSCK DISSDO MODE16 SSEN SPIROV SPI2 Transmit Receive Buffer MSTEN SPRE2 SPRE1 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000 SPIBEC2 SPIBEC1 SPIBEC0
U1TXREG
0224
U1RXREG
0226
U1BRG
0228
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-12:
UART2 REGISTER
File Name
Addr
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1
UTXINV
U2TXREG
0234
U2RXREG
0236
U2BRG
0238
PIC24FJ128GA FAMILY
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-13:
SPI1 REGISTER
File Name
Addr
SPI1STAT
0240
SPIEN
SPI1CON1
0242
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-14:
SPI2 REGISTER
File Name
Addr
SPI2STAT
0260
SPIEN
SPI2CON1
0262
SPI2CON2
0264
FRMEN
SPIFSD
SPI2BUF
0268
2005 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-15:
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer VCFG0 PCFG13 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 CSSL7 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 OFFCAL CSCNA BUFS ADCS6 PCFG6 CSSL6 ADSIDL FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
File Name
Addr
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
2005 Microchip Technology Inc.
RA10
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
AD1CON1
0320
ADON
AD1CON2
0322
VCFG2
VCFG1
AD1CON3
0324
ADRC
AD1CHS
0328
CH0NB1
CH0NB0
TRISA10(1) TRISA9(1)
AD1PCFG
032C
PCFG15
PCFG14
AD1CSSL
0330
CSSL15
CSSL14
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-16:
PORTA REGISTER
LATA9(1) ODA9(1) TRISA7(2) TRISA6(2)
File Name
Addr
TRISA5(2) LATA7(2) ODA7(2)
TRISA4(2) LATA6(2) ODA6(2)
TRISA3(2) TRISA2(2) LATA5(2) ODA5(2)
TRISA1(2) LATA4(2) ODA4(2)
TRISA0(2) LATA3(2) ODA3(2)
Resets C6FF LATA2(2) ODA2(2)
TRISA
02C0
TRISA15(1) TRISA14(1)
PORTA
02C2
RA15
RA14
RA0(2) LATA1(2) ODA1(2) LATA0(2) ODA0(2)
xxxx xxxx 0000
LATA
02C4
LATA15(1)
LATA14(1)
LATA10(1) ODA10(1)
ODCA
06C0
ODA15(1)
ODA14(1)
PIC24FJ128GA FAMILY
DS39747A-page
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only. Implemented 100-pin devices only
TABLE 3-17:
TRISB13 RB13 LATB13 ODB13 ODB12 ODB11 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 RB12 RB11 RB10 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 LATB0 ODB0
PORTB REGISTER
Resets FFFF xxxx xxxx 0000
File Name
Addr
TRISB
02C6
TRISB15
TRISB14
PORTB
02C8
RB15
RB14
LATB
02CA
LATB15
LATB14
ODCB
06C6
ODB15
ODB14
2005 Microchip Technology Inc.
LATC4(2) ODC4(2) RC4(2) TRISC4(2) TRISC3(1) RC3(1) LATC3(1) ODC3(1) TRISC2(2) RC2(2) LATC2(2) ODC2(2) TRISC1(1) RC1(1) LATC1(1) ODC1(1) F01E xxxx xxxx 0000 RC13 LATC13 ODC13 ODC12 LATC12 RC12 TRISD11 RD11 LATD11 ODD11 ODD10 ODD9 LATD10 LATD9 RD10 LATD8 ODD8 TRISD10 TRISD9 TRISD8 TRISD7 LATD7 ODD7 TRISD6 LATD6 ODD6 TRISD5 LATD5 ODD5 TRISD4 LATD4 ODD4 TRISD3 LATD3 ODD3 TRISD2 LATD2 ODD2 TRISD1 LATD1 ODD1 TRISD0 LATD0 ODD0 FFFF xxxx xxxx 0000 RD13(1) LATD13(1) ODD13(1) ODD12(1) LATD12(1) RD12(1)
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices.
TABLE 3-18:
PORTC REGISTER
Resets
File Name
Addr
TRISC
02CC
TRISC15 TRISC14 TRISC13 TRISC12
PORTC
02CE
RC15
RC14
LATTC
02D0
LATC15
LATC14
ODCC
06CC
ODC15
ODC14
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only. Implemented 100-pin devices only
TABLE 3-19:
PORTD REGISTER
Resets
File Name
Addr
TRISD
02D2
TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1)
PORTD
02D4
RD15(1)
RD14(1)
LATD
02D6
LATD15(1)
LATD14(1)
ODCD
06D2
ODD15(1)
ODD14(1)
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only.
PIC24FJ128GA FAMILY
DS39747A-page
TABLE 3-20:
ODE9(1) ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE8(1) ODE1 LATE9(1) LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE8(1) RE9(1) RE8(1) TRISE9(1) TRISE8(1) TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 LATE0 ODE0
PORTE REGISTER
Resets 03FF xxxx xxxx 0000
File Name
Addr
TRISE
02D8
PORTE
02DA
LATE
02DC
ODCE
06D8
2005 Microchip Technology Inc.
TRISF13(1) TRISF12(1) ODF8(2) ODF6 ODF5 ODF7(2) LATF8(2) LATF6 LATF5 LATF7(2) RF8(2) LATF4 ODF4 RF7(2) TRISF6 TRISF5 TRISF4 RG13 LATF13(1) ODF13(1) ODF12(1) LATF12(1)
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only.
TABLE 3-21:
TRISF8(2) TRISF7(2) TRISF3 LATF3 ODF3
PORTF REGISTER
TRISF2 LATF2 ODF2 TRISF1 LATF1 ODF1 TRISF0 LATF0 ODF0 Resets 31FF xxxx xxxx 0000
File Name
Addr
TRISF RG12
02DE
PORTF
02E0
LATF
02E2
ODCF
06DE
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 100-pin devices only. Implemented 80-pin 100-pin devices only.
TABLE 3-22:
ODG9 LATG9 LATG8 ODG8 TRISG9 TRISG8 TRISG7 LATG7 ODG7
PORTG REGISTER
TRISG6 LATG6 ODG6 TRISG3 LATG3 ODG3 TRISG2 LATG2 ODG2 TRISG1(2) TRISG0(2) RG1(2) LATG1(2) ODG1(2) RG0(2) LATG0(2) ODG0(2) Resets F3CF xxxx xxxx 0000
RG13(1) LATG13(1) ODG13(1) ODG12(1) LATG12(1) RG12(1)
File Name
Addr
TRISG
02E4
TRISG15(1) TRISG14(1) TRISG13(1) TRISG12(1
PORTG
02E6
RG15(1)
RG14(1)
LATG
02E8
LATG15(1)
LATG14(1)
ODCG
06E4
ODG15(1)
ODG14(1)
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 100-pin devices only Implemented 80-pin 100-pin devices only.
TABLE 3-23:
CONFIGURATION
RTSECSEL PMPTTL Resets 0000
File Name
Addr
PADCFG1
02FC
PIC24FJ128GA FAMILY
DS39747A-page
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices.
TABLE 3-24:
PSIDL IRQM0 Parallel Port Destination Address<13:0> (Master modes) Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers PTEN13 IB3F IB2F IB1F IB0F OBUF OB3E PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 CS2P CS1P WRSP RDSP Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000
PARALLEL MASTER/SLAVE PORT REGISTER
File Name
Addr
PMCON
0600
PMPEN
PMMODE
0602
BUSY
IRQM1
DS39747A-page
Alarm Value Register Window based APTR<1:0> AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Resets xxxx 0000 xxxx CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 RTCC Value Register Window based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT CVREN C1OUT CVROE C2INV CVRR C1INV CVRSS C2NEG CVR3 C2POS CVR2 C1NEG CVR1 C1POS CVR0 Resets 0000 0000
PMADDR(1)
PMDOUT1(1)
0604
PMDOUT2
0606
PMDIN1
0608
PMPDIN2
060A
PMPEN
060C
PTEN15
PTEN14
PMSTAT
060E
IBOV
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. PMADDR PMDOUT1 share same physical register. register functions PMDOUT1 only Slave modes, PMADDR only Master modes.
TABLE 3-25:
REAL-TIME CLOCK CALENDAR REGISTER
File Name
Addr
ALRMVAL
0620
PIC24FJ128GA FAMILY
ALCFGRPT
0622
ALRMEN
CHIME
RTCVAL
0624
RCFGCAL(1)
0626
RTCEN
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCFGCAL register Reset value dependent type Reset.
TABLE 3-26:
DUAL COMPARATOR REGISTER
File Name
Addr
CMCON
0630
CMIDL
CVRCON
0632
2005 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-27:
CSIDL Polynomial Register Data Input Register Result Register VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCGO PLEN3 PLEN2 PLEN1 PLEN0
REGISTER
Resets 0000 0000 0000 0000
File Name
Addr
CRCCON
0640
CRCXOR
0642
CRCDAT
0644
CRCWDAT
0646
2005 Microchip Technology Inc.
COSC1 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 COSC0 NOSC2 NOSC1 NOSC0 CLKLOCK LOCK EXTR SWDTEN WDTO SLEEP IDLE SOSCEN TUN<3:0> OSWEN WRERR ERASE NVMOP3 NVMOP2 NVMOP1 NVMOP0 NVMKEY<7:0> T3MD IC5MD IC4MD T2MD T1MD IC3MD CMPMD IC2MD RTCCMD IC1MD PMPMD I2C1MD CRCPMD U2MD U1MD SPI2MD OC5MD SPI1MD OC4MD OC3MD OC2MD I2C2MD ADCMD OC1MD
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-28:
SYSTEM REGISTER
Resets xxxx(1) xxxx(2) 0300 0000
File Name
Addr
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
COSC2
CLKDIV
0744
DOZE2
OSCTUN
0748
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCON register Reset values dependent type Reset. OSCCON register Reset values dependent FOSC Configuration bits type Reset.
TABLE 3-29:
REGISTER
Resets 0000(1) 0000
File Name
Addr
NVMCON
0760
WREN
NVMKEY
0766
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 3-30:
REGISTER
Resets 0000 0000 0000
File Name
Addr
PMD1
0770
T5MD
T4MD
PMD2
0772
PMD3
0774
PIC24FJ128GA FAMILY
DS39747A-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ128GA FAMILY
3.2.5 SOFTWARE STACK
addition working register, register PIC24 devices also used software Stack Pointer. pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 3-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24 architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24 architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. only access least significant word program word.
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TABPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TABPAG used determine operation occurs user memory (TABPAG<7> configuration memory (TABPAG<7> remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 3-31 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 3-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
DS39747A-page
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TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2) TBLPAG bits bits bits
Select Program Space (Remapping) Visibility(1) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed `0', order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
2005 Microchip Technology Inc.
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3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, "phantom byte", will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper "phantom" byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space, without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit word wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TABPAG). TABPAG covers entire program memory space device, including user configuration spaces. When TABPAG<7> Table Page located user memory space. When TABPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space only then, implemented areas such Device Table write operations allowed.
FIGURE 3-6:
TABPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h
00000000 00000000
020000h 030000h
00000000 00000000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W
800000h
address table operation determined data within page defined TABPAG register. Only read operations shown; write operations also valid user memory area.
DS39747A-page
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3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 3-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
2005 Microchip Technology Inc.
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PIC24FJ128GA FAMILY
NOTES:
DS39747A-page
2005 Microchip Technology Inc.
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Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24FJ devices. intended comprehensive reference source.
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time, erase program memory blocks instructions (1536 bytes) time.
PIC24FJ128GA family devices contains internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed ways: In-Circuit Serial Programming (ICSP) Run-Time Self-Programming (RTSP)
Table Instructions Flash Programming
ICSP allows PIC24FJ128GA family device serially programmed while application circuit. This simply done with lines Programming Clock Programming Data (which named PGCx PGDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using bits<7:0> TBLPAG register Effective Address (EA) from register specified table instruction, shown Figure 4-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
FIGURE 4-1:
ADDRESSING TABLE REGISTERS
bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG bits bits
User/Configuration Space Select
24-bit
Byte Select
2005 Microchip Technology Inc.
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RTSP Operation Control Registers
PIC24 Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time, program time. 8-row erase blocks single-row write blocks edgealigned, from beginning program memory, boundaries 1536 bytes bytes, respectively. program memory implements holding buffers that contain instructions programming data. Prior actual programming operation, write data must loaded into buffers sequential order. instructions words loaded must always from group boundaries. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. total TBLWTL TBLWTH instructions required load instructions. table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each row. There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 4-1) controls which blocks erased, which memory type programmed start programming cycle. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
complete programming sequence necessary programming erasing internal Flash RTSP mode. programming operation nominally duration processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation, automatically cleared when operation finished.
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REGISTER 4-1: NVMCOM: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR Upper Byte: R/SO-0(1) R/W-0(1) WREN
Lower Byte: R/W-0(1) ERASE
R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) NVMOP3 NVMOP2 NVMOP1 NVMOP0(2)
Write Control Initiates Flash memory program erase operation operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP3:NVMOP0 next command Perform program operation specified NVMOP3:NVMOP0 next command Unimplemented: Read NVMOP3:NVMOP0: Operation Select bits(2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0010 Memory erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE Note These bits only reset POR. other combinations NVMOP3:NVMOP0 unimplemented. Legend: Readable Value Reset Writable Settable-Only cleared Unimplemented unknown
12-7
2005 Microchip Technology Inc.
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4.4.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program program Flash memory time. this, necessary erase 8-row erase block containing desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 4-1): NVMOP bits (NVMCOM<3:0>) `0010' configure block erase. ERASE (NVMCOM<6>) WREN (NVMCOM<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCOM<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 4-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 4-3.
EXAMPLE 4-1:
ERASING PROGRAM MEMORY BLOCK
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 4-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++] 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++]
EXAMPLE 4-3:
DISI BSET
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
#0x55, NVMKEY #0xAA, NVMKEY NVMCON,
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RESETS
Note: Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset MCLR: Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized Register Reset Refer specific peripheral section this manual register Reset states.
types device Reset will corresponding status RCON register indicate type Reset (see Register 5-1). will clear bits except bits (RCON<1:0>), which set. user clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software will cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
simplified block diagram Reset module shown Figure 5-1. active source Reset will make SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR Module Sleep Idle SYSRST
Rise Detect Brown-out Reset
Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized Register
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REGISTER 5-1: RCON: RESET CONTROL REGISTER
Upper Byte: R/W-0 R/W-0 TRAPR IOPUWR
Lower Byte: R/W-0 R/W-0 EXTR
R/W-0 SWDTEN
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1
R/W-1
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode, uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable enabled disabled Note: FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
13-8
WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake From Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up From Idle Flag Device Idle mode Device Idle mode BOR: Brown-out Reset Flag Brown-out Reset occurred. Note that also after Power-on Reset. Brown-out Reset occurred POR: Power-on Reset Flag Power-up Reset occurred Power-up Reset occurred Note: Reset status bits cleared software. Setting these bits software does cause device Reset.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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TABLE 5-1: RESET FLAG OPERATION
Setting Event Trap conflict event Illegal opcode uninitialized register access MCLR Reset RESET instruction time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, PWRSAV instruction, Clearing Event Flag TRAPR (RCON<15>) IOPR (RCON<14>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) Note:
Reset flag bits cleared user software.
Clock Source Selection Reset
Device Reset Times
clock switching enabled, system clock source device Reset chosen shown Table 5-2. clock switching disabled, system clock source always selected according oscillator Configuration bits. Refer "Oscillator Configuration" further details.
Reset times various types device Reset summarized Table 5-3. Note that system Reset signal, SYSRST, released after PWRT delay times expire. time that device actually begins execute code will also depend system oscillator delays, which include Oscillator Start-up Timer (OST) lock time. lock times occur parallel with applicable SYSRST delay times. FSCM delay determines time which FSCM begins monitor system clock source after SYSRST signal released.
TABLE 5-2:
OSCILLATOR SELECTION TYPE RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant Oscillator Configuration Bits (FNOSC2:FNOSC0) COSC Control bits (OSCCON<14:12>)
Reset Type MCLR WDTR
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TABLE 5-3:
Reset Type
RESET DELAY TIMES VARIOUS DEVICE RESETS
Clock Source SYSRST Delay System Clock Delay TLOCK TOST TLOCK TOST TOST TLOCK FSCM Delay TFSCM TFSCM TFSCM TFSCM TFSCM TFSCM Notes
FRC, FRCDIV, LPRC TPOR TSTARTUP TRST ECPLL, FRCPLL SOSC XTPLL, HSPLL TPOR TSTARTUP TRST TPOR TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TRST TRST TRST TRST TRST TRST
TPOR TSTARTUP TRST TOST TLOCK
FRC, FRCDIV, LPRC ECPLL, FRCPLL SOSC XTPLL, HSPLL
MCLR Software Illegal Opcode Uninitialized Trap Conflict Note
Clock Clock clock Clock Clock Clock
TPOR Power-on Reset delay nominal). TSTARTUP TVREG nominal) on-chip regulator enabled TPWRT nominal) on-chip regulator disabled. TRST Internal state Reset time nominal). TOST Oscillator Start-up Timer. 10-bit counter counts 1024 oscillator periods before releasing oscillator clock system. TLOCK lock time nominal). TFSCM Fail-Safe Clock Monitor delay (100 nominal).
5.2.1
LONG OSCILLATOR START-UP TIMES
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) DEVICE RESETS
oscillator start-up circuitry associated delay timers linked device Reset delays that occur power-up. Some crystal circuits (especially low-frequency crystals) will have relatively long start-up time. Therefore, more following conditions possible after SYSRST released: oscillator circuit begun oscillate. Oscillator Start-up Timer expired crystal oscillator used). achieved LOCK used). device will begin execute code until valid clock source been released system. Therefore, oscillator start-up delays must considered when Reset delay time must known.
FSCM enabled, will begin monitor system clock source when SYSRST released. valid clock source available this time, device will automatically switch oscillator user switch desired crystal oscillator Trap Service Routine.
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5.2.2.1 FSCM Delay Crystal Clock Sources
Special Function Register Reset States
When system clock source provided crystal oscillator and/or PLL, small delay, TFSCM, will automatically inserted after PWRT delay times. FSCM will begin monitor system clock source until this delay expires. FSCM delay time nominally provides additional time oscillator and/or stabilize. most cases, FSCM delay will prevent oscillator failure trap device Reset when PWRT disabled.
Most Special Function Registers (SFRs) associated with PIC24 peripherals reset particular value device Reset. SFRs grouped their peripheral function their Reset values specified each section this manual. Reset value each does depend type Reset, with exception four registers. Reset value Reset Control register, RCON, will depend type device Reset. Reset value Oscillator Control register, OSCCON, will depend type Reset programmed values oscillator Configuration bits FOSC Device Configuration register (see Table 5-2). RCFGCAL EECON1 registers only affected POR.
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INTERRUPT CONTROLLER
6.1.1
PIC24 interrupt controller reduces numerous peripheral interrupt request signals single interrupt request signal PIC24 CPU. following features: processor exceptions software traps user-selectable priority levels Interrupt Vector Table (IVT) with vectors unique vector each interrupt exception source Fixed priority within specified user priority level Alternate Interrupt Vector Table (AIVT) debug support Fixed interrupt entry return latencies
ALTERNATE INTERRUPT VECTOR TABLE
Alternate Interrupt Vector Table (AIVT) located after shown Figure 6-1. Access AIVT provided ALTIVT control (INTCON2<15>). ALTIVT set, interrupt exception processes will alternate vectors instead default vectors. alternate vectors organized same manner default vectors. AIVT supports emulation debugging efforts providing means switch between application support environment without requiring interrupt vectors reprogrammed. This feature also enables switching between applications evaluation different software algorithms time. AIVT needed, AIVT should programmed with same addresses used IVT.
Interrupt Vector Table
Interrupt Vector Table (IVT) shown Figure 6-1. resides program memory, starting location 000004h. contains vectors, consisting non-maskable trap vectors, plus sources interrupt. general, each interrupt source vector. Each interrupt vector contains 24-bit wide address. value programmed into each interrupt vector location starting address associated Interrupt Service Routine (ISR). Interrupt vectors prioritized terms their natural priority; this linked their position vector table. other things being equal, lower addresses have higher natural priority. example, interrupt associated with vector will take priority over interrupts other vector address. PIC24FJ128GA family devices implement nonmaskable traps unique interrupts. These summarized Table Table 6-2.
Reset Sequence
device Reset true exception because interrupt controller involved Reset process. PIC24 device clears registers response Reset which forces zero. microcontroller then begins program execution location 000000h. user programs GOTO instruction Reset address, which redirects program execution appropriate start-up routine. Note: unimplemented unused vector locations AIVT should programmed with address default interrupt handler routine that contains RESET instruction.
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FIGURE 6-1: PIC24 INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Start Code 000000h 000002h 000004h
000014h
Decreasing Natural Order Priority
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh 000100h 000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h
0001FEh 000200h
Note
Table Interrupt Vector list.
TABLE 6-1:
TRAP VECTOR DETAILS
Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 0001172h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
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Vector Number
Trap Source
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS
Vector Number Address 00002Eh 000038h 00009Ah 000014h 00003Ch 00004Eh 00007Eh 000080h 000036h 000034h 000078h 000076h 000016h 00001Eh 00005Eh 000060h 000062h 00003Ah 000018h 000020h 000046h 000048h 000066h 00006Eh 000090h 000026h 000028h 000054h 000056h 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h AIVT Address 00012Eh 000138h 00019Ah 000114h 00013Ch 00014Eh 00017Eh 000180h 000136h 000034h 000178h 000176h 000116h 00011Eh 00015Eh 000160h 000162h 00013Ah 000118h 000120h 000146h 000148h 000166h 00016Eh 000190h 000126h 000128h 000154h 000156h 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h Interrupt Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS0<0> IFS1<4> IFS1<13> IFS3<5> IFS3<6> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS1<3> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> Enable IEC0<13> IEC1<2> IEC4<3> IEC0<0> IEC1<4> IEC1<13> IEC3<5> IEC3<6> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC1<3> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<13> IEC3<13> IEC0<9> IEC0<10> IEC0<0> IEC2<1> IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC13<6:4> IPC13<10:8> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC4<14:12> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> Interrupt Source ADC1 Conversion Done Comparator Event Generator External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture Input Capture Input Capture Input Capture Input Capture Input Change Notification Output Compare Output Compare Output Compare Output Compare Output Compare Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter
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Interrupt Control Status Registers
interrupt sources assigned IFSx, IECx IPCx registers same sequence that they listed Table 6-2. example, INT0 (External Interrupt shown having vector number natural order priority Thus, INT0IF status found IFS0<0>, enable IEC0<0> priority bits first position IPC0 (IPC0<2:0>). Although they specifically part interrupt control hardware, control registers contain bits that control interrupt functionality. STATUS register (SR) contains IPL2:IPL0 bits (SR<7:5>). These indicate current interrupt priority level. user change current priority level writing bits. CORCON register contains IPL3 bit, which together with IPL2:IPL0, also indicates current priority level. IPL3 read-only that trap events cannot masked user software. interrupt registers described Register through Register 6-30, following pages.
PIC24FJ128GA family devices implement total registers interrupt controller: INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC14, IPC16
Global interrupt control functions controlled from INTCON1 INTCON2. INTCON1 contains Interrupt Nesting Disable (NSTDIS) bit, well control status flags processor trap sources. INTCON2 register controls external interrupt request signal behavior Alternate Interrupt Vector Table. registers maintain interrupt request flags. Each source interrupt status which respective peripherals, external signal, cleared software. registers maintain interrupt enable bits. These control bits used individually enable interrupts from peripherals external signals. registers used interrupt priority level each source interrupt. Each user interrupt source assigned eight priority levels.
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REGISTER 6-1:
Upper Byte:
STATUS REGISTER CPU)
Lower Byte: R/W-0 R/W-0 IPL2(1,2) IPL1(1,2)
R/W-0 IPL0(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
IPL2:IPL0: Interrupt Priority Level Status bits(1,2) interrupt priority level (15). User interrupts disabled. interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level Note bits concatenated with IPL3 (CORCON<3>) form interrupt priority level. value parentheses indicates IPL3 Status bits read-only when NSTDIS (INTCON1<15>)
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
REGISTER 6-2:
Upper Byte:
CORCON: CORE CONTROL REGISTER
Lower Byte:
R/C-0 IPL3(1)
R/W-0
IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than peripheral interrupts disabled interrupt priority level less Note IPL3 concatenated with IPL2:IPL0 bits (SR<7:5>) form interrupt priority level.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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REGISTER 6-3:
Upper Byte: R/W-0 NSTDIS
INTCON1: INTERRUPT CONTROL REGISTER
Lower Byte:
R/W-0 R/W-0 MATHERR ADDRERR
R/W-0 STKERR
R/W-0 OSCFAIL
NSTDIS: Interrupt Nesting Disable Interrupt nesting disabled Interrupt nesting enabled Unimplemented: Read MATHERR: Arithmetic Error Trap Status Overflow trap occurred Overflow trap occurred ADDRERR: Address Error Trap Status Address error trap occurred Address error trap occurred STKERR: Stack Error Trap Status Stack error trap occurred Stack error trap occurred OSCFAIL: Oscillator Failure Trap Status Oscillator failure trap occurred Oscillator failure trap occurred Unimplemented: Read Legend: Readable Value Writable Unimplemented bit, read cleared unknown
14-5
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REGISTER 6-4:
Upper Byte: R/W-0 ALTIVT DISI
INTCON2: INTERRUPT CONTROL REGISTER
Lower Byte:
R/W-0 INT4EP
R/W-0 INT3EP
R/W-0 INT2EP
R/W-0 INT1EP
R/W-0 INT0EP
ALTIVT: Enable Alternate Interrupt Vector Table alternate vector table standard (default) vector table DISI: DISI Instruction Status DISI instruction active DISI active Unimplemented: Read INT4EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT3EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT2EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT1EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT0EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge Legend: Readable Value Writable Unimplemented bit, read cleared unknown
13-5
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REGISTER 6-5:
Upper Byte:
IFS0: INTERRUPT FLAG STATUS REGISTER
R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF
Lower Byte: R/W-0 R/W-0 T2IF OC2IF
R/W-0 IC2IF
R/W-0 T1IF
R/W-0 OC1IF
R/W-0 IC1IF
R/W-0 INT0IF
15,14 Unimplemented: Read AD1IF: Conversion Complete Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1TXIF: UART1 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1RXIF: UART1 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1IF: SPI1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPF1IF: SPI1 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred T3IF: Timer3 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T2IF: Timer2 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC2IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC2IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read T1IF: Timer1 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC1IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC1IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT0IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred
Legend: Readable Value
Writable
Unimplemented bit, read cleared unknown
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REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF Upper Byte: R/W-0 R/W-0 U2TXIF U2RXIF
Lower Byte:
R/W-0 INT1IF
R/W-0 CNIF
R/W-0 CMIF
R/W-0 MI2C1IF
R/W-0 SI2C1IF
U2TXIF: UART2 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U2RXIF: UART2 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT2IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred T5IF: Timer5 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T4IF: Timer4 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC4IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC3IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT1IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred CNIF: Input Change Notification Interrupt Flag Status Interrupt request occurred Interrupt request occurred CMIF: Comparator Interrupt Flag Status Interrupt request occurred Interrupt request occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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REGISTER 6-7:
Upper Byte:
IFS2: INTERRUPT FLAG STATUS REGISTER
R/W-0 PMPIF R/W-0 OC5IF
Lower Byte: R/W-0 R/W-0 IC5IF IC4IF 15-14 Unimplemented: Read
R/W-0 IC3IF
R/W-0 SPI2IF
R/W-0 SPF2IF
PMPIF: Parallel Master Port Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC5IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read IC5IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC4IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC3IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read SPI2IF: SPI2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI2IF: SPI2 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred Legend: Readable Value Writable Unimplemented bit, read cleared unknown
12-10 Unimplemented: Read
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REGISTER 6-8:
Upper Byte: R/W-0 RTCIF
IFS3: INTERRUPT FLAG STATUS REGISTER
Lower Byte: R/W-0 INT4IF Unimplemented: Read
R/W-0 INT3IF
R/W-0 MI2C2IF
R/W-0 SI2C2IF
RTCIF: Real-Time Clock/Calendar Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT4IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT3IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read MI2C2IF: Master I2C2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read Legend: Readable Value Writable Unimplemented bit, read cleared unknown
13-7
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REGISTER 6-9:
Upper Byte:
IFS4: INTERRUPT FLAG STATUS REGISTER
Lower Byte: 15-4
R/W-0 CRCIF
R/W-0 U2ERIF
R/W-0 U1ERIF
Unimplemented: Read CRCIF: Generator Interrupt Flag Status Interrupt request occurred Interrupt request occurred U2ERIF: UART2 Error Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1ERIF: UART1 Error Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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REGISTER 6-10:
Upper Byte:
IEC0: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE
Lower Byte: R/W-0 R/W-0 T2IE OC2IE
R/W-0 IC2IE
R/W-0 T1IE
R/W-0 OC1IE
R/W-0 IC1IE
R/W-0 INT0IE
15-14 Unimplemented: Read AD1IE: Conversion Complete Interrupt Enable Interrupt request enabled Interrupt request enabled U1TXIE: UART1 Transmitter Interrupt Enable Interrupt request enabled Interrupt request enabled U1RXIE: UART1 Receiver Interrupt Enable Interrupt request enabled Interrupt request enabled SPI1IE: SPI1 Transfer Compl
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