VCXO-Based Line Card Clock Synchronizer MK2069-01 VCXO (Voltage C
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MK2069-01
VCXO-Based Line Card Clock Synchronizer
MK2069-01 VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation, frequency multiplication translation. accept unstable, jittery input clock provide de-jittered, phase noise output clock user determined frequency. device's clock multiplication ratios user selectable since major divider blocks configured through device settings. External loop filter components allow tailoring VCXO loop response therefore clock jitter attenuation characteristics. MK2069-01 ideal line card applications. three input enables selection master slave (backup) system clocks, well backup local line card clock. lock detector (LD) output serves clock status monitor. clear (CLR) input enables rapid synchronization phase newly selected input clock, while eliminating generation extra clock cycles wander caused memory feedback divider. also serves temporary holdover function when kept low.
Features
Input clock frequency 1kHz 170MHz Output clock frequency 500kHz 160MHz Jitter attenuation input clock provided VCXO
circuit. Jitter transfer characteristics user configured through selection external loop filter components. Input input reference clocks lock status output Clear function allows seamless synchronizing altered input clock phase, virtually eliminating generation wander extra clock cycles. VCXO-based clock generation offers very jitter phase noise generation, even with frequency jittery input clock. provides translation VCXO output (VCLK) higher alternate clock frequencies (TCLK). Device will free-run absence input clock based VCXO crystal frequency. TSSOP package Single 3.3V power supply tolerant inputs ICLK0 ICLK1
Block Diagram
VCLK
Phase etector
VCXO
Charge
TCLK
VCXO
RCLK
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MK2069-01 Line Card Clock Synchronizer
Assignment
VDDT GNDT VDDV GNDV TCLK VDDP VCLK GNDP RCLK FV11 FV10
VCXO Feedback Divider Selection
FV11:0 Divider Ratio Notes 0.00 addresses 4094, 0.01 Divide Address 1.10 4096 1.11
VCXO Scaling Divider Selection Table
Divider Ratio
Translator Reference Divider Selection Table
Divider Ratio
Translator Feedback Divider Selection
FT5:0 Divider Ratio Notes
Input Selection Tables
Input Selection Table
Input Selection ICLK0 ICLK0 ICLK1 ICLK2
000000 000001 111110 111111
addresses Divide Address
Translator Scaling Divider Selection Table
Divider Ratio
VCXO Reference Divider Selection Table
Divider Ratio
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MK2069-01 Line Card Clock Synchronizer
Descriptions
Number
Name
VDDT GNDT VDDV GNDV ISET FV10 FV11 ICLK2 ICLK0 RCLK GNDP
Type
Input Input Input Input Input Input Input Input Input Input Input Power Ground Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Ground Output Ground
Scaling Divider input, Translator (internal pull-up). Scaling Divider input, Translator (internal pull-up). Reference Divider input, Translator (internal pull-up). Reference Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Feedback Divider input, Translator (internal pull-up). Reference Divider input, VCXO (internal pull-up). Power Supply connection translator PLL. Ground connection translator PLL. Crystal oscillator input. Connect this external reference crystal. Power Supply connection VCXO PLL. Crystal oscillator output. Connect this external reference crystal. Ground connection VCXO PLL. Loop filter connection, reference node. Refer loop filter circuit page Loop filter connection, active node. Refer loop filter circuit page Charge pump current setting input. Refer loop filter circuit page Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Feedback Divider input, VCXO (internal pull-up). Input selection (internal pull-up). Reference clock input Reference clock input tolerant input. Clear input, clears VCXO dividers when (internal pull-up). Lock detector threshold setting circuit connection. Refer circuit page Digital ground connection. Lock detector threshold setting circuit connection. Refer circuit page VCXO phase detector Reference Clock output. Ground connection output drivers (VCLK, TCLK, RCLK, LDR).
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MK2069-01 Line Card Clock Synchronizer
Number
Name
VCLK VDDP TCLK ICLK1
Type
Output Power Output Output Power Input Input Input Input Input Input Input Input Input Input
Clock output from VCXO Power Supply connection output drivers (VCLK, TCLK, RCLK, LDR). Clock output from Translator Lock detector output. Power Supply connection digital circuitry. Output enable RCLK. RCLK tri-stated when (internal pull-up). Output enable VCLK. VCLK tri-stated when (internal pull-up). Output enable TCLK. TCLK tri-stated translator disabled when (internal pull-up). Output enable LDR. Both tri-stated when (internal pull-up). Reference clock input tolerant input. Input selection input (internal pull-up). Reference Divider input, VCXO (internal pull-up). Scaler Divider input, VCXO (internal pull-up). Scaler Divider input, VCXO (internal pull-up). Scaler Divider input, VCXO (internal pull-up).
Functional MK2069-01 (phase locked loop) based clock generator that generates output clocks synchronized input reference clock. contains cascaded PLL's with user selectable divider ratios. first VCXO-based uses external pullable crystal part normal "VCO" (voltage controlled oscillator) function PLL. VCXO assures phase noise clock source even when loop bandwidth implemented. loop bandwidth needed when input reference frequency low, when jitter attenuation input reference desired. second used translate multiply frequency VCXO which maximum output frequency MHz. This second PLL, Translator PLL, uses on-chip circuit that provide output clock MHz. Translator uses high loop bandwidth (typically greater than MHz) assure stability clock output. requires stable, high frequency input reference which provided VCXO PLL. divide values divider blocks within both PLLs device configuration. This enables system designer define following:
Input clock frequency VCXO crystal frequency VCLK output frequency RCLK output frequency, which also phase detector frequency VCXO PLL. TCLK output frequency
unused clock logic outputs tri-stated reduce interference (jitter, phase noise) other clock outputs. Outputs also tri-stated system testing purposes. External components used configure VCXO loop response. This serves maximize loop stability achieve desired input clock jitter attenuation characteristics.
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Application Information
MK2069-01 mixed analog digital integrated circuit that sensitive (printed circuit board) layout external component selection. Used properly, device will provide same high performance expected from canned VCXO-based hybrid timing device, lower cost. help avoid unexpected problems, guidance provided sections below should followed.
Setting TCLK Output Frequency
clock frequency TCLK determined Divider f(TCLK) f(VCLK) Divider Where: Divider Divider frequency range TCLK operational range internal circuit output divider selections: f(TCLK) f(VC0) Divider
Setting VCLK Output Frequency
frequency VCLK output determined following relationship: Divider f(VCLK) f(ICLK) Divider Where: Divider 4096 Divider 1,2,4 operational frequency range VCLK allowable frequency range external VCXO crystal internal VCXO divider selections: f(VCLK)
Where: f(VCO) Divider 2,4,8 higher frequency will generally produce lower phase noise therefore preferred.
MK2069-01 Loop Response JItter Attenuation Characteristics
MK2069-01 will reduce transfer phase jitter existing input reference clock output clock. This operation known jitter attenuation. low-pass frequency response VCXO loop mechanism that provides input jitter attenuation. Clock jitter, more accurately called phase jitter, overall instability clock period which measured time domain using oscilloscope, instance. Jitter comprised phase noise which represented frequency domain. phase noise input reference clock attenuated according VCXO low-pass frequency response curve. response curve, thus jitter attenuation characteristics, established through selection external MK2069-01 passive components other device setting explained following section.
VCXO Divider
Where: F(VCXO) F(External Crystal) Divider 1,2,4,6,8,10,12 higher crystal frequency will generally produce lower phase noise therefore preferred. crystal frequency between 13.5 recommended. Because VCLK generated external crystal, frequency range VCLK given configuration limited pullable range crystal. This guaranteed +/-115 minimum. This frequency range also applies input clock other clock outputs device remain frequency locked input, which required normal operation.
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Setting VCXO Loop Response.
VCXO loop response determined both fixed device characteristics other characterizes user. This includes values RSET shown External VCXO Components figure this page. VCXO loop bandwidth approximated
NBW(VCXO PLL) Divider Divider
External VCXO Components
DON'T STUFF Refer "Crystal Tuning Load Capacitors" Section
Where: Value resistor loop filter Ohms Charge pump current amps (see table page VCXO Gain Hz/V (see table page Divider 1,2,4,6,8,10,12 Divider 4096 above equation calculates "normalized" loop bandwidth (denoted "NBW") which approximately equal bandwidth. does take into account effects damping factor second pole imposed does, however, provide useful approximation filter performance. prevent jitter VCLK modulation VCXO phase detector frequency, following general rule should observed: NBW(VCO PLL)
Optional Crystal Tuning Capacitors
MK2069
XTAL
RSET
ISET
f(Phase Detector)
loop damping factor determined
DF(VCLK) Divider Divider
Where: Value capacitor loop filter Farads
general, loop damping factor should greater ensure output stability. higher damping factor will create less peaking passband will further ensure output stability with presence system power supply noise. damping factor will ensure passband peak less then 0.2dB which required network clock wander transfer compliance. higher damping factor also increase output clock jitter when there excess digital noise system application, reduced ability respond therefore compensate phase noise ingress.
Notes setting value
another general rule, following relationship should maintained between components loop filter:
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establishes second pole VCXO loop filter. higher damping factors calculate value based value that would used damping factor This will minimize baseband peaking loop instability that lead output jitter. also dampens VCXO input voltage modulation charge pump correction pulses. value that will result increased output phase noise phase detector frequency this. extreme cases where input jitter high, charge pump current high, small, VCXO input voltage
supply ground rail resulting non-linear loop response. best value filter response software available from (please refer following section). should increased value until just starts affecting passband peak.
Loop Filter Response Software
Online tools calculate loop filter response found www.icst.com.
Graph Charge Pump Current Value RSET (external resistor)
1E-3
ICP, Amps
100E-6
10E-6 100E+3
1E+6
RSET, ohms
Recommended Range Operation
10E+6
Charge Pump Current, Example Settings from Above Graph
RSET Charge Pump Current (ICP)
problems, output clock cycle slips, frequency phase noise. seen loop bandwidth damping factor equations using filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth damping factor.
Notes Setting Charge Pump Current
recommended range charge pump current Below loop filter charge leakage, capacitor leakage, become problem. This loop filter leakage cause locking
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MK2069-01 Line Card Clock Synchronizer
VCXO Gain (KO) XTAL Frequency
6000
Notes Setting Divider Values
shown loop bandwidth damping factor equations page using filter response software available from ICS, increasing decreases both bandwidth damping factor. Many applications require that these cases, decrease loop bandwidth increase value which accompanied increase value maintain same frequency multiplication ratio. However, phase detector frequency, FPD, also needs considered. equal input frequency divided value divider. should typically least loop bandwidth prevent loop modulation (phase noise) phase detector frequency. phase detector jitter tolerance limit (use 0.4UI) input phase noise frequency aliasing should considerations well.
5000
4000
3000
2000
1000
Example Loop Filter Component Value
Input Clock 19.44 Xtal Freq (MHz) 19.44 19.44 22.368 19.44 VCLK (MHz) 19.44 19.44 22.368 19.44 2430 2430 2796 RSET
Loop Loop Damp. (-3dB) 0.85
Passband Peaking 0.15dB 1.2dB 0.12dB 1.8dB
Note
Notes: This filter configuration assures passband ripple compliant with Bellcore GR-1244 satisfy wander transfer requirements (<0.2 ripple required) network node. used following system synchronizer such MT9045 provide clock jitter attenuation while maintaining Stratum compliance. 155.52 TCLK output generated with VCXO configuration will OC-3 OC-12 timing jitter compliant. This reduced cost size variant above filter, decreased size useful when GR-1244 compliance needed, such network access application. This configuration used generate clock 44.768 TCLK output. This configuration GR-1244 compliant. MK2069-02 MK2069-04 more suitable this application since VCXO feedback divider increased (>128), enabling lower bandwidth improved jitter attenuation.
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Loop Filter Capacitor Type
Loop filters must specific types capacitors. Recommendations these capacitors found www.icst.com.
eliminating generation extra VCLK clock cycle that would occur loop re-lock under normal means. Lock time also reduced, generation clock wander. using this fashion VCLK will align input clock phase with only VCLK cycle slips resulting. When used, number VCLK cycle slips high Divider value. TCLK always locked VCLK regardless state input.
Input
MK2069-01 incorporates input clock multiplexer `mux' that allows selection between three alternate reference inputs supplied device. input selection pins asynchronous non-latched. Please refer Input Selection Table page Note that inputs ICLK0 ICLK1 tolerant, whereas ICLK2 not.
Lock Detection
MK2069-01 includes lock detection feature that indicates lock status VCLK relative selected input reference clock. When phase lock achieved (such following power-up), output goes high. When phase lock lost (such when input clock stops, drifts beyond pullable range crystal, suddenly shifts phase), output goes low. definition "locked" condition determined user. high when VCXO phase detector error below user-defined threshold. This threshold external components shown Lock Detection Circuit Diagram, below. help guard against false lock indications, will high only when phase error below threshold consecutive phase detector cycles. will when phase error above threshold only phase detector cycle. lock detector threshold (phase error) determined following relationship: Threshold)
Where:
Input Phase Compensation Circuit
VCXO includes special input clock phase compensation circuit. used when selecting reference input that clock phase differing from previously selected input. phase compensation circuit allows VCXO quickly lock input phase without producing extra clock cycles clock wander, assuming clock same frequency. Input controls phase compensation circuit. must remain high normal operation. When used conjunction with input select pins, should brought prior reselection, then returned high after reselection. This prevents VCXO from attempting lock input clock phase associated with input clock. When high, VCXO operates normally. When low, VCXO charge pump output inactivated which means that charge pump correction pulses provided loop filter. During this time, VCXO frequency held constant residual charge voltage loop filter, regardless input clock condition. However, VCXO frequency will drift over time, eventually minimum pull range crystal, leak-off loop filter charge. This means that provide holdover function, only very short duration, typically milliseconds. Upon bringing high, Divider reset begins counting upon with first positive edge input clock, charge pump re-activated. resetting Divider, memory previous input clock phase removed from feedback divider,
2069-01 Integrated Circuit Systems
avoid excessive noise leakage) avoid excessive error stray capacitance, which much including LDC) Lock Detector Application example: desired maximum allowable loop phase error generated 19.44MHz clock 100UI which Solution: (0.001 (8.5
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Under ideal conditions, where VCXO phaselocked low-jitter reference input, loop phase error typically maintained within nanoseconds.
Clock noise from device pins must onto
power plane system problems result. This above requirements served circuit illustrated Recommended Power Supply Connection (next page). main features this circuit follows:
Lock Detection Circuit Diagram
ctio
Lock lific
RESET
Only connection made power
plane.
capacitors ferrite chip ferrite bead)
VCXO Phase
common device supply form lowpass `pi' filter that remove noise from power supply well clock noise back toward supply. bulk capacitor should tantalum type, minimum. other capacitors should ceramic type.
power supply traces individual pins
should common supply filter reduce interaction between device circuit blocks.
decoupling capacitors pins should
ceramic type should close possible. There should via's between decoupling capacitor supply pin.
lock detection circuit used, output remain unconnected, however input should tied high low. designed accommodate components output will used, remain unstuffed replaced with resistor kohm).
Power Supply Considerations
with integrated clock device, MK2069-01 special power supply requirements:
feed from system power supply must
filtered noise that cause output clock jitter. Power supply noise sources include system switching power supply other system components. noise interfere with device components such phase detector.
Each must decoupled individually
prevent power supply noise generated device circuit block from interfering with another circuit block.
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MK2069-01 Line Card Clock Synchronizer
Recommended Power Supply Connection
capacitance 14pF. achieve this, layout should short traces between MK2069-01 crystal.
0.01
onnection 3.3V Plane
Recommended Crystal Parameters:
errite
0.01
Crystal parameters found application note MAN05 www.icst.com. Approved crystals found www.icst.com (search "crystal").
Crystal Tuning Load Capacitors
Series Termination Resistor
Output clock traces over inch should series termination maintain clock signal integrity reduce EMI. series terminate trace, which commonly used trace impedance, place resistor series with clock line close clock output possible. nominal impedance clock output
0.01
crystal traces should include pads small capacitors from ground, shown External VCXO Components diagram page These capacitors used center total load capacitor adjustment range imposed crystal. load adjustment range includes stray capacitance that varies with board layout. Because typical telecom reference frequency accurate less than ppm, MK2069-01 operate properly without these adjustment capacitors. However, recommends that these capacitors included minimize effects variation individual crystals, including those induced temperature aging. value these capacitors (typically determined once given board layout, using procedure described MAN05.
0.01
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please refer Recommended Layout drawing following page. Each 0.01µF decoupling capacitor (CD) should mounted component side board close possible. via's should used between decoupling capacitor pin. trace should kept short possible, should trace ground via. Distance ferrite chip bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted close device possible, component side
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Quartz Crystal
MK2069-01 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters must used, layout guidelines discussed following section must followed. frequency oscillation quartz crystal determined load capacitors connected MK2069-01 incorporates variable load capacitors on-chip which "pull" change frequency crystal. crystals specified with MK2069-01 designed have zero frequency error when total on-chip stray
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board. This will keep crystal traces short which will minimize parasitic load capacitance crystal well noise pickup. crystal traces should spaced away from each other should minimum trace width. There should signal traces near crystal traces. Also refer Optional Crystal Shielding section that follows. minimize series termination resistor, needed, should placed close clock output. components should same side board, minimizing vias through other signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK2069-01. This includes signal traces traces just underneath device, layers adjacent ground plane layer used device. Because each input selection includes internal pull-up device, those inputs requiring logic high state ("1") left unconnected. pins requiring logic state ("0") grounded.
evaluation. crystal less sensitive system noise interference when case grounded. ground trace around crystal circuit shield from other active traces component layer. external crystal particularly sensitive other system clock sources that near crystal frequency since will lock interfering clock source. crystal should keep away from these clock sources. Applications Note MAN05 also referenced additional suggestions layout crystal section.
Optional Crystal Shielding
crystal connection traces pins sensitive noise pickup. applications that especially sensitive noise, such SONET G-Bit ethernet transceivers, some following crystal shielding techniques should considered. This especially important when MK2069-01 placed near high speed logic signal traces. following techniques illustrated Recommended Layout drawing. metal layer underneath crystal section should ground layer. Remove other layers that above. This ground layer will help shield crystal circuit from other system noise sources. alternative, layers underneath crystal removed, however this recommended there adjacent PCBs that induce noise into unshielded crystal circuit. channel ground plane around crystal area shown. This will eliminate high frequency ground currents that couple into crystal circuit. through-hole optional third lead offered crystal manufacturer (case ground). requirement this third lead made prototype
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Recommended Layout Diagram
SUPPLY SOURCE DEVICE (SUCH SUPPLY PLANE) OPTIONAL CRYSTAL SHIELDING THRU HOLE LEAD (XTAL CASE GROUND) SHIELD TRACE (TOP LAYER) CHANNEL GROUND PLANE
XTAL
MK2069
1206
RSET
Components identified function (top line) typical package type (bottom line) which vary. Legend: Ground plane Power Plane suppression cap, typical value (ceramic) Ferrite chip Bulk decoupling capacitor chip power supply, minimum (tantalum) Bulk bypass chip power supply, typical value 1000 (ceramic) Decoupling capacitor (ceramic) Optional load capacitor crystal tuning stuff) External loop capacitor (film type) External loop capacitor (film type) External loop resistor RSET Resistor RSET used charge pump current Series termination resistor clock output, typical value RLD* External resistor lock detector circuit CLD* External capacitor lock detector circuit *Note: output used, omitted. text page
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Circuit Troubleshooting
TCLK VCLK does lock ICLK
First check VCLK ICLK. best display trigger scope with RCLK, especially non-integer VCXO multiplication ratio used. VCLK locked ICLK: 1.1) Ensure proper ICLK input selected. 1.2) Check Divider settings 1.3) Ensure ICLK within lock range (within about nominal input frequency, limited pull range external crystal). doubt, tweak ICLK frequency down VCLK locks. 1.4) Ensure ICLK jitter excessive. ICLK jitter excessive device lock. Also item below. 1.5) Clean PCB. VCXO loop filter very sensitive board leakage, especially when VCXO phase detector frequency kHz. organic solder flux used (most common today) scrub board with detergent water then blow bake dry. Inorganic solder flux (Rosen core) requires solvent. also section below.
2.3) VCLK TCLK jitter also caused poor power supply decoupling. Ensure bulk decoupling capacitor place. 2.4) Ensure that VCXO loop bandwidth sufficiently low. should least 1/20th phase detector frequency. 2.5) Ensure that VCXO loop damping sufficient. should least 0.7, preferably higher. 2.6) Ensure that pole VCXO loop filter sufficiently. general, should equal CS/20. high, passband peaking will occur loop instability occur. low, excessive VCXO modulation charge correction pulses occur.
There Excessive Input Output Skew
3.1) TCLK should track VCLK. rising edge TCLK should within nanoseconds VCLK. 3.1) VCLK should track RCLK. rising edge VCLK should within 5-10 nsec RCLK (VCLK leads). 3.3) biggest cause input output skew VCXO loop filter leakage. Skew best observed comparing ICLK RCLK. When leakage present rising edge RCLK should rising edge ICLK about usec. Loop filter leakage greatly increase this time cause loop lock. Refer item 1.5, above. 3.4) Another view loop filter leakage observe pin. RCLK scope trigger. will produce negative pulse equal length charge pump pulse. 3.5) Filter leakage also caused improper loop capacitors. Refer section titled `Loop Filter Capacitor Type' page
There Excessive Jitter VCLK TCLK
2.1) problem unstable input reference clock. unstable ICLK will appear jitter when ICLK used oscilloscope trigger source. this condition, VCLK TCLK appear unstable since jitter from ICLK (the trigger source) been removed trigger circuit scope. 2.2) instability caused VCXO loop filter leakage. Refer item above.
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Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2069-01. These ratings stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5V VDD+0.5V +85°C +150°C 175°C 260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
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Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current
Symbol
Conditions
clock outputs loaded with VCLK 19.44 MHz, TCLK 155.52
Min.
3.15
Typ.
Max.
3.45
Units
Input High Voltage, MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0 Input Voltage, MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0 Input Pull-Up Resistor (Note Input High Voltage, ICLK2, Input High Voltage, ICLK1:0 Input Voltage, ICLK2:0, Input High Current (Note Input Current (Note Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage Output Short Circuit Current, TCLK Output Short Circuit Current, VCLK, RCLK VIN, VCXO Control Voltage
-0.4
VDD-0.4
VDD/2+1 VDD/2+1
VDD/2-1
-0.4
Note logic select inputs (MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0, CLR) have internal pull-up resistor.
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Electrical Characteristics
Unless stated otherwise, 3.3V ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Frequency Range (Note VCXO Crystal Pull Range VCXO Crystal Free-Run Frequency (Note Input Clock Frequency (Note Input Clock Pulse Width VCXO Phase Detector Frequency (Note VCXO Phase Detector Jitter Tolerance Translator Frequency Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) Timing Jitter, Filtered 65kHz-5MHz (OC-3) Timing Jitter, Filtered 1kHz-5MHz (OC-12) Timing Jitter, Filtered 250kHz-5MHz (OC-12) Output Duty Cycle high time), VCLK when Divider Output Duty Cycle high time), VCLK when Divider TCLK Output High Time, RCLK (Note Output Rise Time, VCLK RCLK Output Fall Time, VCLK RCLK
Symbol
fXTAL tOJf
Conditions
Using recommended crystal Using recommended crystal Input reference
Min.
13.5 ±115 -300 0.001
Typ.
Max. Units
nsec
±150 -150
Positive Negative Pulse
0.001
phase detector period Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Derived from phase noise characteristics, peak-to-peak sigma Measured VDD/2, CL=15pF Measured VDD/2, CL=15pF Measured VDD/2, CL=15pF 2.0V, CL=15pF 0.8V, CL=15pF
tOJf
tOJf
tOJf
VCLK Period
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Parameter
Output Rise Time, TCLK Output Fall Time, TCLK Skew, ICLK VCLK (Note Skew, ICLK RCLK (Note Skew, ICLK TCLK (Note Nominal Output Impedance
Symbol
ZOUT
Conditions
2.0V, CL=15pF 0.8V, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF Rising edges, CL=15pF
Min.
Typ.
0.75 0.75
Max. Units
Note This recommended crystal operating range. crystal used, although this result increased output phase noise. Note VCXO crystal will pulled minimum frequency when there input clock (CLR attempt lock Note minimum practical input frequency kHz. Through proper loop filter design lower input frequencies possible. Note output RCLK positive pulse with duration equal VCLK high time, half VCLK period. Note Referenced ICLK, skews VCLK, RCLK TCLK increase together when leakage present external VCXO loop filter.
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Package Outline Package Dimensions
TSSOP 6.10 (240 mil) body, 0.50 mil) pitch Package dimensions kept current with JEDEC Publication
Millimeters Symbol
Inches
-1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 Basic 0.45 0.75 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 Basic 0.018 0.030 -0.004
Ordering Information
Part Order Number
MK2069-01GI MK2069-01GITR
Marking
MK2069-01GI MK2069-01GI
Shipping packaging
Tubes Tape Reel
Package
TSSOP TSSOP
Temperature
+85° +85°
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