3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

Datasheet Thumbnail

Top Searches for this datasheet

IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available SSOP, TSSOP, TVSOP packages
IDT74ALVCH16843
FEATURES:
DESCRIPTION:
ALVCH16843 built using advanced dual metal CMOS technology. This device 9-bit D-type latches featuring separate D-type inputs each latch 3-state outputs oriented applications. sections each register controlled independently latch enable (LE), clear (CLR), preset (PRE) output enable (OE) control pins. When low, data registers appear outputs. When high, outputs high impedance state. Operation input does affect state flip-flops. ALVCH16843 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH16843 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V high speed systems 3.3V lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1CLR
1PRE
logo registered trademark Integrated Device Technology, Inc.
©1999 Integrated Device Technology, Inc.
2CLR 2PRE EIGHT OTHER CHANNELS EIGHT OTHER CHANNELS
OCTOBER 1999
DSC-5154/1
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
CONFIGURATION
1CLR 2CLR 1PRE 2PRE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) VTERM(3) TSTG IOUT Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100
Unit
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
FUNCTION TABLE(1)
Inputs xPRE xCLR Output Q(2)
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names xCLR xPRE Description Clear input (Active LOW) Output enable input (Active LOW) Preset input (Active LOW) Latch enable input Data inputs(1) 3-State Data outputs Ground (0V) Positive supply voltage
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance Output level before indicated steady-state input conditions were established.
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) -0.7 Max. -1.2 Unit
Quiescent Power Supply Current Variation
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tREM tREM tSK(O) Parameter Propagation Delay Propagation Delay Propagation Delay xPRE Propagation Delay xCLR Output Enable Time Output Disable Time Set-up Time, Hold Time, Pulse Width HIGH xPRE Pulse Width xCLR Pulse Width Recovery Time xPRE Recovery Time xCLR Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator
VLOAD Open
VLOAD/2
ALVC Link
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
Pulse Width
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH16843 3.3V CMOS 18-BIT BUS-INTERACE D-TYPE LATCH WITH 3-STATE OUTPUTS
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-Bit Interface D-Type Latch with 3-State Outputs Double-Density with Resistors, ±24mA Bus-Hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com
Tech Support: logichelp@idt.com (408) 654-6459

3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

Top Searches for this datasheet

Other recent searches