DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR differenti
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ICS8735-01
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
differential 3.3V LVPECL outputs Selectable differential clock inputs CLKx, nCLKx pair accept following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Output frequency range: 31.25MHz 700MHz Input frequency range: 31.25MHz 700MHz range: 250MHz 700MHz Programmable dividers allow following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, External feedback "zero delay" clock regeneration with configurable frequencies Cycle-to-cycle jitter: 25ps (maximum) Output skew: 25ps (maximum) Static phase offset: 50ps 100ps 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS8735-01 highly versatile Differential-to-3.3V LVPECL clock generator HiPerClockSmember HiPerClockSfamily High Performance Clock Solutions from ICS. ICS8735-01 fully integrated configured zero delay buffer, multiplier divider, output frequency range 31.25MHz 700MHz. reference divider, feedback divider output divider each programmable, thereby allowing following output-toinput frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. external feedback allows device achieve "zero delay" between input clock output clocks. PLL_SEL used bypass system test debug purposes. bypass mode, reference clock routed around into internal output dividers.
BLOCK DIAGRAM
PLL_SEL
÷16, ÷32,
ASSIGNMENT
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL
PLL_SEL SEL3
VCCO
VCCA
CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN
VCCO VCCO
8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
ICS8735-01
SEL0 SEL1 SEL2 SEL3
32-Lead (LQFP) 1.4mm package body Package View
nFB_IN
FB_IN
SEL2
VCCO
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Description
TABLE DESCRIPTIONS
Number Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Type Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects CLK1, nCLK1. Pulldown When LOW, selects CLK0, nCLK0. LVCMOS LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs high. Pulldown When logic LOW, internal dividers otuputs enabled. LVCMOS LVTTL interface levels. Core supply pins. Pullup Feedback input phase detector regenerating clocks with "zero delay". Pulldown Feedback input phase detector regenerating clocks with "zero delay". Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Analog supply pin. Selects between reference clock input dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS LVTTL interface levels.
nFB_IN FB_IN SEL2 nQ0, VCCO nQ1, nQ2, nQ3, nQ4, SEL3 VCCA PLL_SEL
Input Power Input Input Input Power Output Power Output Output Output Output Input Power Input
Pullup
NOTE: Pullup Pulldown refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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Outputs PLL_SEL Enable Mode Q0:Q4, nQ0:nQ4
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* 62.5 31.25 87.5 62.5 62.5 31.25 87.5 62.5 31.25 87.5 31.25 87.5
*NOTE: frequency range configurations above 700MHz.
TABLE BYPASS FUNCTION TABLE
Inputs SEL3
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SEL2
SEL1
SEL0
Outputs PLL_SEL Bypass Mode Q0:Q4, nQ0:nQ4
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
4.6V -0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter VCCA VCCO ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage Input High Current CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, SEL0, SEL1, SEL2, SEL3 PLL_SEL 3.465V 3.465V 3.465V 3.465V -150 Test Conditions Minimum -0.3 Typical Maximum Units
Input Current
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions 3.465V 3.465V 3.465V 3.465V -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE VCMR NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V. NOTE Common mode voltage defined VIH.
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Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL PLL_SEL Minimum 31.25 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fMAX sk(o) jit(cc) jit() Parameter Output Frequency Propagation Delay; NOTE Static Phase Offset; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; NOTE Phase Jitter; NOTE Lock Time Output Rise Time Output Fall Time 50MHz 50MHz PLL_SEL 700MHz PLL_SEL 3.3V Test Conditions Minimum Typical Maximum Units
Output Duty Cycle parameters measured fMAX unless noted otherwise. NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined time difference between input reference clock averaged feedback input signal, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE Phase jitter dependent input source used. NOTE This parameter defined accordance with JEDEC Standard NOTE Characterized frequency 622MHz.
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA VCCO
SCOPE
LVPECL
nCLK0, nCLK1 CLK0, CLK1
Cross Points
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
tsk(o)
nQ0:nQ4 Q0:Q4
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
Clock Outputs
CYCLE-TO-CYCLE JITTER
nQ0:nQ4 Q0:Q4
Pulse Width
PERIOD
PERIOD
OUTPUT RISE/FALL TIME
tPERIOD
nCLK0, nCLK1 CLK0, CLK1
nFB_IN FB_IN
Q0:Q4
mean Phase Jitter mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
PROPAGATION DELAY
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PHASE JITTER STATIC PHASE OFFSET
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nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4
tcycle
ICS8735-01
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive
FOUT FOUT
transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
(VOH
FIGURE LVPECL OUTPUT TERMINATION
WIRING
DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
Single Ended Clock Input
CLKx
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8735AY-01
FIGURE LVPECL OUTPUT TERMINATION
V_REF
nCLKx
0.1u
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
3.3V .01µF
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8735-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
VCCA .01µF
FIGURE POWER SUPPLY FILTERING
LAYOUT GUIDELINE
schematic ICS8735-01 layout example shown Figure ICS8735-01 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will
depend selected component types, density components, density traces, stack P.C. board.
Space (i.e. intstalled)
CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 PLL_SEL SEL3 VCCA
SEL[3:0] 0101, Divide
0.01u
(77.76 MHz)
VCCO
LVPECL_input
3.3V
(155.52 MHz)
SEL0 SEL1
PLL_SEL VCCA SEL3 VCCO
CLK_SEL 3.3V PECL Driver
nFB_IN FB_IN SEL2 VCCO
SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL
VCCO VCCO
Output Termination Example
Bypass capacitor located near power pins
(U1-9)
(U1-32)
8735-01
VCC=3.3V
0.1uF 0.1uF
VCCO=3.3V
SEL2
(U1-16)
0.1uF
VCCO
(U1-17)
(U1-24)
(U1-25)
0.1uF
0.1uF
0.1uF
FIGURE ICS8735-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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following component footprints used this layout example: resistors capacitors size 0603.
ICS8735-01
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape
VCCO
VCCA
Traces
FIGURE BOARD LAYOUT ICS8735-01
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8735-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8735-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 150mA 520mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 151mW
Total Power_MAX (3.465V, with outputs switching) 520mW 151mW 671mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.671W 42.1°C/W 98°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8735-01
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50] 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8735-01 2969
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PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Marking ICS8735AY-01 ICS8735AY-01 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8735AY-01 ICS8735AY-01T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8735AY-01
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REVISION HISTORY SHEET Description Change changed Test Condtions from 0MHz 700MHz 700MHz. Date
Table
Page
Figure
changed Parameter name from Reference Zero Delay Static Phase Offset. tjit() changed Max. Max. Added ICCA row. Updated Block Diagram. Added note table. Added Note Revised Figure LVPECL Zero Delay Buffer Schematic Example Added Termination LVPECL Outputs section Description Table revised description. 3.3V Output Load Test Circuit Diagram, revised equation from "-1.3V 0.135V" -1.3V 0.165V". Revised Output Rise/Fall Time Diagram. LVPECL table corrected VSWING from max. max. Table changed from min. min, deleted typical.
10/12/01
10/30/01 11/1/01 11/19/01 12/3/01 6/3/02
8/19/02
9/17/02
Updated description read Core supply pins from Positive supply pins. Updated read Core Supply Voltage from Positive Supply Voltage. IEE, deleted 100mA typical added 150mA Maximum. Updated format. Description Table updated description. Corrected LVPECL Zero Delay Buffer Schematic Example. 12/3/02
1/31/03
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