700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR di
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
differential 3.3V LVPECL output pair, differential feedback output pair Differential CLK, nCLK input pair CLK, nCLK pair accept following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Output frequency range: 31.25MHz 700MHz Input frequency range: 31.25MHz 700MHz range: 250MHz 700MHz Programmable dividers allow following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, External feedback "zero delay" clock regeneration with configurable frequencies Cycle-to-cycle jitter: 25ps (maximum) Static phase offset: 50ps 100ps 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS8735-21 highly versatile Differential-to-3.3V LVPECL clock generator HiPerClockSmember HiPerClockSfamily High Performance Clock Solutions from ICS. CLK, nCLK pair accept most standard differential input levels. ICS8735-21 fully integrated configured zero delay buffer, multiplier divider, output frequency range 31.25MHz 700MHz. reference divider, feedback divider output divider each programmable, thereby allowing following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. external feedback allows device achieve "zero delay" between input clock output clocks. PLL_SEL used bypass system test debug purposes. bypass mode, reference clock routed around into internal output dividers.
BLOCK DIAGRAM
PLL_SEL
÷16, ÷32,
ASSIGNMENT
nQFB
nCLK
8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
nCLK nFB_IN FB_IN SEL2 nQFB
SEL1 SEL0 PLL_SEL VCCA SEL3 VCCO
FB_IN nFB_IN
ICS8735-21
20-Lead, 300-MIL SOIC 7.5mm 12.8mm 2.3mm body package Package View
SEL0 SEL1 SEL2 SEL3
ICS8735AM-21
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Type Description
TABLE DESCRIPTIONS
Number Name nCLK nFB_IN FB_IN SEL2 nQFB, VCCO SEL3 VCCA PLL_SEL SEL0 SEL1 Input Input Input Power Input Input Input Power Output Output Power Input Power Input Input Input Unused Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outpus inver outputs high. Pulldown When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Core supply pins. Feedback input phase detector regenerating clocks with "zero delay". Pullup Connect Feedback input phase detector regenerating clocks with "zero delay". Pulldown Connect Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Negative supply pin. Differential feedback outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Output supply pin. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Analog supply pin. Selects between reference clock input dividers. Pullup When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS LVTTL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. Pulldown Determines output divider values Table LVCMOS LVTTL interface levels. connect. Pullup
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
ICS8735AM-21
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL Enable Mode QFB, nQFB
TABLE CONTROL INPUT FUNCTION TABLE
Inputs SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* 62.5 31.25 87.5 62.5 62.5 31.25 87.5 62.5 31.25 87.5 31.25 87.5
*NOTE: frequency range configurations above 250MHz 700MHz.
TABLE BYPASS FUNCTION TABLE
Inputs SEL3
8735AM-21
SEL2
SEL1
SEL0
Outputs PLL_SEL Bypass Mode QFB, nQFB
REV. FEBRUARY 2003
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, VCCO Package Thermal Impedance, Storage Temperature, TSTG
4.6V -0.5V -0.5V VCCO 0.5V 46.2°C/W lfpm) -65°C 150°C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter VCCA VCCO ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage Input High Current SEL0, SEL1, SEL2, SEL3, PLL_SEL SEL0, SEL1, SEL2, SEL3, PLL_SEL 3.465V 3.465V 3.465V, 3.465V, -150 Test Conditions Minimum -0.3 Typical Maximum Units
Input Current
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current CLK, FB_IN nCLK, nFB_IN CLK, FB_IN nCLK, nFB_IN Test Conditions 3.465V 3.465V 3.465V, 3.465V, -150 0.15 0.85 Minimum Typical Maximum Units
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE VCMR NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V.
ICS8735AM-21
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input Frequency CLK, nCLK Test Conditions PLL_SEL PLL_SEL Minimum 31.25 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol fMAX tsk(o) jit(cc) jit() Parameter Output Frequency Propagation Delay; NOTE Output Skew; NOTE Static Phase Offset; NOTE Cycle-to-Cycle Jitter; NOTE Phase Jitter; NOTE Lock Time Output Rise Time Output Fall Time 50MHz 50MHz PLL_SEL 700MHz PLL_SEL PLL_SEL 3.3V Test Conditions Minimum Typical Maximum Units
Output Duty Cycle parameters measured fMAX unless noted otherwise. NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined time difference between input reference clock average feedback input signal, when locked input reference frequency stable. NOTE Phase jitter dependent input source used. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential crosspoints. NOTE This parameter defined accordance with JEDEC Standard NOTE Characterized frequency 622MHz.
8735AM-21
REV. FEBRUARY 2003
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
nCLK
LVPECL
Cross Points
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQFB tCycle
tJIT(cc) tCycle tCycle
tsk(o)
OUTPUT SKEW
nCLK nFB_IN nFB_IN
CYCLE-TO-CYCLE JITTER
nCLK
mean Phase Jitter mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
nQFB
PHASE JITTER
nQFB
STATIC PHASE OFFSET
PROPAGATION DELAY
Pulse Width
PERIOD
Clock Outputs
PERIOD
odc, tPERIOD
ICS8735AM-21
OUTPUT RISE/FALL TIME
REV. FEBRUARY 2003
tCycle
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8735-21 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VCC/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
CLK_IN V_REF
0.1uF
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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Integrated Circuit Systems, Inc. TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
SCHEMATIC EXAMPLE
Figure shows schematic example ICS8735-21. this example, input driven HCSL driver. zero delay buffer configured operate 155.52MHz input 77.75MHz output. logic control pins configured follows:
3.3V VCCA
(155.5 MHz)
SEL2
HCSL
PLL_SEL SEL0 SEL1 SEL2 SEL3
Space (i.e. intstalled)
FIGURE ICS8735-21 LVPECL BUFFER SCHEMATIC EXAMPLE
ICS8735AM-21
FIGURE LVPECL OUTPUT TERMINATION
[3:0] 0101; PLL_SEL decoupling capacitors should physically located near power pin. ICS8735-21.
nCLK VCCI nFB_IN FB_IN SEL2 nQFB ICS8735-21 SEL1 SEL0 VCCI PLL_SEL VCCA SEL3 VCCO SEL1 SEL0 PLL_SEL VCCA SEL3 0.01u
(77.75 MHz)
LVPECL_input
Bypass capacitors located near power pins
(U1-4) (U1-17)
0.1uF
(U1-13)
0.1uF
VCC=3.3V
0.1uF
SEL[3:0] 0101, Divide
REV. FEBRUARY 2003
Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples ICS8735-21 clock input driven most common driver types. input interfaces suggested here
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE ICS8735-21 CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE ICS8735-21 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
FIGURE ICS8735-21 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
8735AM-21
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8735-21. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8735-21 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 150mA 519.8mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 519.8mW 60.4mW 580.2mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 39.7°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.580W 39.7°C/W 93°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
20-PIN SOIC, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W
65.7°C/W 39.7°C/W
57.5°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
ICS8735AM-21
REV. FEBRUARY 2003
Calculations Equations.
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50] 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 46.2°C/W
65.7°C/W 39.7°C/W
57.5°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8735-21 2969
ICS8735AM-21
REV. FEBRUARY 2003
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 10.00 0.25 0.40 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 Millimeters Minimum 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication MS-013, MO-119
8735AM-21
REV. FEBRUARY 2003
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Marking ICS8735AM-21 ICS8735AM-21 Package Lead SOIC Lead SOIC Tape Reel Count tube 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8735AM-21 ICS8735AM-21T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. ICS8735AM-21
REV. FEBRUARY 2003
ICS8735-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description Change Revised Block Diagram. Added Output Skew 20ps Max. Relabled Reference Zero Delay Static Phase Offset. Added Output Skew Diagram. Added note bottom table. Added Note Added Termination LVPECL Outputs section Description Table revised description. 3.3V Output Load Test Circuit Diagram, revised equation from "-1.3V 0.135V" -1.3V 0.165V". Revised Output Rise/Fall Time Diagram. Added Schematic Example section Description table revised descriptions. Power Supply table revised Parameter correspond with description. Deleted Figure "Clock Input Driven LVPECL Driver w/AC Couple". Couple recommended Zero Delay Buffers. Date 10/31/01
Table
Page
11/20/01 6/3/02
8/19/02
10/17/02
2/03/03
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