700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESI
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ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
Fully integrated PLL, external loop filter requirements differential 3.3V LVPECL output Crystal oscillator interface: 10MHz 25MHz Output frequency range: 25MHz 700MHz range: 200MHz 700MHz Parallel serial interface programming dividers during power-up Period jitter: Cycle-to-cycle jitter: 15ps (typical) 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS84330-01 general purpose, single output high frequency synthesizer member HiPerClockSthe HiPerClockSfamily High Performance Clock Solutions from ICS. operates frequency range 200MHz 700MHz. output frequency programmed using serial parallel interfaces configuration logic. output configured divide frequency Output frequency steps from 250KHz 2MHz achieved using 16MHz crystal depending output divider setting.
compatible with SY89430V
BLOCK DIAGRAM
XTAL1 XTAL2
ASSIGNMENT
TEST FOUT nFOUT nP_LOAD XTAL2 XTAL1 VCCA S_LOAD S_DATA S_CLOCK VCCO FOUT nFOUT
PHASE DETECTOR
ICS84330-01
28-Lead SOIC 7.5mm 18.05mm 2.25mm body package Package View
nFOUT FOUT TEST VCCO
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
S_CLOCK S_DATA S_LOAD VCCA XTAL1
ICS84330-01
28-Lead PLCC Package 11.6mm 11.4mm 4.1mm View
XTAL2
nP_LOAD
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 16MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE
ICS84330-01 features fully integrated therefore requires external components setting loop bandwidth. quartz crystal used input on-chip oscillator. output oscillator divided prior phase detector. With 16MHz crystal this provides 1MHz reference frequency. operates over range 200MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency divided adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS84330-01 support input modes program divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input LOW. data inputs through through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. TEST output Mode (shift register out) when operating parallel input mode. relationship between frequency, crystal frequency divider defined follows: fxtal fVCO value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock defined 350. frequency defined follows: fout fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider each rising edge S_CLOCK. serial mode used program bits test bits T2:T0. internal registers T2:T0 determine state TEST output follows: TEST Output Shift Register High Reference Xtal (VCO (non Duty divider) fOUT LVCMOS Output Frequency 200MHz (S_CLOCK (non Duty Cycle divider) fOUT fOUT fOUT fOUT fOUT fOUT fOUT fOUT S_CLOCK divider fOUT
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
PARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
84330AV-01
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ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Description Core supply pins. Analog supply PLL. Negative supply pins. Output supply pin. connect.
TABLE DESCRIPTIONS
Name VCCA VCCO XTAL1, XTAL2 nP_LOAD S_CLOCK S_DATA S_LOAD TEST nFOUT, FOUT Power Power Power Power Unused Input Input Input Input Input Input Input Output Output Type
Crystal oscillator interface. XTAL1 input. XTAL2 output. Parallel load input. Determines when data present M8:M0 loaded into Pullup divider, when data present N1:N0 sets output divide value. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register Pulldown rising edge S_CLOCK. LVCMOS LVTTL interface levels. Shift register serial input. Data sampled rising edge S_CLOCK. Pulldown LVCMOS LVTTL interface levels. Controls transition data from shift register into divider. Pulldown LVCMOS LVTTL interface levels. Pullup Pullup divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS LVTTL interface levels. Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. Test output which used serial mode operation. LVCMOS LVTTL interface levels. Differential output synthesizer. 3.3V LVPECL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE PARALLEL
nP_LOAD Data Data
SERIAL MODE FUNCTION TABLE
Inputs S_LOAD S_CLOCK S_DATA Data Data Data Data Conditions Reset. bits HIGH. Data inputs passed directly divider output divider. TEST mode 000. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divide output divide values latched. Parallel serial input affect shift registers. S_DATA passed directly Divider clocked.
Data Data
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond crystal frequency 16MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs Divider Value Output Frequency (MHz) Minimum Maximum 87.5
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V -0.5V VCCO 0.5V 37.8°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage M0:M8, nP_LOAD, XTAL_SEL Input High Current S_LOAD, S_DATA, S_CLOCK M0:M8, nP_LOAD, XTAL_SEL Input Current S_LOAD, S_DATA, S_CLOCK Output High Voltage; NOTE Output Voltage; NOTE 3.465V 3.465V 3.465V, 3.465V, -150 Test Conditions Minimum Typical -0.3 Maximum Units
NOTE Outputs terminated with VCCO/2.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum 0.95 Units
NOTE Outputs terminated with VCCO
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REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
Fundamental
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input Frequency XTAL; NOTE Test Conditions Minimum Typical Maximum Units
S_CLOCK NOTE ystal frequency range value must achieve minimum maximum frequency range 200MHz 700MHz. Using minimum frequency 10MHz, valid values 511. Using maximum frequency 25MHz, valid values 224.
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol FOUT Parameter Output Frequency Period Jitter, RMS; NOTE Cycle-to-Cycle Jitter; NOTE Output Rise/Fall Time S_DATA S_CLOCK Setup Time S_CLOCK S_LOAD nP_LOAD Hold Time Lock Time S_DATA S_CLOCK nP_LOAD Test Conditions Minimum Typical Maximum Units
tjit(per) tjit(cc)
Output Duty Cycle Parameter Measurement Information section. Characterized using 16MHz XTAL. NOTE This parameter defined accordance with JEDEC Standard NOTE Applications section.
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
nFOUT FOUT
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
nFOUT
VREF
FOUT
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Pulse Width
PERIOD
Reference Point
(Trigger Edge)
Histogram
PERIOD
Mean Period
(First edge after trigger)
PERIOD JITTER
tPERIOD
Clock Outputs
OUTPUT RISE/FALL TIME
84330AV-01
LVPECL
tcycle
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS84330-01 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V FOUT FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
84330AV-01
FIGURE LVPECL OUTPUT TERMINATION
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS84330-01. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS84330-01 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 115mA 398.5mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 30.2mW
Total Power_MAX (3.465V, with outputs switching) 398.5mW 30.2mW 428.7mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 31.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.429W 31.1°C/W 83.3°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
28-PIN PLCC, FORCED CONVECTION
31.1°C/W
Velocity (Linear Feet Minute)
28.3°C/W Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TABLE THERMAL RESISTANCE
28-PIN SOIC, FORCED CONVECTION
60.8°C/W 39.7°C/W
Velocity (Linear Feet Minute)
53.2°C/W 36.8°C/W Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
84330AV-01
REV. FEBRUARY 2003
Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT VOH_MAX VCCO_MAX 1.0V
CCO_MAX
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50] 20.0mW Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW PLCC TABLE
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TABLE JAVS. FLOW SOIC TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2°C/W 46.2°C/W
60.8°C/W 39.7°C/W
53.2°C/W 36.8°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS84330-01 4442
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REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM
Reference Document: JEDEC Publication MS-018
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE 10B. PACKAGE DIMENSIONS
SYMBOL 10.00 0.25 0.40 -0.10 2.05 0.33 0.18 17.70 7.40 1.27 BASIC 10.65 0.75 1.27 Millimeters MINIMUM 2.65 -2.55 0.51 0.32 18.40 7.60 MAXIMUM
Reference Document: JEDEC Publication MS-013, MO-119
84330AV-01
REV. FEBRUARY 2003
ICS84330-01
700MHZ, JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS84330AV-01 ICS84330AV-01 ICS84330AM-01 ICS84330AM-01 Package Lead PLCC Lead PLCC Tape Reel Lead SOIC Lead SOIC Tape Reel Count Tube Tube 1000 Temperature 70°C 70°C 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS84330AV-01 ICS84330AVT-01 ICS84330AM-01 ICS84330AM-01T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 84330AV-01
REV. FEBRUARY 2003
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