CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER F

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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER F

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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
FEATURES
differential 3.3V LVPECL outputs Crystal oscillator interface Output frequency range: 106.25MHz 250MHz Crystal input frequency: 25MHz 25.5MHz Cycle-to-cycle jitter: 40ps (typical) phase jitter 212.5MHz, using 25.5MHz crystal (637KHz 10MHz): 2.69ps Phase noise: Typical 212.5MHz Offset Noise Power 100Hz dBc/Hz 1KHz -110 dBc/Hz 10KHz -120 dBc/Hz 100KHz -122 dBc/Hz 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request
GENERAL DESCRIPTION
ICS84325 Crystal-to-3.3V LVPECL Frequency Synthesizer with Fanout Buffer HiPerClockSmember HiPerClockSfamily High Performance Clock Solutions from ICS. output frequency programmed using frequency select pins. phase noise characteristics ICS84325 make ideal clock source Fibre Channel Fibre Channel Infiniband Gigabit Ethernet applications.
FUNCTION TABLE
Inputs F_SEL1 F_SEL0 25.5MHz 25.5MHz 25MHz 25MHz XTAL Output Frequency F_OUT 106.25MHz 212.5MHz 125MHz 250MHz
BLOCK DIAGRAM
ASSIGNMENT
VCCO F_SEL0 F_SEL1 XTAL1 XTAL2 VCCA PLL_SEL VCCO
XTAL1
XTAL2
Output Divider
Q0:Q5 nQ0:nQ5
Feedback Divider
ICS84325
24-Lead, 300-MIL SOIC 7.5mm 15.33mm 2.3mm body package Package View
F_SEL1 PLL_SEL F_SEL0
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Type Output Output Output Output Output Output Power Power Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output supply pins. Core supply pin. Negative supply pins. Input Power Input Input Input Input Pullup Selects between ystal inputs input dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS LVTTL interface levels. Analog supply pin. ystal oscillator interface. XTAL1 input. XTAL2 output. Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs inver outputs Pulldown high. When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Pulldown Feedback frequency select pin. LVCMOS LVTTL interface levels. Pullup Output select pin. LVCMOS LVTTL interface levels.
TABLE DESCRIPTIONS
Number Name VCCO PLL_SEL VCCA XTAL2, XTAL1 F_SEL1 F_SEL0
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
4.6V -0.5V -0.5V VCCO 0.5V 50°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current PLL_SEL, F_SEL0, F_SEL1 PLL_SEL, F_SEL0, F_SEL1 F_SEL1 PLL_SEL, F_SEL0 F_SEL1 PLL_SEL, F_SEL0 Test Conditions Minimum -0.3 3.465V 3.465V 3.465V, 3.465V, -150 Typical Maximum Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Test Conditions Minimum Typical Maximum 25.5 Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter NOTE Output Skew; NOTE Output Rise/Fall Time Output Duty Cycle Output Pulse Width tPERIOD/2 tPERIOD/2 Test Conditions Minimum Typical Maximum Units
tjit(cc) tsk(o)
Lock Time tLOCK Parameter Measurement Information section. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VCCO/2. NOTE This parameter defined accordance with JEDEC Standard
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE
-100 -110 -120 -130 -140 -150 -160 -170 -180 100k 100M
Source Process Result 10.000 40.000M 212.5M
Start Freq. Stop Freq. Freq. carrier Mode Integral 2.69p Execute
Noise only sec. Plot
25.5MHz Input
Phase Noise Jitter 637K 10MHz 2.69ps (typical)
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA
SCOPE
LVPECL
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD TEST CIRCUIT
OUTPUT SKEW
nQ0:nQ5 Q0:Q5
VREF
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
nQ0:nQ5 Q0:Q5
Pulse Width
PERIOD
PERIOD
tPERIOD
84325EM
tcycle
tcycle
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Period Jitter
Clock Outputs
OUTPUT RISE/FALL TIME
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS84325 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
FOUT FOUT
3.3V
(VOH
FIGURE LVPECL OUTPUT TERMINATION
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FIGURE LVPECL OUTPUT TERMINATION
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
were chosen minimize error. optimum values slightly adjusted different board layouts.
CRYSTAL INPUT INTERFACE
ICS84326 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal
XTAL2 18pF Parallel stal XTAL1
Figure CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure shows schematic example using ICS84325. this example, input 25MHz parallel resonant crystal with load capacitor CL=18pF. frequency fine tuning capacitors 22pF respectively. This example also shows logic control input handling. configuration F_SEL[1:0]=11
therefore output frequency 250MHz. recommended have decouple capacitor power pin. Each decoupling capacitor should located close possible power pin. pass filter clean analog supply should also located close VCCA possible.
VCCA 0.1u 25MHz,18pF
PLL_SEL VCCA XTAL2 XTAL1 F_SEL1 F_SEL0
F_SEL1 F_SEL0
ICS84325 F_SEL1 F_SEL0
VCC=3.3V
(U1,13) (U1,16) 0.1u (U1,24) 0.1u
e.g. F_SEL[1:0]=11 Spare, Installed
0.1u
FIGURE ICS84325 SCHEMATIC EXAMPLE
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following component footprints used this layout example: resistors capacitors size 0603.
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces.
CRYSTAL
crystal should located close possible pins (XTAL1) (XTAL2). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
Signals
VCCA
ICS84325
Pin1
Traces
FIGURE BOARD LAYOUT ICS84325
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS84325. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS84325 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 135mA 468mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 181mW
Total Power_MAX (3.465V, with outputs switching) 468mW 181mW 649mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 43°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.649W 43°C/W 98°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
24-PIN SOIC, FORCED CONVECTION
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 50°C/W
43°C/W
38°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT VOH_MAX VCCO_MAX 1.0V
CCO_MAX
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50) 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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ICS84325
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 50°C/W
43°C/W
38°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS84325 3500
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
SYMBOL 10.00 0.25 0.40 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 Millimeters Minimum 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
Reference Document: JEDEC Publication MS-013, MO-119
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
Marking ICS84325EM ICS84325EM Package Lead SOIC Lead SOIC Tape Reel Count tube 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS84325EM ICS84325EMT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 84325EM
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CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER F

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