HY57V281620HC(L/S)T-I Series Banks 16bits Synchronous DRAM H

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

HY57V281620HC(L/S)T-I Series Banks 16bits Synchronous DRAM H

Datasheet Thumbnail

Top Searches for this datasheet

Part generation
HY57V281620HC(L/S)T-I Series
Banks 16bits Synchronous DRAM
Hynix HY57V281620HC(L/S)T 134,217,728bit CMOS Synchronous DRAM, ideally suited Mobile applications which require power consumption extended temperature range. HY57V281620HC(L/S)T organized 4banks 2,097,152x16 HY57V281620HC(L/S)T offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth. input output voltage levels compatible with LVTTL. Programmable options include length pipeline (Read latency number consecutive read write cycles initiated single control command (Burst length 1,2,4,8, full page), burst count sequence(sequential interleave). burst read write cycles progress terminated burst terminate command interrupted replaced burst read write command cycle. (This pipelined design restricted `2N` rule.)
FEATURES
Single 3.3±0.3V power supply device pins compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm pitch inputs outputs referenced positive edge system clock Data mask function UDQM LDQM Internal four banks operation Auto refresh self refresh 4096 refresh cycles 64ms Programmable Burst Length Burst Type Full page Sequential Burst Interleave Burst Programmable Latency Clocks
ORDERING INFORMATION
Part
HY57V281620HCT-6I HY57V281620HCT-7I HY57V281620HCT-KI HY57V281620HCT-HI HY57V281620HCT-8I HY57V281620HCT-PI HY57V281620HCT-SI HY57V281620HC(L/S)T-6I HY57V281620HC(L/S)T-7I HY57V281620HC(L/S)T-KI HY57V281620HC(L/S)T-HI HY57V281620HC(L/S)T-8I HY57V281620HC(L/S)T-PI HY57V281620HC(L/S)T-SI
Clock Frequency
166MHz 143MHz 133MHz 133MHz 125MHz 100MHz 100MHz 166MHz 143MHz 133MHz 133MHz 125MHz 100MHz 100MHz
Power
Organization
Interface
Package
Normal
4Banks 2Mbits
LVTTL
400mil 54pin TSOP
power
This document general product description subject change without notice. Hynix Semiconductor does assume responsibility circuits described. patent licenses implied. Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
CONFIGURATION
VDDQ VSSQ VDDQ VSSQ LDQM /CAS /RAS A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ UDQM
54pin TSOP 400mil 875mil 0.8mm pitch
BA0, Clock Clock Enable Chip Select Bank Address Address Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground Connection NAME DESCRIPTION system clock input. other inputs registered SDRAM rising edge Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh Enables disables inputs except CLK, CKE, UDQM LDQM Selects bank activated during activity Selects bank read/written during activity Address RA11, Column Address Auto-precharge flag RAS, define operation Refer function truth table details Controls output buffers read mode masks input data write mode Multiplexed data input output Power supply internal circuits input buffers Power supply output buffers connection
RAS, CAS, UDQM, LDQM DQ15 VDD/VSS VDDQ/VSSQ
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
FUNCTIONAL BLOCK DIAGRAM
2Mbit 4banks Synchronous DRAM
Self refresh logic timer
Internal counter
active
2Mx16 Bank Decoders 2Mx16 Bank decoders decoders 2Mx16 Bank 2Mx16 Bank decoders Buffer Logic Sense Gate
UDQM LDQM
State Machine Address buffers
decoders
refresh
Column Active
Memory Cell Array
Column Decoders decoders
DQ14 DQ15
Bank Select
Column Counter
Address Registers Burst Counter
Mode Registers
Latency
Data Control
Pipe Line Control
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDD, VDDQ TSOLDER Symbol -1.0 -1.0 Rating Unit
Note Operation above absolute maximum rating adversely affect device reliability.
OPERATING CONDITION (TA= 85°C)
Parameter Power Supply Voltage Input High voltage Input voltage Symbol VDD, VDDQ -0.3 VDDQ Unit Note
Note 1.All voltages referenced 2.VIH(max) acceptable 5.6V pulse width with <=3ns duration. 3.VIL(min) acceptable -2.0V pulse width with <=3ns duration.
OPERATING TEST CONDITION (TA= 85°C, VDD=3.3±0.3V, VSS=0V)
Parameter Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement Symbol Vtrip Voutref Value 2.4/0.4 Unit Note
Note 1.Output load measure access times equivalent gates capacitor (50pF). details, refer AC/DC output load circuit
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
CAPACITANCE (TA=25°C, f=1MHz)
-6I/KI/HI Parameter Symbol Input capacitance A11, BA0, BA1, CKE, RAS, CAS, UDQM, LDQM Data input output capacitance DQ15 CI/O -8I/PI/SI Unit
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output 50pF
Output
50pF
Output Load Circuit
Output Load Circuit
CHARACTERISTICS (TA= 85°C, VDD=3.3±0.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Symbol Min. Unit Note -2mA +2mA
Note 1.VIN 3.6V, other pins tested under 2.DOUT disabled, VOUT=0
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
CHARACTERISTICS (TA= 85°C, VDD=3.3±0.3V, VSS=0V)
Speed Parameter Symbol Test Condition Operating Current Precharge Standby Current Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current Power Down Mode IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Burst length=1, bank active tRC(min), IOL=0mA VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 30ns. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 30ns. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active CL=3 CL=2
Unit
Note
IDD4 IDD5
tRRC tRRC(min), banks active
Self Refresh Current
IDD6
0.2V
Note 1.IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open 2.Min. tRRC (Refresh cycle time) shown CHARACTERISTICS
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Symbol System Clock Cycle Time Latency Latency tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH tOLZ tOHZ3 tOHZ2 1000 1000 1000 1000 1000 1000 1000 Latency Unit Note
Clock High Pulse Width Clock Pulse Width Access Time From Clock Latency
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time Data Output Low-Z Time Data Output High-Z Time Latency Latency
Note 1.Assume (input rise fall time 1ns, then [(tR+tF)/2-1]ns should added parameter 2.Access times measured with input signals 1v/ns edge rate, from 0.8v 2.0v 1ns, then (tR/2-0.5)ns should added parameter
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
CHARACTERISTICS
Parameter Symbol Operation Cycle Time Auto Refresh Delay Active Time Precharge Time Bank Active Delay Delay Write Command Data-In Delay Data-In Precharge Command Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Output Hi-Z Latency Latency tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 100K 100K 100K 100K 100K 100K 100K Unit Note
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note command given tRRC after self refresh exit
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
DEVICE OPERATING OPTION TABLE
HY57V281620HC(L/S)T-6I
Latency 166MHz(6ns) 143MHz(7ns) 133MHz(7.5ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 6CLKs 6CLKs 10CLKs 9CLKs 9CLKs 3CLKs 3CLKs 3CLKs 5.4ns 5.4ns 5.4ns 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-7I
Latency 143MHz(7ns) 133MHz(7.5ns) 125MHz(8ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 7CLKs 10CLKs 10CLKs 10CLKs 3CLKs 3CLKs 3CLKs 5.4ns 5.4ns 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-KI
Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 2CLKs 3CLKs 2CLKs tRCD 2CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 8CLKs 9CLKs 7CLKs 2CLKs 3CLKs 2CLKs 5.4ns 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-HI
Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 9CLKs 9CLKs 7CLKs 3CLKs 3CLKs 2CLKs 5.4ns 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-8I
Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 2CLKs 2CLKs tRCD 3CLKs 2CLKs 2CLKs tRAS 6CLKs 5CLKs 4CLKs 9CLKs 7CLKs 6CLKs 3CLKs 2CLKs 2CLKs 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-PI
Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs 7CLKs 7CLKs 6CLKs 2CLKs 2CLKs 2CLKs 2.0ns 2.0ns 2.0ns
HY57V281620HC(L/S)T-SI
Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs 7CLKs 7CLKs 6CLKs 2CLKs 2CLKs 2CLKs 2.0ns 2.0ns 2.0ns
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Burst Stop Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit Entry Precharge power down Exit Clock Suspend Entry Exit High (Other Pins code)
CKEn-1
CKEn
ADDR
A10/ code
Note
Note Exiting Self Refresh occurs asynchronously bringing from high Dont care, Logic High, Logic Low. =Bank Address, Address, Column Address, Opcode Operand Code, Operation burst read sigle write mode entered programming write burst mode (A9) mode register logic
Rev. 1.0/Mar.
HY57V281620HC(L/S)T-I
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 10.262(0.4040) 10.058(0.3960) 1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 1.0/Mar.

HY57V281620HC(L/S)T-I Series Banks 16bits Synchronous DRAM H

Top Searches for this datasheet

Other recent searches