CB-C7, 3-VOLT 0.8-MICRON CELL-BASED CMOS ASIC October 1993 F
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CB-C7, 3-volt cell-based product family intended power portables battery-operated products. power reduction percent possible compared with CB-C7, 5-volt. CB-C7, 3-volt manufactured with 0.8-micron (drawn) process with twoor three-layer metalization offered ring sizes. Typical applications include handheld terminals, personal digital office assistants, word spellers, cellular phones variety high-volume, portable PC-based applications. family allows designing complex logic functions, 237,000 usable gates user-defined logic. Megamacro blocks include industry-standard cores, peripherals, analog functions thus enabling complete system-on-a-chip solutions. CB-C7 series consists types architectures, Fast Turn FT-type embedded array High Density HDtype full standard cell. FT-type uses fully-diffused standard cell embedded cores with sea-of-gates userdefinable logic. solution offers gate-array-like turnaround times while allowing incorporation large embedded functions. Another important advantage that FT-type well-suited multiple designs built around common embedded function, such V30HL (8086) CPU. HD-type comprised fully-diffused standard cell architecture both embedded cores userdefined logic area. This solution offers optimal size economic cost-effective volume production. Full gate delay models available both Verilog®, golden simulator, part NEC's OpenCAD® Design System.
CB-C7, 3-VOLT 0.8-MICRON CELL-BASED CMOS ASIC
October 1993
Figure Integrated Solution with CB-C7 Cell-Based ASIC Embedded Megafunctions
Digital Megamacros Library
Compatible Device 8088 8086 80C42 8237A 8251A 8254 8255A 8259A 4991A 72020 Code V20HL (NA70108H) V30HL (NA70116H) NA70008A NA80C42H NA71037 NA71051 NA71054 NA71055 NA71059 NA4991A NA72020 8-bit 16-bit Z808-bit Keyboard Controller Programmable Controller Serial Communications Controller Interval Timer Peripheral Interface Interrupt Controller Real Time Clock Graphics Display Controller
Features
voltage cell-based library means power savings over solutions µW/gate power dissipation Standby current IDDQ Advanced drawn gate (0.6 Leff) length CMOS technology with three-layer metalizations 237,000 usable gates 3-layer full standard cell product with I/Os pitch Extensive embedded core library includes CPU, analog, video functions Datapath compiler available multipliers, FIFOs, register files Supports leading third-party design tools
Analog Megamacros Library
Code XXXA AADA8GPC AACP25NA AACP80NA AACP01UA AAOP10MA AAOP01MA AASWGPCA AASWGPTA Description triple 8-bit video 8-bit general-purpose High-speed (25ns) comparator High-speed (80ns) comparator General-purpose comparator High-speed operational amplifier General-purpose operative amplifier Analog switch with control Analog switch with control
Note: Some analog functions currently development
70195
CB-C7/3V
OpenCAD Design System
CB-C7 supported OpenCAD Design System, ASIC design environment that merges best today's most powerful ASIC software design tools proprietary tools, such floorplanner module compilers, into single environment. Sample design kits available charge qualified users: contact ASIC Design Center nearest more information. software license agreement required. table compilable ROM, shown page describes three different ratios along with minimum maximum size. 16:1 MUX, minimum word depth minimum width word depth increase words increments width increase maximum bits. other configurations determined same fashion. Typical examples applications containing digital memory analog cores their step size shown Figure
Digital Megafunctions
addition V30HL/V20HL 8086, 8088 product families support peripherals, offers complex standard functions well converters multimedia applications. Compiled also available satisfy myriad different product applications.
Operation
CB-C7 CMOS ideal power, high volume, battery-operated products. CB-C7 process been recharacterized operate voltage levels, 10%. only have macrocells been recharacterized operate lower voltage, complex megamacros compiled memory well.
Analog Blocks
building upon expertise analog standard offering select members analog family analog megamacros. These megamacros layed area maximize area core digital functions user-defined logic. This separation analog digital functions separate analog line also contributes better noise isolation. Digital analog functions CB-C7 cell-based array tested separately.
Figure Typical Application Example (See Table
Compiled
Compiled
Test Emulation Architecture
test emulation architecture used CB-C7 design methodology approach testing emulation embedded functions. allows emulation production chip system validation, reuse test circuit standard micro functional test vectors system vectors modularized fashion. also provides real-time emulation support test structure allows testing on-chip RAM/ROM analog blocks.
Megafunction
Core
User-Defined Logic
Analog
On-Chip Compiled Memory
blocks custom compiled CB-C7 design environment. compiler allows ASIC designers generate silicon-efficient memory blocks specific size performance suit exact system requirements quickly efficiently.
Trademarks
OpenCAD registered trademark Electronics TMZ80 trademark Zilog, Inc. Verilog registered trademark Cadence Design System, Inc. TMMACRObus trademark
CB-C7/3V
Table CB-C7 Step Sizes Usable Gate Count
Step Size I/O1 Total Grids 35,400 49,600 66,600 86,000 107,700 131,800 158,300 172,500 202,700 235,800 270,800 307,800 348,300 390,700 435,500 482,100 531,700 583,800 662,900 720,900 781,300 907,800 HD-Type Usable Gates2 2-Layer Metal 3-Layer Metal 5,930 8,840 12,390 16,530 21,150 26,460 32,230 35,390 42,160 49,360 57,290 65,810 74,730 84,410 94,480 105,330 116,770 128,550 147,680 160,890 174,960 204,550 7,040 10,430 14,560 19,370 24,740 30,900 37,590 41,260 49,100 57,440 66,630 76,500 86,820 98,030 109,680 122,240 135,470 149,100 171,230 186,510 202,780 236,990 FT-Type Usable Gates2 2-Layer Metal 3-Layer Metal 3,140 4,720 6,660 8,910 11,440 14,340 17,490 19,230 22,930 26,870 31,220 35,890 40,780 46,100 51,620 57,580 63,860 70,330 80,830 88,090 95,820 112,070 3,860 5,760 8,070 10,760 13,780 17,230 20,990 23,050 27,450 32,140 37,300 42,850 48,660 54,970 61,520 68,590 76,040 83,710 96,170 104,770 113,930 133,200
Notes:
configured VDD/GND Usable gates: equivalent estimated 2-input NAND, will vary depedning pecific design 2-layer metal 3-layer metal Grid/gate ratio* utilization routing utilization routing grid/gate ratio utilization routing utilization routing
Grid gate ratio based conversion from other libraries will different. Contact Design Center size estimation Based CMOS-6 L302 cell equivalents
Table Examples Core (Refer Figure
Application Cellular Phone Wireless Hard Disk Drive Core V20HL V20HL 71054 71059 Triple Video bits bits bits UDL* 40,000 10,000 3,000 Step Size Metalization Package TQFP TQFP TQFP
Graphics Controller Document Scanner
40,000 3,000
PQFP
User-Defined Logic; measured 2-input NAND gate equivalents CMOS-6 family
CB-C7/3V
Table Compilable RAM, Datapath Elements CB-C7
Compiled SRAM
Single port, asynchronous operation Size 16:1 Column Column Column Size Increment words, words, words, Column
Compiled Dual Port
Dual port, asynchronous operation Speed: 43ns (typ) (512W bit) Size Size Increment words,
Compiled
Single port, asynchronous operation Speed: 63ns (typ) (512W bit) Size 32:1 Column Size Increment words, words, words, bits
Compiled High-Speed SRAM
Single port, asynchronous high speed operation Speed: 12.6ns (typ) (512W bit) Size Column Size Increment words,
Example: column minimum size Increments thus words max. size mimimum bit, time increments bits max.
16:1 Column
Column Please check with Design Center exact specifications availability. Examples Compiled High-Speed SRAM: column MUX, minimum size Increments thus words max. size minimum bit, time increments bits max. Multiplier Register File FIFO
Datapath Modules
Size Size Increment bits words, words,
CB-C7/3V
Absolute Maximum Ratings
Power supply voltage, Input/output voltage, Output current, (min) (typ) (min) (typ) (min) (typ) Operating temperature, TOPT Storage temperature, TSTG +85°C +150°C -0.5 +6.5 -0.5
Input/Output Capacitance
Terminal Input Output Symbol COUT CI/O Unit
Note: Values include package capacitance.
Power Consumption
Description Internal cell (L302) Limits (max) Unit µW/MHz Test Conditions
Caution: Exposure absolute maximum ratings extended periods affect device reliability; exceeding ratings could cause permanent damage. device should operated outside recommended operating conditions.
Recommended Operating Conditions
Parameter Power supply voltage Ambient temperature Input voltage High-level input voltage Low-level input voltage Input rise fall time (normal input) Input rise fall time (Schmitt-trigger input) Positive Schmitt-trigger voltage Negative Schmitt-trigger voltage Hysteresis voltage Symbol Unit
Note: rise/fall time given Schmitt-trigger input buffer varies depending operating environment. Simultaneous switching output buffers should analyzed before deciding Schmitt-trigger input buffer.
Characteristics
10%; +85°C Parameter Internal toggle frequency Delay time, 2-input NAND Gate* Standard gate (F302) HD-type Standard gate (F302) HD-type power gate (L302) HD-type power gate (L302) HD-type Delay time, Buffer Input buffer (FI01) Output buffer (FO01) Rise Fall Times Output rise time (FO01) Input fall time (FO01) With L101 load IOH= -2mA 4800 (HL) (HL) (HL) 1310 (HL) Symbol fTOG Unit Conditions -F/F;
CB-C7/3V
Characteristics
10%; +85°C Parameter Static current (Note Input leakage current Normal input pull-up pull-up pull-down Off-state output leakage current Normal Input pull-up pull-up pull-down Low-level output voltage (CMOS) High-level output voltage -0.4 -0.4 -0.4 2.2mA -1.1mA -2.2mA -3.3mA Symbol Unit Conditions
Notes: maximum value reflects pull-up/pull-down resistors oscillator blocks. Contact ASIC Design Center assistance calculation. CMOS-level output buffer (VDD 10%, -40°C +85°C)
CB-C7/3V
Table Package Options
Ring Step Sizes Package Type Plastic Quad Flatpack (QFP) 44-pin (0.8 lead pitch) 52-pin lead pitch) 64-pin lead pitch) 80-pin (0.8 lead pitch) 100-pin (0.65 lead pitch) 120-pin (0.8 lead pitch) 136-pin (0.65 lead pitch) 160-pin (0.65 lead pitch) 1601-pin (0.65 lead pitch) 1602-pin (0.65 lead pitch) Plastic Quad Flatpack (QFP-FP) 100-pin (0.5 lead pitch) 120-pin (0.5 lead pitch) 144-pin (0.5 lead pitch) 160-pin (0.5 lead pitch) 1602-pin (0.5 lead pitch) 176-pin (0.5 lead pitch) 1761-pin (0.5 lead pitch) 1762-pin (0.5 lead pitch) 208-pin (0.5 lead pitch) Thin Plastic Quad Flatpack (TQFP) 64-pin (0.5 lead pitch) 80-pin (0.5 lead pitch) 1001-pin (0.5 lead pitch)
Plastic Leaded Chip Carrier (PLCC) 68-pin mils lead pitch) 84-pin mils lead pitch) lead frame lead frame heat sink
Available under development Unavailable
Note: reserves right alter these package options based results qualification. Each cell-based design/package combination must cleared manufacturing suitability. latest package availability CB-C7, please contact your local ASIC Design Center.
Typical CB-C7 Package Marking
CB-C7 Numbering System
Part Number µPD93XXX Description Contains logic only logic plus and/or Contains same µPD93XXX with code change Same µPD93XXX contains megamacro blocks, such 710XXX V20HL/V30HL Same µPD95XXX with code change
JAPAN
µPD94XXX µPD95XXX
NEC: Company Mark JAPAN: Origin D93000: Part Number Package Code 9115K1: Number Number Index
83NR-7687A
D93000
9115K1
µPD96XXX
CB-C7/3V
Table Package Options (Cont'd)
Ring Step Size Package Type Plastic Quad Flatpack (QFP) 64-pin lead pitch) 80-pin (0.8 lead pitch) 100-pin (0.65 lead pitch) 120-pin (0.8 lead pitch) 136-pin (0.65 lead pitch) 160-pin (0.65 lead pitch) 1601-pin (0.65 lead pitch) 1602-pin (0.65 lead pitch) 1841-pin (0.65 lead pitch) Plastic Quad Flatpack (QFP-FP) 100-pin (0.5 lead pitch) 120-pin (0.5 lead pitch) 144-pin (0.5 lead pitch) 160-pin (0.5 lead pitch) 1602-pin (0.5 lead pitch) 176-pin (0.5 lead pitch) 1761-pin (0.5 lead pitch) 1762-pin (0.5 lead pitch) 208-pin (0.5 lead pitch) 2081-pin (0.5 lead pitch) 2082-pin (0.5 lead pitch) 2401-pin (0.5 lead pitch) 2561-pin (0.4 lead pitch) 2721-pin (0.5 lead pitch) 3041-pin (0.5 lead pitch) lead frame lead frame heat sink
Available under development Unavailable
Note: reserves right alter these package options based results qualification. Each cell-based design/package combination must cleared manufacturing suitability. latest package availability CB-C7, please contact your local ASIC Design Center.
Figure Popular CB-C7 Package 100-pin TQFP Body Size
Enlarged detail lead
83CL-8904B (8/92)
±0.1
0.125 0.05 0.10 1.25
CB-C7/3V
NEC's ASIC Design System
supports ASIC products with comprehensive system that significantly reduces time expense usually associated with development semi-custom devices. NEC's OpenCAD Design System front-end back-end ASIC design package that merges several advanced CAE/CAD tools into single structure. design flow combines tools floorplanning, logic synthesis, automatic test generation, accelerated fault-grading, full timing simulation, advanced place-and-route algorithms. RAM/ROM Datapath Compilers also available CB-C7 designs. top-down modeling methodology possible means specification. Designers concentrate their design effort higher level abstraction, specifying, modeling, simulating their designs systems level. This leaves details gate-level implementation synthesis tools. After having verified proper functionality, designers free explore functional architectural trade-offs, optimize chip performance while minimizing chip area. engineer evaluate several architectures select best solution before committing silicon. design flow shown below. benefits ASIC design flow that sign-off simulation accomplished customer's site since offers designers choice simulators with "golden simulator" status. Golden simulator status means that after receiving post place-and-route simulation results from customer, proceed directly photomask production, bypassing additional post-simulation steps. simplify simulation testing embedded cores megamacros, full Verilog gate delay models provided megamacros. megamacros then fully tested with standard production test vectors. floorplanner tool provides realistic estimate wire length grouping hierarchical blocks specific physical location chip. This allows more accurate simulation results minimizing critical path interconnect delays. floorplanner also allows placement fully-diffused functions such memory
Figure CB-C7 HDL-Based Design Flow
CUSTOMER
Behavioral Sim.
Logic Synthesis
Netlist
EDIF 2.0.0 Netlist Place Route
Sim.
Delay Calculator
Floorplanner
Simulator Test Vector
Post Sim.
Timing Analyzer Fault Simulation
Option
Changed Netlist
Fabrication
Test Vector Output ATPG Test Vector
ATPRG
Test Program
Tester
CB-C7/3V
microprocessors. Graphical assignment available with floorplanner. floorplanner generates delay file post-floorplanner simulation, shown design flow. option allows designer make minor corrections design without requiring entirely placement routing device. tool ensures that relatively small changes, such connectivity changes, will greatly impact timing current design. This vastly improve turnaround time design. also incorporates proprietary tools facilitate design process. single delay calculator used platforms ensure consistent timing simulation results. comprehensive design rule check, DRC, program reports design rule violations well chip utilization statistics design netlist. generated report contains information such cell count usage rate well total counts. Unused input pins, violations naming conventions, exceeded fan-out limits examples design rule violations reported this program. Sample design kits available charge qualified users: Contact ASIC design center more information. NEC's ASIC Design Centers listed back this data sheet. software license agreement required.
CB-C7/3V
Cell Library List
CB-C7 standard cell library offers variety blocks, macrocells megafunctions. library elements shown include gates, flip-flop circuits, shift registers. names functions these blocks designed compatible with those CMOS-7 CMOS-6 families.
Block Name
Area1 (grids)
Function Blocks Normal Power (Cont)
Gates F202 F203 F204 F208 F222 F223 F224 Gates 2-input 3-input 4-input 8-input 2-input NOR, power 3-input NOR, power 4-input NOR, power 12/7 16/10 24/18 16/9 24/13 32/17
Block List
Block Name Description Area (mA) (grids)
Interface Blocks
Input Buffers FI01 Input buffer, CMOS 12/6
Output Buffers FO01 FO02 FO03 B007 Output buffer, CMOS Output buffer, CMOS Output buffer, CMOS Output buffer, CMOS 3-state 16/9 16/9 24/15
F212 F213 F214 F232 F233 F234
2-input 3-input 4-input 2-input power 3-input power 4-input power
12/6 12/7 12/7 16/8 16/9
NAND Gates F302 F303 F304 F305 F306 F308 F322 F323 F324 2-input NAND 3-input NAND 4-input NAND 5-input NAND 6-input NAND 8-input NAND 2-input NAND, power 3-input NAND, power 4-input NAND, power 12/7 16/9 20/11 20/12 24/14 16/9 24/13 32/17
Open Drain Output Buffers EXT1 Output buffer, N-ch open drain
Bi-directional Buffers B001 buffer, CMOS CMOS 3-state pull-up res. 36/21
Gates F312 F313 F314 F332 F333 F334 2-input 3-input 4-input 2-input AND, power 3-input AND, power 4-input AND, power 12/6 12/7 12/7 16/8 16/9
Function Blocks Normal Power
Inverters F101 F102 F103SD F104SD F108SD Buffers F111 F112 F113SD F114SD F118SD Delays F131 F132 Delay gate Delay gate 24/13 40/22 Non-inverting buffer (F/O (FT) Non-inverting buffer (F/O (FT) Non-inverting buffer Non-inverting buffer Non-inverting buffer 12/7 Inverter (F/O (FT) Inverter (F/O (FT) Inverter (x3) Inverter (x4) Inverter (x5)
AND-NOR Gates F421 F422 F423 F424 F425 F426 F429 F442 F462 2-wide 1-2-input AND-OR inverter 3-wide 1-1-2-input AND-OR inverter 2-wide 1-3-input AND-OR inverter 2-wide 2-2-input AND-OR inverter 3-wide 2-2-2-input AND-OR inverter 2-wide 3-3-input AND-OR inverter 4-wide 2-2-2-2-input AND-OR inverter 2-wide input AND-OR inverter 3-wide 1-2-3 input AND-OR inverter 12/7 16/10 16/9 16/9 24/14 24/13 32/18 32/17 24/14
Note (1): Grids shown FT/HD types respectively; indicates
CB-C7/3V
Area1 (grids) Area1 (grids)
Block Name
Block Name
Function Blocks Normal Power (Cont)
OR-NAND Gates F431 F432 F433 F434 F435 F436 F454 2-wide 1-2-input OR-AND inverter 3-wide 1-1-2-input OR-AND inverter 2-wide 1-3-input OR-AND inverter 2-wide 2-2-input OR-AND inverter 2-wide 2-3-input OR-AND inverter 2-wide 3-3-input OR-AND inverter 4-wide 2-2-2-2-input OR-AND inverter 12/7 16/10 16/9 16/9 20/11 24/13 32/18
Function Blocks Normal Power (Cont)
Latches (Cont) F604 F605 F901 F902 Flip-Flops F596 F611 F614 F617 F631 F637 F641 F644 F647 F661 F667 F714 F717 F737 F744 F747 F767 F771 F774 F777 F781 F787 F791 F792 F922 F924 F615 F616 S999 Counters 72/46 36/27 20/16 76/35 F961 F962 4-bit synchronous binary counter with Reset low, buffered 4-bit synchronous binary counter with Reset 240/158 152/102 Synchronous with Set-Reset D-F/F D-F/F with Set-Reset D-F/F with Set-Reset D-F/F D-F/F with Set-Reset D-F/F, buffered D-F/F with Set-Reset, buffered D-F/F with Set-Reset low, buffered D-F/F low, buffered D-F/F with Set-Reset low, buffered Toggle with Set-Reset Toggle with Set-Reset Toggle with Set-Reset Toggle with Set-Reset, buffered Toggle with Set-Reset low, buffered Toggle with Set-Reset low, buffered F/F, buffered with Set-Reset, buffered with Set-Reset low, buffered low, buffered with Set-Reset low, buffered Toggle with Set-Reset Toggle Enable Toggle with Set-Reset Toggle Enable 4-bit D-F/F with Reset 4-bit D-F/F D-F/F with D-F/F with 2-to-1 Data Slector (Scan path) 44/28 32/18 40/24 40/24 32/18 40/24 32/22 40/28 40/28 32/22 40/28 36/23 36/23 36/23 36/27 36/27 36/27 40/24 48/30 48/30 40/24 48/30 48/30 48/30 136/75 112/61 -/21 -/22 -/10 D-latch with driver D-latch with low, Reset 4-bit D-latch 8-bit D-latch 24/14 28/16 80/45 152/85
Parity Generators F581 F582 8-bit parity generator 8-bit even parity generator 76/48 76/48
EX-OR Gate F511 Exclusive-OR 16/9
EX-NOR Gate F512 Adders F521 F523 Buffers F531 F532 F533 Decoders F561 F981 F982 2-to-4 decoder 2-to-4 decoder with Enable 3-to-8 decoder with Enable 40/24 52/31 104/60 3-state buffer with Enable 3-state buffer with Enable 3-state buffer 20/11 20/11 36/14 1-bit full-adder 4-bit binary full-adder 36/24 128/89 Exclusive-NOR 16/9
Shift Registers F911 F912 F913 F914 4-bit shift register with Reset 4-bit serial/parallel shift register 4-bit parallel shift register with Reset low, Load 4-bit shift register 136/75 144/80 160/92 112/61
Multiplexers L655 F569 F570 F571 F572 Latches F595 F601 F602 F603 latch D-latch D-latch with Reset D-latch with Reset 20/14 24/14 24/15 28/16 2-to-1 multiplexer enable/low drive) 8-to-1 multiplexer 4-to-1 multiplexer 2-to-1 multiplexer Quad 2-to-1 multiplexer
Comparator F985 4-bit magnitude comparator 128/82
Miscellaneous F091 level Generator
Note (1): Grids shown FT/HD types respectively.
CB-C7/3V
Area1 (grids) Area1 (grids)
Block Name
Block Name
Function Blocks Power
Inverters L101 Buffers L111 Non-inverting buffer (F/O (FT) (F/O (FT)
Function Blocks Power (Cont)
Exclusive-OR L511 EX-OR 12/8
Exclusive-NOR L512 Decoder L561 L981 L982 2-to-4 Decoder 2-to-4 Decoder with Enable 3-to-8 Decoder with Enable 24/17 68/42 68/42 EX-NOR 12/8
Gates L202 L203 L204 Gates L212 L213 L214 2-input 3-input 4-input 12/6 2-input 3-input 4-input
Multiplexer L571 L572 Latches 12/6 L901 L902 4-Bit Latch 8-Bit Latch 48/33 88/61 2-to-1 Multiplexer Quad 2-to-1 Multiplexer 16/10 40/27
NAND Gates L302 L303 L304 L305 L306 Gates L312 L313 L314 2-Input 3-Input 4-Input 12/6 2-Input NAND 3-Input NAND 4-Input NAND 5-Input NAND 6-Input NAND
Shift Registers L911 L912 L913 Flip Flops L922 L924 4-Bit D-F/F with Reset 4-Bit D-F/F 104/63 80/49 4-Bit Shift Register with Reset 4-Bit Serial/Parallel Shift Register 4-Bit Parallel Shift Register with Reset 104/60 112/60 128/80
AND-NOR Gates L421 L422 L423 L424 L425 L426 L429 L442 L462 2-Wide, 1-2-Input AND-OR Inverter 3-Wide 1-1-2-Input AND-OR Inverter 2-Wide, 1-3-Input AND-OR Inverter 2-Wide, 2-2-Input AND-OR Inverter 3-Wide, 2-2-2-Input AND-OR Inverter 2-Wide, 3-3-Input AND-OR Inverter 4-Wide, 2-2-2-2-Input AND-OR Inverter 2-Wide, 4-4-Input AND-OR Inverter 3-Wide, 1-2-3-Input AND-OR Inverter 12/8 12/7 16/10 12/9 12/8
Megafunctions 70108H 70116H 78350 70008A 72065B 71037 71051 71054 71055 71059 71088 4991A V20HL 8-bit Microprocessor V30HL 16-bit Microprocessor 78K3 16-bit Microprocessor 8-bit Microprocessor Floppy Disk Controller 8237A Programmable Controller 8251A USART 8254 Interval Timer 8255A Peripheral Interface 8259A Interrupt Controller 8288 System Controller Real Time Clock 78,580 31,780 17,750 16,170 9540 7510
OR-NAND Gates L431 L432 L433 2-Wide, 1-2-Input OR-AND Inverter 3-Wide, 1-1-2-Input OR-AND Inverter 2-Wide, 1-3-Input OR-AND Inverter
OR-AND Gates L434 L435 L436 L454 2-Wide, 2-2-Input OR-AND Inverter 2-Wide, 2-3-Input OR-AND Inverter 2-Wide, 3-3-Input OR-AND Inverter 4-Wide, 2-2-2-2-Input OR-AND Inverter 12/6 12/7 16/10
Note (1): Grids shown FT/HD types respectively.
CB-C7/3V
Notes:
CB-C7/3V
Notes:
CB-C7/3V
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THIRD-PARTY DESIGN CENTERS
SOUTH CENTRAL/SOUTHEAST
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Document 70195
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