DCP02 Series SBVS011E MARCH 2000 REVISED AUGUST 2006 Miniatu
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DCP02 Series
SBVS011E MARCH 2000 REVISED AUGUST 2006
Miniature, Isolated UNREGULATED DC/DC CONVERTERS
FEATURES
Efficiency Thermal Protection Device-to-Device Synchronization SO-28 Power Density 106W/in3 (6.5W/cm3 EN55022 Class Performance UL1950 Recognized Component JEDEC 14-Pin SO-28 Packages
DESCRIPTION
DCP02 series family isolated, unregulated DC/DC converters. Requiring minimum external components including on-chip device protection, DCP02 series provides extra features such output disable synchronization switching frequencies. highly integrated package design results highly reliable products with power densities 79W/in3 (4.8W/cm3) DIP-14, 106W/in3 (6.5W/cm3) SO-28. This combination features small size makes DCP02 suitable wide range applications.
APPLICATIONS
Point-of-Use Power Conversion Ground Loop Elimination Data Acquisition Industrial Control Instrumentation Test Equipment
800kHz Oscillator
Divide-by-2 Reset
VOUT Power Stage
SYNC/DISABLE
Watchdog/ Startup
Thermal Shutdown Power Controller
IBIAS
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2000-2006, Texas Instruments Incorporated
DCP02 Series
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SBVS011E MARCH 2000 REVISED AUGUST 2006
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ORDERING INFORMATION
most current package ordering information, Package Option Addendum this data sheet, website www.ti.com. Supplemental Ordering Information
DCP02 Basic Model Number: Product Voltage Input: Voltage Output: Dual Output: Package Code: DIP-14 SO-28
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
input models Input Voltage input models input models input models Storage temperature range
DCP02 Series +125
UNIT
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
+25°C, unless otherwise noted.
PARAMETER OUTPUT Power Ripple INPUT Voltage range ISOLATION Voltage LINE Regulation %/1% Flash test test, UL1950 kVrms kVrms 100% full load capacitor 1µF, load mVPP TEST CONDITIONS UNIT
During UL1950 recognition tests only.
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ELECTRICAL CHARACTERISTICS (continued)
+25°C, unless otherwise noted.
PARAMETER SWITCHING/SYNCHRONIZATION Oscillator frequency (fOSC) Sync input Sync input current Disable time Capacitance loading SYNC RELIABILITY Demonstrated THERMAL SHUTDOWN temperature shutdown Shutdown current TEMPERATURE RANGE Operating +150 +55°C FITS External VSYNC Switching frequency fOSC/2 TEST CONDITIONS UNIT
ELECTRICAL CHARACTERISTICS DEVICE
+25°C, unless otherwise noted.
INPUT VOLTAGE PRODUCT DCP020503P, DCP020505P, DCP020507P, DCP020509P, DCP020512P DCP020512DP DCP020515DP, DCP020518DP DCP021205P, DCP021212P, DCP021212DP, DCP021215DP DCP021515P, DCP022405P DCP022405U DCP022405DP, DCP022412DP DCP022415DP, DCP022418DP 10.8 10.8 10.8 10.8 13.5 21.6 21.6 21.6 21.6 21.6 21.6 13.2 13.2 13.2 13.2 16.5 26.4 26.4 26.4 26.4 26.4 26.4 3.13 4.75 6.65 8.55 11.4 ±11.4 ±14.25 ±17.1 4.75 11.4 ±11.4 ±14.25 14.25 4.85 4.75 ±4.75 ±11.4 ±14.25 ±17.1 OUTPUT VOLTAGE VNOM LOAD 3.46 5.25 7.35 9.45 12.6 ±12.6 ±15.75 ±18.9 5.25 12.6 ±12.6 ±15.75 15.75 5.35 5.25 +5.25 ±12.6 ±15.75 ±18.9 100% LOAD LOAD REGULATION LOAD CURRENT (mA) LOAD 100% LOAD EFFICIENCY BARRIER CAPACITANCE (pF) CISO VISO 750Vrms
100% load current 2W/VNOM typ.
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DCP02 Series
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DEVICE INFORMATION
PACKAGE DIP-14 (Single-DIP) (Top View)
SYNC
PACKAGE DIP-14 (Dual-DIP) (Top View)
SYNC
DCP02 +VOUT -VOUT +VOUT
DCP0
Table Description (Single-DIP)
TERMINAL NAME +VOUT SYNC DESCRIPTION Voltage input Input side common Output side common +Voltage connected Synchronization
Table TERMINAL FUNCTIONS (Dual-DIP)
TERMINAL NAME +VOUT -VOUT SYNC DESCRIPTION Voltage input Input side common Output side common +Voltage -Voltage connected Synchronization
PACKAGE SO-28 (Single-SO) (Top View)
DCP02 SYNC
PACKAGE SO-28 (Dual-SO) (Top View)
DCP02 SYNC
+VOUT
+VOUT -VOUT
Table TERMINAL FUNCTIONS (Single-SO)
TERMINAL NAME +VOUT SYNC DESCRIPTION Voltage input Input side common Input side common Output side common +Voltage connected Synchronization NAME +VOUT -VOUT SYNC
Table TERMINAL FUNCTIONS (Dual-SO)
TERMINAL DESCRIPTION Voltage input Input side common Input side common Output side common +Voltage -Voltage connected Synchronization
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TYPICAL CHARACTERISTICS
+25°C, unless otherwise noted.
DCP020505P CONDUCTED EMISSIONS (500mA Load)
5.04 5.02 5.00
DCP020505P VOUT TEMPERATURE (75% Load)
Emission Level, Peak (dBmA)
VOUT
0.15
4.98 4.96 4.94 4.92 4.90
Frequency (MHz)
Temperature (°C)
Figure DCP021205P VOUT LOAD
Figure DCP021205P POWER TEMPERATURE (400mA Load)
POUT
Load
VOUT
Temperature (°C)
Figure DCP0212 EFFICIENCY LOAD
DCP1212DP DCP1205P
Figure DCP020505P OUTPUT RIPPLE (20MHz Band)
0.1F
Ripple (mVPP)
Efficiency
Load
Load Current (mA)
Figure
Figure
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FUNCTIONAL DESCRIPTION OVERVIEW
DCP02 offers unregulated output power from 12V, 15V, input source with typical efficiency 89%. This efficiency achieved through highly integrated packaging technology implementation custom power stage control circuit design uses advanced BiCMOS/DMOS process. This interference occurs because small variations switching frequencies between DC/DC converters. DCP02 overcomes this interference allowing devices synchronized another. eight devices synchronized connecting SYNC pins together, taking care minimize capacitance tracking. Stray capacitance 10pF) effect reducing switching frequency, even stopping oscillator circuit. also recommended that power ground lines star-connected. should noted that synchronized devices used start devices will draw maximum current simultaneously. This configuration cause input voltage dip; dips below minimum input voltage (4.5V), devices start 2.2µF capacitor should connected close input pins. more than eight devices synchronized, recommended that SYNC pins driven external device. Details contained Application Report SBAA035, External Synchronization DCP01/02 Series DC/DC Converters, available download from www.ti.com.
POWER STAGE
DCP02 uses push-pull, center-tapped topology switching 400kHz (divide-by-2 from 800kHz oscillator).
OSCILLATOR WATCHDOG
onboard 800kHz oscillator generates switching frequency divide-by-2 circuit. oscillator synchronized other DCP02 circuits external source, used minimize system noise. watchdog circuit checks operation oscillator circuit. oscillator stopped pulling SYNC low. output pins will tri-stated, which occurs 2µs.
THERMAL SHUTDOWN
DCP02 protected thermal-shutdown circuit. on-chip temperature exceeds +150°C, device will shut down. Once temperature falls below +150°C, normal operation resumes.
CONSTRUCTION
basic construction DCP02 same standard ICs; there substrate within molded package. DCP02 constructed using rectifier diodes, wound magnetic toroid leadframe. Since there solder within package, DCP02 does require special printed circuit board (PCB) assembly processing. This architecture results isolated DC/DC converter with inherently high reliability.
SYNCHRONIZATION
event that more than DC/DC converter needed onboard, beat frequencies other electrical interference generated.
VSUPPLY SYNC SYNC
VOUT VOUT VOUT VOUT
NOTE: requires low-ESR ceramic capacitor: version 2.2mF; version minimum 0.47mF. COUT 1.0mF.
Figure Connecting DCP02 Series
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ADDITIONAL FUNCTIONS DISABLE/ENABLE
DCP02 disabled enabled driving SYNC using open drain CMOS gate. SYNC pulled low, DCP02 will disabled. disable time depends upon external loading; internal disable function implemented 2µs. Removal pull down causes DCP02 enabled. Capacitive loading SYNC should minimized order prevent reduction oscillator frequency. Connecting DCP02 Series Multiple DCP02 isolated DC/DC converters connected series provide nonstandard voltage rails. This configuration possible using floating outputs provided galvanic isolation DCP02. Connect positive VOUT from DCP02 negative VOUT (0V) another (see Figure SYNC pins tied together, self-synchronization feature DCP02 prevents beat frequencies voltage rails. SYNC feature DCP02 allows easy series connection without external filtering, thus minimizing cost. outputs dual-output DCP02 versions also connected series provide times magnitude VOUT, shown Figure example, dual DCP022415D could connected provide rail. Connecting DCP02 Parallel output power from DCP02 sufficient, possible parallel outputs multiple DCP02s, shown Figure Again, SYNC feature allows easy synchronization prevent power-rail beat frequencies additional filtering cost.
VSUPPLY +VOUT -VOUT +VOUT -VOUT
DECOUPLING
Ripple Reduction high switching frequency 400kHz allows simple filtering. reduce ripple, recommended that capacitor used VOUT. Dual outputs should both decoupled 2.2µF capacitor input also recommended.
NOTE: requires low-ESR ceramic capacitor: version 2.2mF; version minimum 0.47mF. COUT 1.0mF.
Figure Connecting Dual Outputs Series
VSUPPLY
SYNC SYNC
VOUT
Power VOUT
NOTE: requires low-ESR ceramic capacitor: version 2.2mF; version minimum 0.47mF. COUT 1.0mF.
Figure Connecting Multiple DCP02s Parallel
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APPLICATION INFORMATION
DCP01B, DCV01, DCP02 three families miniature DC/DC converters providing isolated unregulated voltage output. fabricated using CMOS/DMOS process with DCP01B replacing familiar DCP01 family that fabricated from bipolar process. DCP02 essentially extension DCP01B family, providing higher power output with significantly improved load regulation. DCV01 tested higher isolation voltage.
OPTIMIZING PERFORMANCE
Optimum performance only achieved device correctly supported. very nature switching converter requires power instantly available when switches converter DMOS switching transistors, fast edges will create high current demand input supply. This transient load placed input supplied external input decoupling capacitor, thus maintaining input voltage. Therefore, input supply does this transient (this analogy high-speed digital circuits). positioning capacitor critical must placed close possible input pins connected low-impedance path. optimum performance primarily depends factors: Connection input output circuits minimal loss. ability decoupling capacitors maintain input output voltages constant level. Design copper losses (resistance inductance) minimized mutual ground power planes (tracks) where possible. that possible, wide tracks reduce losses. several devices being powered from common power source, star-connected system track must deployed; devices must connected series, this will cascade resistive losses. position decoupling capacitors important. They must close devices possible order reduce losses. Layout section more details.
TRANSFORMER DRIVE CIRCUIT
Transformer drive transistors have characteristically value transistor resistance (RDS); thus, more power transferred transformer. transformer drive circuit limited base current available switch power transistors driving transformer characteristic current gain (beta), resulting slower turn-on time. Consequently, more power dissipated within transistor, resulting lower overall efficiency, particularly higher output load currents.
SELF-SYNCHRONIZATION
input synchronizations facility (SYNCIN) allows easy synchronizing multiple devices. eight devices (maximum) have their respective SYNCIN pins connected together, then devices will synchronized. Each device onboard oscillator. This oscillator generated charging capacitor from constant current producing ramp. When this ramp passes threshold, internal switch activated that discharges capacitor second threshold before cycle repeated. When several devices connected together, internal capacitors charged simultaneously. When device passes threshold during charge cycle, starts discharge cycle. other devices sense this falling voltage and, likewise, initiate discharge cycle that devices discharge together. subsequent charge cycle only restarted when last device finished discharge cycle.
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Decoupling Ceramic Capacitors capacitors have losses because internal equivalent series resistance (ESR), lesser degree, equivalent series inductance (ESL). Values always easy obtain. However, some manufacturers provide graphs frequency versus capacitor impedance. These graphs typically show capacitor impedance falling frequency increased shown Figure 10). frequency increases, impedance stops decreasing begins rise. point minimum impedance indicates resonant frequency capacitor. This frequency where components capacitance inductance reactance equal magnitude. Beyond this point, capacitor effective capacitor.
Input Capacitor Effects input decoupling capacitor ceramic with ESR, then instant power transistors switch voltage input pins falls momentarily. Should voltage fall below approximately detects under-voltage condition switches drive circuits state. This detection carried precaution against genuine input voltage condition that could slow down even stop internal circuits from operating correctly. slow-down stoppage would result drive transistors being turned long, causing saturation transformer destruction device. Following detection input voltage condition, device switches internal drive circuits until input voltage returns safe value. Then device tries restart. input capacitor still unable maintain input voltage, shutdown recurs. This process repeated until capacitor charged sufficiently start device correctly. Otherwise, device will caught loop. Normal startup should occur approximately from power being applied device. considerably longer startup duration time encountered, likely that either both) input supply capacitors performing adequately. input devices, 2.2µF low-ESR ceramic capacitor ensures good startup performance. remaining input voltage ranges, 0.47µF ceramic capacitors recommended. Tantalum capacitors recommended, since most have low-ESR values will degrade performance. tantalum capacitors must used, close attention must paid both voltage derated vendor. Output Ripple Calculation Example DCP020505: Output voltage Output current 0.4A. full output power, load resistor 12.5. Output capacitor 1µF, 0.1. Capacitor discharge time 800kHz (ripple frequency): tDIS 0.0125µs RLOAD 12.5 12.5µs VDIS VO(1 EXP(-tDIS/)) VDIS contrast, voltage dropped because ESR: VESR VESR 40mV Ripple voltage 45mV
XL)2 (ESR)2 Where: reactance capacitance. reactance ESL. resonant frequency. Frequency
Figure Capacitor Impedance Frequency however, there 180° phase difference resulting cancellation imaginary component. resulting effect that impedance resonant point real part complex impedance; namely, value ESR. resonant frequency must well above 800kHz switching frequency DCVs. effect cause voltage drop within capacitor. value this voltage drop simply product transient load current, shown:
(ESR ITR)
Where: voltage device input. maximum value voltage capacitor during charge. transient load current. other factor that affects performance value capacitance. However, input full wave outputs (single-output voltage devices), dominant factor.
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Clearly, increasing capacitance much smaller effect output ripple voltage than does reducing value filter capacitor.
DUAL OUTPUT VOLTAGE DCVs
voltage output dual DCPs half wave rectified; therefore, discharge time 1.25µs. Repeating above calculations using 100% load resistance (0.2A output), results are: 25µs tDIS 1.25µs VDIS 244mV VESR 20mV Ripple Voltage 266mV This time, capacitor discharging that contributes largest component ripple. Changing output filter 10µF, repeating calculations, result Ripple Voltage 45mV. This value composed almost equal components. previous calculations given only guide. Capacitor parameters usually have large tolerances susceptible environmental conditions.
SYNCIN pin, when being used, best left floating pad. ground ring annulus connected around prevents noise being conducted onto pin. SYNCIN connected more SYNCIN pins, then linking trace should narrow must kept short length. addition, other trace should close proximity this trace because that will increase stray capacitance this pin. turn, stray capacitance affects performance oscillator. Ripple Noise Careful consideration should given layout PCB, order obtain best results. DCP02 switching power supply, such place high peak current demands input supply. order avoid supply falling momentarily during fast switching pulses, ground power planes should used connect power input DCP02. this connection possible, then supplies must connected star formation with traces made wide possible. SYNCIN being used, then trace connection between device SYNCIN pins should short avoid stray capacitance. SYNCIN being used, advisable place guard ring (connected input ground) around this avoid noise pick output should taken from device using ground power planes; this ensures minimum losses. good quality low-ESR ceramic capacitor placed close practical across input reduces reflected ripple ensures smooth startup. good quality low-ESR capacitor (ceramic preferred) placed close practical across rectifier output terminal output ground gives best ripple noise performance. Application Bulletin SBVA012, DC-to-DC Converter Noise Reduction, more information noise rejection.
LAYOUT
Figure Figure illustrate printed circuit board (PCB) layout conventional (DCP01/02, DCV01), SO-28 surface-mount packages (DCP02U). Figure shows schematic. Input power ground planes have been used, providing low-impedance path input power. output, common been connected ground plane, while connections positive negative voltage outputs conducted wide traces order minimize losses. location decoupling capacitors close proximity their respective pins ensures losses effects stray inductance; thus, improving ripple performance. This location particular importance input decoupling capacitor, because this capacitor supplies transient current associated with fast switching waveforms power drive circuits.
THERMAL MANAGEMENT
Because high power density this device, advisable provide ground planes input output.
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Figure Example Layout, Component-Side View
Figure Example Layout, Non-Component-Side View
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CON1 COM1 C4-1 C2-1 DCP02xP COM3 SYNC DCP02xU SYNC CON3
CON2 COM2 C9-1 C7-1 DCP02xP COM4 SYNC
CON4 SYNC DCP02xU
Capacitors C2-1, C4-1, C7-1, C9-1 through-hole plated components connected parallel with (1206 SMD), respectively. optimum low-noise performance, low-ESR capacitors. connect SYNC jumper (JP1-JP4) SYNC function being used. Connections power input should made with minimum wire 16/0.2 twisted pair, with length kept short. input supply ground respectively represents channel). positive negative outputs, referenced common ground COMx. links used self-synchronization; this facility being used, links should unconnected. R1-R8 power output loads; these external load connected. CON1 CON2 DIL-14; CON3 CON4 SO-28 packages. (10) connected.
Figure Example Layout, Schematic Diagram
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device DCP020503P DCP020503U DCP020503U/1K DCP020505P DCP020505U DCP020505U/1K DCP020507P DCP020507U DCP020507U/1K DCP020509P DCP020509U DCP020515DP DCP020515DU DCP020515DU/1K DCP021205P DCP021205PE4 DCP021205U DCP021205U/1K DCP021212DP DCP021212DU DCP021212DU/1K DCP021212P DCP021212U DCP021212U/1K DCP021215DP DCP021515P DCP021515PE4 DCP021515U DCP021515U/1K DCP022405DP DCP022405DU DCP022405DU/1K DCP022405P DCP022405U Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP Package Drawing Pins Package Plan 1000 1000 1000 1000 1000 1000 1000 1000 1000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Lead/Ball Finish NIPDAU NIPDAU NIPDAU SNPB NIPDAU NIPDAU NIPDAU SNPB SNPB NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Peak Temp Type Level-3-240C-168 Level-3-240C-168 Type Level-3-240C-168 Level-3-240C-168 Type Level-3-240C-168 Level-3-240C-168 Type Level-3-260C-168 Type Level-3-240C-168 Level-3-240C-168 Type Type Level-3-240C-168 Level-3-240C-168 Type Level-3-240C-168 Level-3-240C-168 Type Level-3-240C-168 Level-3-240C-168 Call Type Type Level-3-240C-168 Level-3-240C-168 Type Level-3-240C-168 Level-3-240C-168
NIPDAULATEN Type NIPDAU Level-3-240C-168
Addendum-Page
PACKAGE OPTION ADDENDUM
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18-Sep-2006
Orderable Device DCP022405U/1K DCP022412DP DCP022415DP DCP022415DU DCP022415DU/1K DCP022418DP
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type PDIP PDIP PDIP
Package Drawing
Pins Package Plan 1000 1000 Pb-Free (RoHS)
Lead/Ball Finish NIPDAU Call NIPDAU NIPDAU NIPDAU Call
Peak Temp Level-3-240C-168 Call Type Level-3-240C-168 Level-3-240C-168 Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MPDI058 APRIL 2001
(R-PDIP-T7/14)
0.775 (19,69) 0.735 (18,67)
PLASTIC DUAL-IN-LINE
0.280 (7,11) 0.240 (6,10) Index Area
Base Plane 0.070 (1,78) 0.045 (1,14) 0.195 (4,95) 0.115 (2,92) 0.325 (8,26) 0.300 (7,62)
0.015 (0,38)
0.210 (5,33)
0.005 (0,13) Full Lead
0.100 (2,54) Seating Plane 0.022 (0,56) 0.014 (0,36) 0.010 (0,25)
0.150 (3,81) 0.115 (2,92)
0.300 (7,63)
0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.000 (0,00)
0.430 (10,92)
4202489/A 03/01
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Dimensions measured with package seated JEDEC seating plane gauge GS-3. Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 (0,25). Dimensions measured with leads constrained perpendicular Datum Dimensions measured lead tips with leads unconstrained. Pointed rounded lead tips preferred ease insertion. Lead shoulder maximum dimension does include dambar protrusions. Dambar protrusions shall exceed 0.010 (0,25).
Distance between leads including dambar protrusions 0.005 (0,13) minumum. visual index feature must located within cross-hatched area. automatic insertion, raised irregularity surface (step, mesa, etc.) shall symmetrical about lateral longitudinal package centerlines. Falls within JEDEC MS-001-AA.
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MECHANICAL DATA
MPDS106A AUGUST 2001 REVISED NOVEMBER 2001
DVB(R-PDSO-G12/28)
PLASTIC SMALL-OUTLINE
18,10 17,70 11,20 10,8
0°-8° 1,27 0,40
7,60 7,40 Index Area
10,65 10,01 0,25
0,30 0,10 2,65 2,35
0,75 0,25
Base Plane Seating Plane 1,27 0,51 0,33 0,10 0,32 0,23
0,25
4202104/B 11/01 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body length dimension does include mold flash, protrusions, gate burrs. Mold flash, protrusions, gate burrs shall exceed 0,15 side. Body width dimension does include inter-lead flash portrusions. Inter-lead flash protrusions shall exceed 0,25 side. chamfer body optional. present, visual index feature must located within cross-hatched area. Lead dimension length terminal soldering substrate. Lead width, measured 0,36 greater above seating plane, shall exceed maximum value 0,61 Lead-to-lead coplanarity shall less than 0,10 from seating plane. Falls within JEDEC MS-013-AE with exception number leads.
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