ASSP (USB2.0 Peripheral Controller) REJ03F0101-0100Z Rev.1.00 Nov
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M66591GP
ASSP (USB2.0 Peripheral Controller)
REJ03F0101-0100Z Rev.1.00 Nov. 2004
1.The M66591 general-purpose (Universal Serial Bus) device controller compliant with Universal Serial Specification Revision supports both Hi-Speed Full-Speed transfer. Hi-Speed Full-Speed transceiver built-in, M66591 meets control, bulk interrupt transfer types which defined Universal Serial Specification Revision 2.0. M66591 3.5K byte FIFO endpoints (maximum) data transfer. Further, being equipped with split (DMA interface) which independent from interface, M66591 suitable systems that require large capacity data transfer Hi-Speed.
Features
Universal Serial Specification Revision compliant Built-in transceiver Supports both Hi-Speed (480M bps) Full-Speed (12M bps) protocol layer hardware stuffing encoding decoding (Cyclic Redundancy Check) generation checking NRZI (Non Return Zero Invert) encoding decoding Packet detection address checking Hi-Speed Full-Speed detection hardware Supports following transfer types Control transfer (PIPE0) Bulk transfer (PIPE1~PIPE4) Interrupt transfer (PIPE5~PIPE6) Built-in FIFO buffer (3.5K bytes) endpoints endpoints selectable Data transfer condition selectable each PIPE Hi-Speed PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO PIPE1~2: Bulk bulk transfer, 512-byte FIFO, double buffer PIPE3~4: Bulk bulk transfer, 512-byte FIFO, single buffer PIPE5~6: Interrupt transfer, 64-byte FIFO, single buffer Full-Speed PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO PIPE1~2: Bulk bulk transfer, continuous transfer mode, 512-byte FIFO, double buffer PIPE3~4: Bulk bulk transfer, continuous transfer mode, 512-byte FIFO, single buffer PIPE5~6: Interrupt transfer, 64-byte FIFO, single buffer Automatic response Address request Supports following input frequency 48MHz Supports 16-bit 8/16-bit transfer Supports separate/multiplex 16-bit separate/multiplex Supports 8-bit split (DMA interface) status output power management 1.8V/3.3V interface power supply Application Digital camera, printer, external storage device Hi-Speed peripheral device
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M66591GP
Configuration
configuration (top view) M66591 shown Figure 1.1.
DGND(GND) DGND(GND)
SD0/PA0
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
SD1/PA1 SD2/PA2 SD3/PA3 SD4/PA4 SD5/PA5 SD6/PA6 SD7/PA7 RD_N WR0_N WR1_N CS_N DGND(GND) DREQ DACK DSTB_N DEND RST_N
D1/AD1
A7/ALE SUSP_ON CONF_ON DGND(GND) MPBUS TEST1 TEST0 XOUT DGND(GND)
M66591GP (Top View)
AFEDGND
AFEAVDD
AFEAVDD
AFEAVDD
BIASGND
DGND(GND)
AFEAGND
AFEAGND
REFRIN
VBUS
TR_ON
BIASVDD
AFEDVDD
PLLGND
M66591GP: 80pin LQFP (0.4mm pitch, Outline: 80P6R-A)
Figure Configuration M66591
Rev.1.00 Nov. 2004 page
PLLVDD
M66591GP functions M66591 shown Table 1.1.
Table Functions M66591
Item interface D7/AD7-D1/AD Input/Output Name D15-D8 Input/Output Input/Output Name Function Data These data access registers from CPU. Data Address When select 16-bit separate bus, these pins used D7-D0 data bus. When select 16-bit multiplex bus, D7-D0 input/output AD7-AD1 input performed time-sharing. this case, used. A7/ALE, A6-A1 Input Address Address Latch Enable When select 16-bit separate bus, these pins address access registers from CPU. When select 16-bit multiplex bus, becomes pin, latching addresses falling edge. A6-A1 used. CS_N RD_N WR1_N WR0_N MPBUS Input Input Input Input Input Chip Select When this level, M66591 selected. Read Strobe Data read from registers level. D15-D8 Byte Write Strobe data (D15-D8) written registers rising edge. D7-0 Byte Write Strobe data (D7-D0) written registers rising edge. Mode Select 16-bit separate selected level. 16-bit multiplex selected high level. This should switched after reset. Interrupt interface Output Interrupt Interrupts requested CPU. Polarity this selected register setting. interface SD7/PA7-SD0/ DREQ Output Input/Output Split General-purpose Port These pins used select either split (DMA Interface) general-purpose port (GPIO). Request This used request transfer D0_FIFO port. Polarity this selected register setting. DACK Input Acknowledge transfer D0_FIFO port enabled either high level. Polarity this selected register setting. DSTB_N Input Split Strobe This used data strobe signal when D0_FIFO port been split (DMA Interface). When RWstb Data FIFO/DMA Control Configuration Register (RD/WR strobe mode), this used data strobe signal. DEND Input/Output Transfer Terminal When PIPE direction "IN", this receives transfer complete signal input signal from other peripheral chip CPU. When PIPE direction "OUT", this indicates last data transferred output signal. Polarity this register. interface Input/Output Input/Output Input/Output Input/Output Hi-Speed Data Connect signal bus. Hi-Speed Data Connect signal bus. Full-Speed Data Connect this resistance. Full-Speed Data Connect this resistance. Count
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M66591GP
Count
Item
Name TR_ON
Input/Output Input Output
Name Function Pull-up Control Connect this TR_ON 1.5K resistance. Pull-up Power Supply Output 3.3V power supply output pull-up. This supply internally converts VBUS input from 3.3V outputs
VBUS
Input
VBUS Input Connect Vbus bus. Connection shutdown Vbus detected.
REFRIN status output SUSP_ON CONF_ON
Input Output
Reference Input Connect this BIASGND 1.2K resistance. Configured Output This used indicate transition configured state. This N-ch open drain output.
Output
Suspend Output This used indicate transition suspend state. This N-ch open drain output.
Clock
XOUT
Input Output Input
Oscillator Input Oscillator Output Reset
These pins used input/output signals internal clock oscillation circuits. Connect crystal unit between Xout pins. external clock signal used, input pin. Leave Xout open.
System control
RST_N
This used initialize values internal register counter level. TEST1-0 Input Input Input Input Input Input Input Input Input Input Input Input Test These pins input test. level keep open. Analog Power Supply Connect 3.3V power supply. AFEAGND AFEDVDD AFEDGND BIASVDD BIASGND PLLVDD PLLGND DGND Analog Ground Transceiver Digital Power Supply Connect 3.3V power supply. Transceiver Digital Power Ground BIAS Power Supply Connect 3.3V power supply. BIASGND Power Supply Connect 3.3V power supply. PLLGND Core Power Supply Connect 3.3V power supply. Power Supply Connect 1.8V 3.3V power supply. Digital Ground
Power supply
AFEAVDD
care method non-used M66591are shown Table 1.2.
Table care method non-used M66591
Item interface interface A6-A1 SD7/PA7-SD0/PA0 DREQ DACK, DEND DSTB_N System control status output TEST1-0 CONF_ON, SUSP_ON Name Open Pull-up pull-down setting output port Open Pull-up pull-down connect Pull-up connect Open connect Open Care Method
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M66591GP
Functions
functions M66591are shown Figure 1.2.
Interface
DREQ DACK DSTB_N DEND
XOUT
Clock
Interface
D15-D8 D7/AD7-D1/AD1, SD7/PA7-SD0/PA0 A7/ALE, A6-A1 CS_N RD_N WR0_N WR1_N MPBUS
M66591
VBUS TR_ON REFRIN
Interface
TEST0 TEST1
Interrupt
System Control
CONF_ON SUSP_ON
Status Output
Figure Function Diagram M66591
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M66591GP
Block Diagram
M66591 contains four blocks, (Serial Interface Engine) side block side block interface unit (BIU) FIFO memory. side block includes transceiver (UTM), protocol engine (Prtcl_Eng), PIPE controller (PIPE_Ctrl), interrupt controller (Int_Ctrl). side block includes FIFO port (FIFO_Port), register block (USB_Reg). block diagram M66591 shown Figure 1.3.
side block
USB_Reg Interface A7/ALE-A1, D15-D8, D7/AD7-D1/AD1, CS_N, RD_N, WR0_N, WR1_N MPBUS FIFO_Port Interface SD7/PA7-SD0/PA0, DREQ, DACK, DSTB_N, DEND
side block
PIPE_Ctrl Interrupt INT_N
Int_Ctrl
Memory
System Control Prtcl_Eng Interface DHP, DFP, REFRIN VBUS TR_ON URST_N, TEST1-0 Clock XIN, XOUT Power Supply GND, VDD,
Figure Block Diagram M66591
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M66591GP
Registers
Read Register Tables
Numbers: Each register connected with internal 16-bit wide, numbers registers located addresses b15-b8, those even addresses b7-b0. State Register Reset: Represents initial state each register immediately after reset with hexadecimal numbers. "H/W reset" reset external reset signal; "S/W reset" reset USBE Operation Enable Register. Read: Read enabled Read disabled (Read value invalid) Read always Read always Write: Write enabled Write enable conditionally (includes some conditions write) Write disabled (Don't care write) Write disabled <Example representation> implemented shaded portion.
Abit
reset reset reset
Bbit
Cbit
<H/W reset: H'0000> <S/W reset: <USB reset: name Reserved. Function
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M66591GP
Register Mapping
M66591 register mapping shown Figure 2.1, Figure Figure 2.3, each register described below.
Address
H'00 H'02
address address Transceiver Control Register Transceiver Control Register
H'04
HS/FS Mode Register
0000h 0000 0000 0100 00??b 0000h
Reset state -??b -000 0000 0000 0000b 0000h
-00b -000 0000 0000 00-b
H'06 H'08 H'0A H'0C H'0E H'10 H'12 H'14 H'16 H'18 H'1A H'1C H'1E H'20 H'22 H'24 H'26 H'28 H'2A H'2C H'2E H'30 H'32 H'34 H'36 H'38 H'3A H'3C H'3E H'40 H'42 H'44 H'46
Test Mode Register Data FIFO/DMA Control Configuration Register Data FIFO/DMA Control Configuration Register Data FIFO/DMA Control Configuration Register
0000h 00??h 0000h 0000h
C_FIFO Port Register D0_FIFO Port Register
0000h 0000h
????h ????h
Continuous Transmit Data Length Register C_FIFO Port Control Register C_FIFO Port Control Register C_FIFO Port Control Register D0_FIFO Port Control Register D0_FIFO Port Control Register D0_FIFO Port Control Register
0000h 0000h 0000h 0000h 0000h 0000h 0000h
0000h 0000h 0000h 0000h 0000h 0000h 0000h
Configuration Register Configuration Register Configuration Register
0000h 0000h 0000h
0000h 0000h
Note: Refer each register described below.
Figure Register Mapping
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M66591GP
Address H'48 H'4A H'4C H'4E H'50 H'52 H'54 H'56 H'58 H'5A H'5C H'5E H'60
address address Configuration Register Configuration Register
0000h 0000h
Reset state 0000h 0000h
Interrupt Status Register
0000 0000 ?000 0000b 0000h 0000h 0000h
0000 0000 ?000 0000b 0000h 0000h 0000h
-001
H'62 H'64 H'66 H'68 H'6A H'6C H'6E H'70 H'72 H'74 H'76 H'78 H'7A H'7C H'7E H'80 H'82 H'84 H'86 H'88 H'8A H'8C H'8E H'90 H'92 H'94 H'96 H'98
Interrupt Status Register Interrupt Status Register Interrupt Status Register
Address Register Request Register Request Register Request Register Request Register Configuration Register Configuration Register Control Register
0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
0000h 0000h 0000h 0000h 0000h -000b
PIPE Configuration Select Register PIPE Configuration Window Register
0000h 0000h
0000h 0000h
Note: Refer each register described below.
Figure Register Mapping
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M66591GP
Address H'9A H'9C H'9E H'A0 H'A2 H'A4 H'A6 H'A8 H'AA
address
address
Reset state
PIPE1 Control Register PIPE2 Control Register PIPE3 Control Register PIPE4 Control Register PIPE5 Control Register PIPE6 Control Register
0000h 0000h 0000h 0000h 0000h 0000h
0000h 0000h 0000h 0000h 0000h 0000h
-00b -00b -00b -00b -00b -00b
Note: Refer each register described below.
Figure Register Mapping
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M66591GP
Register
number address (001h)
Even number address (000h)
SCKE
RpuE
USBE
Transceiver Control Register (USBTrnsCtrl0) XTAL [1:0] XCKE RCKE PLLC
Transceiver Control Register (USBTrnsCtrl1) LNST [1:0]
HS/FS Mode Register (HSFSMode) WKUP RHST [1:0]
Test Mode Register (TestMd)
SUSPEN CONFEN
[2:0]
Data FIFO/DMA Control Configuration Register (PinCtrlCfg0) [7:0]
Data FIFO/DMA Control Configuration Register (PinCtrlCfg1) LDRV
big_end
PAdir
DB_Cfg
Data FIFO/DMA Control Configuration Register (PinCtrlCfg2) DreqA Burst DreqE DackA RWstb DackE
DendA Pktmd DendE
Obus
C_FIFO Port Register (C_FIFOPort0) C_FIFO_Port [15:0]
D0_FIFO Port Register (D0_FIFOPort0) D0_FIFO_Port [15:0]
Continuous Transmit Data Length Register (DCPSdln) SDLN [8:0]
C_FIFO Port Control Register (C_FIFOPortCtrl0) RCNT ISEL Current_PIPE [2:0]
C_FIFO Port Control Register (C_FIFOPortCtrl1) BVAL BCLR FRDY CPU_DTLN [9:0]
C_FIFO Port Control Register (C_FIFOPortCtrl2) SCLR SBUSY
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M66591GP
number address (001h)
RCNT
Even number address (000h)
ABCR
D0_FIFO Port Control Register (D0_FIFOPortCtrl0) TREnb TRclr Current_PIPE [2:0]
D0_FIFO Port Control Register (D0_FIFOPortCtrl2) BVAL BCLR FRDY DMA_DTLN [9:0]
D0_FIFO Port Control Register (D0_FIFOPortCtrl3) TRNCNT [15:0]
Configuration Register (INTPinCfg0) VBSE RSME DVSE CTRE BEMPE INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR
Configuration Register (INTPinCfg1) INTL INTA
Configuration Register (INTPinCfg2) PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ DCP_
Configuration Register (INTPinCfg3) PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ DCP_ NRE6 NRE5 NRE4 NRE3 NRE2 NRE1
Configuration Register (INTPinCfg4) PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ DCP_ EMPE6 EMPE5 EMPE4 EMPE3 EMPE2 EMPE1 EMPE
Interrupt Status Register (INTStatus0)
VBUSINT
RESM
DVST CTRT BEMP
INTN
INTR
VBUSSTS
DVSQ [2:0]
VALID
CTSQ [2:0]
Interrupt Status Register (INTStatus1) PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 _RDY
Interrupt Status Register (INTStatus2) PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ PIPEB_ DCP_ NRDY6 NRDY5 NRDY4 NRDY3 NRDY2 NRDY1 NRDY
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M66591GP
number address (001h)
Interrupt Status Register (INTStatus3)
Even number address (000h)
PIPEB_EM PIPEB_EMP PIPEB_EMP PIPEB_EMP PIPEB_EMP PIPEB_EMP DCP_EMP P_OVR6 _OVR5 _OVR4 _OVR3 _OVR2 _OVR1 _OVR
Address Register (USBAddress) USB_Addr [6:0]
Request Register (USBReq0) bRequest [7:0] bmRequestType [7:0]
Request Register (USBReq1) wValue [15:0]
Request Register (USBReq2) Request Register (USBReq3) wLength [15:0] wIndex [15:0]
Configuration Register (DCPCfg1)
CNTMD
Configuration Register (DCPCfg2) DCP_MXPS [6:0]
Control Register (DCPCtrl) BSTS
SQCLR
NYETMD
CCPL
[1:0]
PIPE Configuration Select Register (PipeCfgSel) PIPE_SEL [2:0]
PIPE Configuration Window Register (PipeCfgWin0) BSTS BSTS BSTS BSTS BSTS BSTS ACLR SQCLR ACLR SQCLR ACLR SQCLR ACLR SQCLR ACLR SQCLR ACLR SQCLR [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] ITMD BFRE DBLB CNTMD EP_NUM [2:0]
PIPE Control Register (i=1~6) (PipeiCtrl(i=1-6))
NYETMD NYETMD NYETMD NYETMD
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M66591GP
Transceiver Control Register
Transceiver Control Register (USBTrnsCtrl0)
<Address: H'00>
XCKE
RCKE
PLLC
SCKE
RpuE
USBE
Xtal [1:0]
15~14 Xtal [1:0] Clock Select
name
Function External clock frequency: 12MHz External clock frequency: 24MHz External clock frequency: 48MHz Reserved Disable oscillation buffer Enable oscillation buffer Disable reference clock (RCK) supply Enable reference clock (RCK) supply Disable Enable Disable internal clock supply Enable internal clock supply
<H/W reset: H'0000> <S/W reset: <USB reset:
XCKE Oscillation Buffer Enable RCKE Internal Reference Clock Supply Enable PLLC Operation Enable SCKE Clock Supply Enable Reserved. "0". Hi-Speed Enable Reserved. "0". RpuE Pull-up Control Reserved. "0". USBE Module Operation Enable
Disable Hi-Speed mode Enable Hi-Speed mode Disable pull-up Enable pull-up module reset state (S/W reset) module operation enable (S/W reset state release)
Xtal [1:0] (Clock Select) Bits (b15-b14) These bits multiplication factor external clock into PLL. XCKE (Oscillation Buffer Enable) (b13) This sets enable/disable oscillation buffer. This after resume from suspend state. RCKE (Internal Reference Clock Supply Enable) (b12) This sets enable/disable internal reference clock supply. this until clock oscillation becomes stable. PLLC (PLL Operation Enable) (b11) This sets enable/disable PLL. this until clock oscillation becomes stable. SCKE (USB Clock Supply Enable) (b10) This sets enable/disable internal clock supply. this until clock oscillation becomes stable.
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M66591GP
(Hi-Speed Enable) (b7) This sets enable/disable Hi-Speed mode. When Hi-Speed mode disabled, M66591 used Full-Speed only device. When Hi-Speed mode enabled, M66591 used either Hi-Speed Full-Speed device. Note: necessary this before enabling internal clock. RpuE (Pull-up Control) (b4) This sets enable/disable line pull-up. USBE (USB Module Operation Enable) (b0) This sets enable/reset state module operation. While this kept "0", register initialized software reset cannot accessed write.
Note: program sequence clock oscillation waiting time setting this register, refer "3.1 System Control".
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M66591GP
Transceiver Control Register
Transceiver Control Register (USBTrnsCtrl1)
<Address: H'02>
LNST [1:0]
15~7 Reserved.
name Reserved. "1". Reserved. LNST [1:0] Line Status Read state Write
Function
<H/W reset: B'0000 0000 0100 00??> <S/W reset: -??> <USB reset: -00>
Invalid (Ignored when written)
LNST [1:0] (Line Status) Bits (b1-b0) These bits indicate (D+/D-) status. relationships between statuses these bits shown table below:
LNST [1:0] State State Squelch UnSquelch Chirp Squelch Chirp Chirp
Explanation Terms: Chirp: Squelch: Unsquelch: Chirp Chirp operation Full-Speed mode operation Hi-Speed mode execution reset handshake protocol Hi-Speed mode enable state (HSE="1") Squelch state (SE0 state idle state) Hi-Speed state Hi-Speed state Chirp state Hi-Speed state Chirp state Hi-Speed state
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M66591GP
HS/FS Mode Register
HS/FS Mode Register (HSFSMode)
<Address: H'04>
WKUP
RHST [1:0]
15~9 WKUP Remote Wakeup
name Reserved. "0". Read
<H/W reset: H'0000> <S/W reset: B'-000 0000 0000 0000> <USB reset: B'-000 0000 0000 00-> Function output remote wakeup signal Output remote wakeup signal Invalid (Ignored when written) Output remote wakeup signal Read Indicate reset handshake status Write Invalid
Write
Reserved. "0". RHST [1:0] Reset Handshake Status
WKUP (Remote Wakeup) (b8) When written this bit, state output 10ms before returning idling state (Remote wakeup signal) then this cleared automatically. idle state minimum needs retained until remote wake signal transmitted Universal Serial Specification Revision 2.0. Therefore, even written this immediately after suspend state detected, state output after waiting. state output even written this while suspend state. Note: When permission remote wakeup been issued from host, this "1". RHST (Reset Handshake Status) Bits (b1-b0) These bits indicate state reset handshake protocol. Reset detection wait state. Reset handshake process. Reset handshake completed, Full-Speed mode. Reset handshake completed, Hi-Speed mode.
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M66591GP
Test Mode Register
Test Register (TestMd)
<Address: H'06>
[2:0]
SUSPEN CONFEN
13~3 SUSPEN
name SUSP_ON Output Enable CONFEN CONF_ON Output Enable Reserved. "0". [2:0] Test Mode Select test mode
Function Disable SUSP_ON output Enable SUSP_ON output Disable CONF_ON output Enable CONF_ON output
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
SUSPEN (SUSP_ON Output Enable) (b15) This sets enable/disable SUSP_ON output. Disable SUSP_ON output. Enable SUSP_ON output. When DVSQ [2:0] bits Interrupt Status Register "1XX", level output SUSP_ON pin. CONFEN (USB Configured Output Enable) (b14) This sets enable/disable CONF_ON output. Disable CONF_ON output. Enable CONF_ON output. When DVSQ [2:0] bits Interrupt Status Register "X11", level output CONF_ON pin. (Test Mode Select) Bits (b2-b0) These bits used select test mode. These bits valid only Hi-Speed mode. During operation Full-Speed mode, these bits "000". 000: Standard operation mode 001: Test_J 010: Test_K 011: Test_SE0_NAK 100: Test_Packet 101-111: Reserved
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M66591GP
Data FIFO/DMA Control Configuration Register
Data FIFO/DMA Control Configuration Register (PinCtrlCfg0)
<Address: H'08>
[7:0]
15~8 [7:0] General port
name Reserved. "0". level High level
Function
<H/W reset: H'00??> <S/W reset: <USB reset:
port number corresponds number.
[7:0] (General Port Bits (b7-b0) When DB_Cfg Data FIFO/DMA Control Configuration Register (GPIO), SD7-SD0 pins assigned general purpose port [7:0]. Since general purpose port separate buffer input output, when port input, read data always state input pins even data written these bits. output buffer general purpose port undefined after reset. necessary write initial value before change direction output, when using output port. And, value undefined when reading from output port.
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M66591GP
Data FIFO/DMA Control Configuration Register
Data FIFO/DMA Control Configuration Register (PinCtrlCfg1)
LDRV
<Address: H'0A>
big_end
PAdir
DB_Cfg
14~9 LDRV
name When VIF=1.7~2.0V When VIF=2.7~3.6V Drive Current Adjust Reserved. "0". big_end Endian Mode Reserved. "0". PAdir Port Direction Reserved. "0". DB_Cfg Data Configuration Input Output Little endian endian
Function
<H/W reset: H'0000> <S/W reset: <USB reset:
SD7-SD0/PA7-PA0 general-purpose port SD7- SD0/PA7-PA0 split
LDRV (Drive Current Adjust) (b15) This used adjust drive current output pins. output pins here refer SD7-0, D15-0, INT, DREQ, DEND, SUSP_ON CONF_ON pins. big_end (Big Endian Mode) (b8) This sets endian C_FIFO port D0_FIFO port. When this "0", C_FIFO port D0_FIFO port becomes little endian. When this "1", C_FIFO port D0_FIFO port becomes endian.
b15~b8 Little Endian Endian number address Even number address b7~b0 Even number address number address
PAdir (Port Direction) (b2) This sets port direction. This valid only when DB_Cfg "0". General purpose port PA7-PA0 input port when this "0". General purpose port PA7-PA0 output port when this "1". DB_Cfg (Data Configuration) (b0) This sets operations SD7-SD0/PA7-PA0. When this "0", SD7-SD0/PA7-PA0 becomes general-purpose port (GPIO). When this "1", SD7-SD0/PA7-PA0 becomes split D0_FIFO port. this case, access D0_FIFO Port Register invalid.
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Data FIFO/DMA Control Configuration Register
Data FIFO/DMA Control Configuration Register (PinCtrlCfg2)
<Address: H'0C>
Pktmd
DreqA
Burst
DreqE
DackE
DendA
DendE
Obus
DackA RWstb
DreqA
name Reserved. "0". active High active DREQ Polarity Select Burst Burst Mode DreqE DREQ Output Enable Reserved. "0". DackA DACK Polarity Select RWstb RD/WR Strobe Mode DackE DACK Select active High active
Function
<H/W reset: H'0000> <S/W reset: <USB reset:
Normal mode (Cycle steal mode) Burst mode Disable DREQ signal output Enable DREQ signal output
WRn_N RD_N pins used strobe signal DSTB_N used strobe signal Address, WRn_N, RD_N CS_N pins selected handshake signal DACK selected handshake signal active High active Transaction completion output mode Buffer completion output mode Disable DEND Enable DEND Hi-Speed drive mode Normal mode
Reserved. "0". DendA DEND Polarity Select Pktmd Packet Mode DendE DEND Enable Reserved. "0". Obus Mode Reserved. "0".
DreqA (DREQ Polarity Select) (b14) This sets DREQ polarity. Burst (Burst Mode) (b13) This selects DREQ timing. When normal mode (cycle steal mode) set, DREQ asserted every transfer bits bits) negated every time DACK input. When burst mode set, DREQ continuously asserted during data transfer negated completion data transfer. DreqE (DREQ Output Enable) (b12) This sets enable DREQ output. DackA (DACK Polarity Select) (b10) This sets DACK polarity.
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RWstb (RD/WR Strobe Mode) (b9) This selects read/write strobe signal data transfer. this order transfer split (DMA Interface). This valid only when DackE "1". DackE (DACK Select) (b8) This selects handshake signal transfer. When this "0", transfer performed bus, where access split (DMA Interface) disabled. DendA (DEND Polarity Select) (b6) This sets DEND polarity. Pktmd (Packet Mode) (b5) This used determine operation DEND which indicates last data transfer data transfer direction data transfer. When this "0", DEND asserted completion packet count transfer specified TRNCNT [15:0] bits D0_FIFO Port Control Register short packet transfer. When this "1", DEND asserted completion buffer size transfer preset PIPE. During direction data transfer this invalid, because DEND kept input direction. DendE (DEND Enable) (b4) This sets enable DEND signal input/output. When input/output DEND disabled, DEND becomes Hi-Z output. When PIPE direction setting Current_PIPE [2:0] bits D0_FIFO Port Control Register DEND kept output direction. When PIPE direction DEND becomes input direction. (10) Obus (OUT Mode) (b2) This selects driving method split (DMA Interface) data DEND pin. When this PIPE direction setting Current_PIPE [2:0] bits D0_FIFO Port Control Register data DEND always driven. And, when these pins kept always ready input. When this PIPE direction setting Current_PIPE [2:0] bits D0_FIFO Port Control Register data DEND driven "High" "Low" during period both DACK DSTB_N asserted. And, when these pins kept always ready input only during period DACK asserted.
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M66591GP
2.10 C_FIFO Port Register
C_FIFO Port Register (C_FIFOPort0)
<Address: H'14>
C_FIFO_Port [15:0]
15~0 C_FIFO Port
name C_FIFO_Port [15:0] Read Reads receive data
Function <When PIPE direction OUT>
<H/W reset: H'0000> <S/W reset: H'????> <USB reset:
<When PIPE direction Write Writes transmit data
C_FIFO_Port [15:0] (C_FIFO Port) Bits (b15-b0) This register data port FIFO buffer reading writing access. data written FIFO buffer sent order first. data received from stored FIFO buffer same order. case 16-bit little endian)
Time (The order data sent bus)
When PIPE direction setting Current_PIPE [2:0] bits C_FIFO Port Control Register (DIR PIPE Configuration Window Register "0".), receive FIFO data register. When PIPE direction (DIR PIPE Configuration Window Register "1".), transmit FIFO data register. Further, direction determined ISEL C_FIFO Port Control Register when ("000") assigned Current_PIPE [2:0] bits. When ISEL "0", becomes receive FIFO data register, when ISEL "1", becomes transmit FIFO data register. corresponding bits become follows according big_end Data FIFO/DMA Control Configuration Register big_end (Little endian) When C_FIFO Port Control Register (8-bit width), C_FIFO_Port [7:0] valid. When C_FIFO Port Control Register (16-bit width), C_FIFO_Port [15:0] valid. C_FIFO_Port [15:8] upper bits, C_FIFO_Port [7:0] lower bits. big_end (Big endian) When C_FIFO Port Control Register "0"(8-bit width), C_FIFO_Port [15:8] valid. When C_FIFO Port Control Register (16-bit width), C_FIFO_Port [15:0] valid. C_FIFO_Port [15:8] lower bits, C_FIFO_Port [7:0] upper bits.
Note: Only this register used access FIFO buffer.
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2.11 D0_FIFO Port Register
D0_FIFO Port Register (D0_FIFOPort0)
<Address: H'18>
D0_FIFO_Port [15:0]
15~0 D0_FIFO Port
name D0_FIFO_Port [15:0] Read Reads receive data
Function <When PIPE direction OUT>
<H/W reset: H'0000 0000> <S/W reset: <USB reset:
<When PIPE direction Write Writes transmit data
D0_FIFO_Port [15:0] (D0_FIFO Port) Bits (b15-b0) This register data port FIFO buffer reading writing access. data written FIFO buffer sent order first. data received from stored FIFO buffer same order. case 16-bit little endian)
Time (The order data sent bus)
When PIPE direction setting Current_PIPE [2:0] bits D0_FIFO Port Control Register (DIR PIPE Configuration Window Register "0".), receive FIFO data register. When PIPE direction (DIR PIPE Configuration Window Register "1".), transmit FIFO data register. Further, when "000" assigned Current_PIPE [2:0] bits DB_Cfg Data FIFO/DMA Control Configuration Register "1", this register invalid access. corresponding bits become follows according big_end Data FIFO/DMA Control Configuration Register big_end (Little endian) When D0_FIFO Port Control Register (8-bit width), D0_FIFO_Port [7:0] valid. When D0_FIFO Port Control Register (16-bit width), D0_FIFO_Port [15:0] valid. D0_FIFO_Port [15:8] upper bits, D0_FIFO_Port [7:0] lower bits. big_end (Big endian) When D0_FIFO Port Control Register "0"(8-bit width), D0_FIFO_Port [15:8] valid. When D0_FIFO Port Control Register (16-bit width), D0_FIFO_Port [15:0] valid. D0_FIFO_Port [15:8] lower bits, D0_FIFO_Port [7:0] upper bits.
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2.12 Continuous Transmit Data Length Register
Continuous Transmit Data Length Register (DCPSdln)
<Address: H'26>
SDLN [8:0]
15~9 SDLN [8:0]
name Reserved. "0".
Function Control read continuous transmit data length
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Control Read Continuous Transmit Data Length
SDLN [8:0] (Control Read Continuous Transmit Data Length) Bits (b8-b0) These bits transmit data length (byte count) control read continuous transfer mode. value includes maximum "H'100" (256 bytes). When control read continuous transfer mode set, this register before writing transmit data into C_FIFO Port Register. This valid only when follows condition condition met. Condition Current_PIPE [2:0] bits "000" ISEL C_FIFO Port Control Register Condition CNTMD="1" Configuration Register (Control continuous transfer mode). operations control read transfer these bits follows: When SDLN value equal integral multiple (excluding 256) MaxPacketSize: M66591, after number data assigned data SDLN bits written FIFO buffer, automatically starts data transmission and, following completion this transmission, automatically transmits zero-length packet next token. When SDLN value equal "256" (H'100): this case, M66591 starts data transmission same above (1), however, does transmit zero-length packet. When SDLN value equal "0": After transmission data written FIFO buffer BVAL set, M66591 starts data transmission. When number data written FIFO equal FIFO buffer size having been set, there need setting BVAL bit. Also, zero-length packet automatically transmitted completion data transmission. order transmit zero-length packet, necessary BVAL without writing data FIFO buffer after setting SDLN bits "0". When SDLN value other than above: M66591, after number data assigned data SDLN written FIFO buffer, automatically starts data transmission. this case, short packet follows transmit data, zero-length packet transmit. (When token received after transmit short packet,M66591 responds with NAK, generating INTN interrupt.)
Note: necessary clear buffer (BCLR="1") after setting SDLN [8:0] bits.
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2.13 C_FIFO Port Control Register
C_FIFO Port Control Register (C_FIFOPortCtrl0)
RCNT
<Address: H'28>
ISEL
Current_PIPE [2:0]
RCNT Read Count Mode
name data
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
CPU_DTLN bits cleared reading receive CPU_DTLN bits counted down reading receive data
Buffer Rewind
<When buffer> Write Invalid (Ignored when written) Clears buffer reading pointer
<When buffer> Write 13~11 Reserved. "0". FIFO Access Maximum Width Reserved. "0". ISEL Access Direction Select Reserved. "0". Current_PIPE [2:0] C_FIFO Port Access PIPE Select "000" "001" "010" "011" "100" "101" "110" "111" PIPE1 PIPE2 PIPE3 PIPE4 PIPE5 PIPE6 Invalid Select FIFO buffer read (control write) Select FIFO buffer write (control read) 8-bit width 16-bit width Invalid (Ignored when written) Clears buffer writing pointer
RCNT (Read Count Mode) (b15) This sets count down mode CPU_DTLN [9:0] bits C_FIFO Port Control Register When this "0", CPU_DTLN [9:0] bits change reading data from C_FIFO Port Register cleared when data read out. When this "1", CPU_DTLN [9:0] bits decremented every time data read from C_FIFO Port Register (Buffer Rewind) (b14) This rewinds reading/writing pointer FIFO buffer writing this bit. Writing this invalid. When PIPE direction having been Current_PIPE [2:0] bits OUT, buffer data read again from beginning after rewind operation. When PIPE direction having been Current_PIPE [2:0] bits data having been written made invalid after rewind operation buffer data written again from beginning. When FRDY C_FIFO Port Control Register "1", rewind operation executable. When written concurrently with renewal Current_PIPE [2:0] bits, rewind operation executed FIFO buffer renewed PIPE.
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(FIFO Access Maximum Width) (b10) This selects width C_FIFO port access. 8-bit width 16-bit width When changing setting, following should noted: When PIPE having been Current_PIPE [2:0] OUT: disabled change setting after Current_PIPE [2:0] been set. sure concurrently with before setting Current_PIPE [2:0]. When PIPE having been Current_PIPE [2:0] disabled change following setting after Current_PIPE [2:0] been set. Changing from MBW="1" (8-bit width) (16-bit width) Changes other than above possible. example changes setting shown below: <Example enable changes setting: write short packet data bytes> PIPE which buffer area bytes. MBW="1" concurrently with setting Current_PIPE [2:0].) write bytes with 16-bit width. change setting "0". write byte with 8-bit width. (131 bytes total) write BVAL bit. (Short packet data transmission) ISEL (DCP Access Direction Select) (b5) This selects access direction DCP. This valid only when Current_PIPE [2:0] bits. Current_PIPE [2:0] (C_FIFO Port Access PIPE Select) Bits (b2-b0) These bits designate access PIPE C_FIFO port. Each configuration register (max. packet size, etc.) PIPE having been Current_PIPE [2:0] should changed. When changing each configuration register PIPE, either change Current_PIPE [2:0] once clear buffer setting BCLR C_FIFO Port Control Register after changing each configuration register. Further, when been Current_PIPE [2:0], neither each configuration register SDLN changed. changed, buffer must cleared. Also, this setting while accessing C_FIFO Port Register should changed. Note: these bits same value Current_PIPE [2:0] bits D0_FIFO Port Control Register PIPE simultaneously both C_FIFO port D0_FIFO port.)
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2.14 C_FIFO Port Control Register
C_FIFO Port Control Register (C_FIFOPortCtrl1)
BVAL
<Address: H'2C>
BCLR
FRDY
CPU_DTLN [9:0]
BVAL Buffer Valid Flag
name <When buffer> Read
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Disables read data buffer Enables read data buffer
Write Invalid (Ignored when written) <When buffer> Read BCLR Buffer Clear Incomplete write data buffer Complete write data buffer Invalid (Ignored when written) Enable transmit short packet
Write
<When buffer> Write Invalid (Ignored when written) Buffer clear (When BVAL "1")
<When buffer> Write 12~10 FRDY C_FIFO Port Ready Reserved. "0". CPU_DTLN [9:0] C_FIFO Receive Data Length Stores receive data length (byte count) Invalid (Ignored when written) Buffer clear (When BVAL "0") Disables access C_FIFO Port Register Enables access C_FIFO Port Register
BVAL (Buffer Valid Flag) (b15) This indicates status whether PIPE buffer Current_PIPE [2:0] bits C_FIFO Port Control Register accessible. When PIPE having been Current_PIPE [2:0] bits C_FIFO Port Control Register OUT, this indicates whether data exist buffer. This changed from following conditions: When buffer become full with received data packet when received short packet continuous transfer mode. When written C_FIFO Port Control Register continuous transfer mode. When packet data have been received non-continuous transfer mode. This cleared when data read from buffer, making buffer empty. However, when zero-length packet received while buffer empty, this cleared. this case, cleared writing BCLR bit. When PIPE having been Current_PIPE [2:0] bits setting this enables transmit short packet. Further, enables transmit zero-length packet setting simultaneously this BCLR bit. This changed from following conditions: When data have been written until buffer becomes full continuous transfer mode. Rev.1.00 Nov. 2004 page
M66591GP When data have been written MaxPacketSize non-continuous transfer mode. When buffer becomes empty, this cleared. Writing this invalid. Further, PIPE having been Current_PIPE [2:0] DCP, IN/OUT direction determined ISEL bit. Note: When PIPE having been Current_PIPE [2:0] bits this "1", writing this prohibited. BCLR (Buffer Clear) (b14) When written this bit, buffer PIPE having been Current_PIPE [2:0] bits cleared. Refer "3.6.2.3 Buffer Clear" detail. While FRDY C_FIFO Port Control Register "1", enables writing this bit. However, PIPE having been Current_PIPE [2:0] bits C_FIFO Port Control Register DCP, buffer having been selected ISEL cleared irrespective FRDY bit. clear buffer DCP, [1:0] bits Control Register before writing this bit. Writing this invalid. FRDY (C_FIFO Port Ready) (b13) C_FIFO Port Register accessed while this bit. CPU_DTLN [9:0] (C_FIFO Receive Data Length) Bits (b9-b0) These bits indicate receive data length. When RCNT C_FIFO Port Control Register "1", every time C_FIFO Port Register read out, these bits count down 8-bit width 16-bit width. When RCNT "0", receive data length retained also during reading data these bits cleared after receive data read out. When PIPE having been Current_PIPE [2:0] bits C_FIFO Port Control Register direction, these bits invalid. Further, when PIPE having been Current_PIPE [2:0] bits DCP, these bits valid only when ISEL "1". Note: necessary polling FDRY confirm FRDY before read these bits. Refer "3.6 Buffer Memory" reading timing.
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2.15 C_FIFO Port Control Register
C_FIFO Port Control Register (C_FIFOPortCtrl2)
<Address: H'2E>
SCLR SBUSY
Buffer Toggle
name <When buffer> Write
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Invalid (Ignored when written) Toggles access buffer
<When buffer> Write SCLR Buffer Clear <When buffer> Write Invalid (Ignored when written) Inhibited
<When buffer> Write 12~0 SBUSY side Buffer Busy Reserved. "0". Invalid (Ignored when written) Clear side buffer access state access state
(Buffer Toggle) (b15) side buffer changed over side buffer writing this while FIFO buffer full continuous transfer mode. this time, buffer ready interrupt occurs. This valid only PIPE direction. Further, when PIPE which been Current_PIPE [2:0] bits C_FIFO Port Control Register DCP, writing this invalid. Writing this invalid. Explanation Terms: Refer "1.5 Block Diagram" about "SIE side" "CPU side". SCLR (Buffer Clear) (b14) side buffer cleared side buffer changed over side buffer writing this bit. This valid only PIPE direction. Further, when PIPE which been Current_PIPE [2:0] bits C_FIFO Port Control Register DCP, writing this invalid. Please according following procedures order this bit: [1:0] bits PIPE Control Register corresponding PIPE having been Current_PIPE [2:0] bits C_FIFO Port Control Register that does respond transaction. Confirm that SBUSY "0". (Confirm that buffer access exists.) Clear SIE-side buffer writing SCLR bit. Writing this invalid. SBUSY (SIE side Buffer Busy) (b13) This indicates that accessing buffer PIPE having been Current_PIPE [2:0] bits C_FIFO Port Control Register Further, when PIPE which been Current_PIPE [2:0] bits DCP, reading this invalid.
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2.16 D0_FIFO Port Control Register
D0_FIFO Port Control Register (D0_FIFOPortCtrl0)
RCNT
<Address: H'30>
ABCR
TREnb
TRclr
Current_PIPE [2:0]
RCNT Read Count Mode
name data
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
DMA_DTLN bits cleared reading receive DMA_DTLN bits counted down reading receive data
Buffer Rewind
<When buffer> Write Invalid (Ignored when written) Clears buffer reading pointer
<When buffer> Write 12~11 ABCR Automatic Buffer Clear Mode Reserved. "0". FIFO Port Access Width TREnb Transaction Counter Enable TRclr Transaction Counter Clear Reserved. "0". Current_PIPE [2:0] D0_FIFO Port Access PIPE Designate "000" "001" "010" "011" "100" "101" "110" "111" Disable D0_FIFO port PIPE1 PIPE2 PIPE3 PIPE4 PIPE5 PIPE6 Invalid 8-bit width 16-bit width Disable transaction counter function Enable transaction counter function Invalid Clears transaction counter Invalid (Ignored when written) Clears buffer writing pointer Disable automatic buffer clear Enable automatic buffer clear
RCNT (Read Count Mode) (b15) This sets count down mode DMA_DTLN [9:0] bits D0_FIFO Port Control Register When this "0", DMA_DTLN [9:0] bits change reading data from D0_FIFO Port Register cleared when data read out. When this "1", DMA_DTLN [9:0] bits decremented every time data read from D0_FIFO Port Register (Buffer Rewind) (b14) This rewinds reading/writing pointer FIFO buffer writing this bit. Writing this invalid. When PIPE direction having been Current_PIPE [2:0] bits OUT, buffer data read again from beginning after rewind operation. When PIPE direction having been Current_PIPE [2:0] bits data having been written made invalid after rewind operation buffer data written again from beginning. When FRDY D0_FIFO Port Control Register "1", rewind operation executable. When Rev.1.00 Nov. 2004 page
M66591GP written concurrently with renewal Current_PIPE [2:0] bits, rewind operation executed FIFO buffer renewed PIPE. ABCR (Automatic Buffer Clear Mode) (b13) This valid only when PIPE direction having been Current_PIPE [2:0] bits OUT. selected whether FIFO cleared software hardware time mentioned below: When zero-length packet been received while buffer kept empty. When short packet received (including, also, zero-length packet) when packet transaction counter been received, where BFRE PIPE Configuration Window Register corresponding PIPE having been Current_PIPE [2:0] "1". Disable automatic buffer clear mode. above (2), buffer status cleared reading buffer data (with BVAL D0_FIFO Port Control Register "1"). Therefore, following completion reading transfer, byte count last transfer confirmed reading DMA_DTLN [9:0] bits (RCNT="0") D0_FIFO Port Control Register Please BCLR D0_FIFO Port Control Register order clear buffer. Enable automatic buffer clear mode. When buffer data have been read out, buffer automatically cleared becomes state ready receiving next data. (FIFO Port Access Width) (b10) This selects width D0_FIFO port access. 8-bit width 16-bit width When changing setting, following should noted: When PIPE having been Current_PIPE [2:0] OUT: disabled change setting after Current_PIPE [2:0] been set. sure concurrently time before setting Current_PIPE [2:0]. When PIPE having been Current_PIPE [2:0] disabled change following setting after Current_PIPE [2:0] been set. When setting been changed, output DREQ does function properly. When short packet transmitted byte write function exists external DMAC, enable write data follows: <Example write last byte short packet port PIPE access PIPE which buffer area bytes. MBW="1" concurrently with setting Current_PIPE [2:0].) Write bytes 16-bit width DREQ/DACK pins DMA, stop external DMAC. Disable DREQ output writing DreqE bit. Change setting "0". Write byte with 8-bit width access. (131 bytes total) Write BVAL bit. (Short packet data transmission) TREnb (Transaction Counter Enable) (b9) This sets enable/disable transaction counter function. Disable transaction counter function Enable transaction counter function This valid only when PIPE direction having been Current_PIPE [2:0] bits OUT. details transaction counter function, refer TRNCNT [15:0] bits D0_FIFO Port Control Register Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~6) "00" (NAK). TRclr (Transaction Counter Clear) (b8) Writing this clears counter transaction counter function. Writing this invalid. Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~6) "00" (NAK).
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Current_PIPE [2:0] (D0_FIFO Port Access PIPE Designate) Bits (b2-b0) These bits designate access PIPE D0_FIFO port. change each configuration register (max. packet size, etc.) PIPE having been Current_PIPE [2:0]. When changing each configuration register PIPE, either change Current_PIPE [2:0] once clear buffer setting BCLR D0_FIFO Port Control Register after changing each configuration register. Also, this setting should changed while accessing D0_FIFO Port Register Note: these bits same value Current_PIPE [2:0] bits C_FIFO Port Control Register PIPE simultaneously both C_FIFO port D0_FIFO port.)
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M66591GP
2.17 D0_FIFO Port Control Register
D0_FIFO Port Control Register (D0_FIFOPortCtrl2)
BVAL
<Address: H'34>
BCLR
FRDY
DMA_DTLN [9:0]
BVAL Buffer Valid Flag
name <When buffer> Read
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Disables read data buffer Enables read data buffer
Write Invalid (Ignored when written) <When buffer> Read BCLR Buffer Clear Incomplete write data buffer Complete write data buffer Invalid (Ignored when written) Enable transmits short packet
Write
<When buffer> Write Invalid (Ignored when written) Buffer clear (When BVAL "1")
<When buffer> Write 12~10 FRDY D0_FIFO Port Ready Reserved. "0". DMA_DTLN [9:0] D0_FIFO Receive Data Stores receive data length (byte count) Invalid (Ignored when written) Buffer clear (When BVAL "0") Disables access D0_FIFO Port Register Enables access D0_FIFO Port Register
BVAL (Buffer Valid Flag) (b15) This indicates status whether PIPE buffer Current_PIPE [2:0] bits D0_FIFO Port Control Register accessible. When PIPE which been Current_PIPE [2:0] bits D0_FIFO Port Control Register OUT, this indicates whether data exist buffer. This changed from following conditions: When buffer become full with received data packet when received short packet continuous transfer mode. When packet been received value preset TRNCNT [15:0] bits D0_FIFO Port Control Register with TREnb D0_FIFO Port Control Register "1". When packet data have been received non-continuous transfer mode. This cleared when data read from buffer, making buffer empty. This automatically cleared depending setting BFRE PIPE Configuration Window Register corresponding setting PIPE having been ABCR Current_PIPE [2:0] bits D0_FIFO Port Control Register details, refer ABCR bit. When PIPE having been Current_PIPE [2:0] bits setting this enables transmit short packet. Further, enables transmit zero-length packet setting simultaneously this Rev.1.00 Nov. 2004 page
M66591GP BCLR bit. This changed from following conditions: When data have been written until buffer becomes full continuous transfer mode. When data have been written MaxPacketSize non-continuous transfer mode. When DEND been asserted during transfer: When buffer becomes empty, this cleared. Writing this invalid. Note: When PIPE which been Current_PIPE [2:0] bits this "1", write this bit. BCLR (Buffer Clear) (b14) When written this bit, buffer PIPE having been Current_PIPE [2:0] bits cleared. Refer "3.6.2.3 Buffer Clear" detail. While FRDY D0_FIFO Port Control Register "1", enables writing this bit. Writing this invalid. FRDY (D0_FIFO Port Ready) (b13) D0_FIFO Port Register accessed while this bit. DMA_DTLN [9:0] (D0_FIFO Receive Data) Bits (b9-b0) These bits indicate receive data length. When RCNT D0_FIFO Port Control Register "1", every time D0_FIFO Port Register read out, these bits count down 8-bit width 16-bit width. When RCNT "0", receive data length retained also during data reading this bits cleared after received data read out. When PIPE which been Current_PIPE [2:0] bits D0_FIFO Port Control Register direction, this invalid. Note: necessary polling FDRY confirm FRDY before read these bits. Refer "3.6 Buffer Memory" reading timing.
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2.18 D0_FIFO Port Control Register
D0_FIFO Port Control Register (D0_FIFOPortCtrl3)
<Address: H'36>
TRNCNT [15:0]
15~0 TRNCNT [15:0]
name Transaction Counter
Function <When TREnb "0"> Packet count that completes receiving <When TREnb "1"> Received packet count
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
TRNCNT [15:0] (Transaction Counter) Bits (b15-b0) These bits valid only when PIPE direction having been Current_PIPE [2:0] bits D0_FIFO Port Control Register OUT. transaction counter uses internal registers: Current counter register Upper limit register Writing these bits means writing upper limit register. Reading these bits consists following: When TREnb D0_FIFO Port Control Register "0", upper limit register read out. When TREnb D0_FIFO Port Control Register "1", current counter register read out. When TREnb D0_FIFO Port Control Register "1", every time transaction received, current counter register incremented. current counter register cleared following event: When short packet been received executed transaction. When current counter register reached upper limit register above When been written TRclr D0_FIFO Port Control Register Note: Before setting these bits, sure [1:0] bits PIPE Control Register (i=1~6) "00" (NAK). When TREnb "1", sure change this register.
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2.19 Configuration Register
Configuration Register (INTPinCfg0)
VBSE
<Address: H'40>
RSME
DVSE
URST
SADR
SCFG
SUSP
WDST
RDST
CMPL
SERR
CTRE BEMPE INTNE INTRE
VBSE
name Disable interrupt VBUS Interrupt Enable
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Enable interrupt (Interrupt occurs when VBUSINT Interrupt Status Register "1") Disable interrupt Enable interrupt (Interrupt occurs when RESM Interrupt Status Register "1")
RSME Resume Interrupt Enable
Reserved. "0". DVSE Device State Transition Interrupt Enable Disable interrupt Enable interrupt (Interrupt occurs when DVST Interrupt Status Register "1") Disable interrupt Enable interrupt (Interrupt occurs when CTRT Interrupt Status Register "1") Disable interrupt Enable interrupt (Interrupt occurs when BEMP Interrupt Status Register "1") Disable interrupt Enable interrupt (Interrupt occurs when INTN Interrupt Status Register "1") Disable interrupt Enable interrupt (Interrupt occurs when INTR Interrupt Status Register "1") Disable DVST Enable DVST Disable DVST Enable DVST Disable DVST Enable DVST Disable DVST Enable DVST Disable CTRT Enable CTRT Disable CTRT Enable CTRT Disable CTRT Enable CTRT Disable CTRT Enable CTRT
CTRE Control Transfer Stage Transition Interrupt Enable
BEMPE
PIPE Buffer Empty/Size Error Interrupt Enable INTNE PIPE Buffer Ready Interrupt Enable INTRE PIPE Buffer Ready Interrupt Enable URST Reset Detect SADR SetAddress Execute SCFG SetConfiguration Execute SUSP Suspend Detect WDST Control Write Transfer Data Stage Complete RDST Control Read Transfer Data Stage Complete CMPL Control Transfer Complete SERR Control Transfer Sequence Error
VBSE (VBUS Interrupt Enable) (b15) This sets enable/disable VBUS interrupt. When this "1", interrupt occurs VBUS Interrupt Status Register "1". This capable writing/reading even clock supplied (SCKE XCKE Transceiver Control Register 0.).
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RSME (Resume Interrupt Enable) (b14) This sets enable/disable resume interrupt. When this "1", interrupt occurs RESM "1". This capable writing/reading even clock supplied (SCKE XCKE Transceiver Control Register 0.). DVSE (Device State Transition Interrupt Enable) (b12) This sets enable/disable device state transition interrupt. When this "1", interrupt occurs DVST "1". conditions setting DVST depend URST, SADR, SCFG SUSP bits. CTRE (Control Transfer Stage Transition Interrupt Enable) (b11) This sets enable/disable control transfer stage transition interrupt. When this "1", interrupt occurs CTRT "1". conditions setting CTRT depend WDST, RDST, CMPL SERR bits. complete setup stage cannot enable/disable CTRT bit. BEMPE (PIPE Buffer Empty/Size Error Interrupt Enable) (b10) This sets enable/disable PIPE buffer empty/size error interrupt. When this "1", interrupt occurs BEMP "1". INTNE (PIPE Buffer Ready Interrupt Enable) (b9) This sets enable/disable PIPE buffer ready interrupt. When this "1", interrupt occurs INTN "1". INTRE (PIPE Buffer Ready Interrupt Enable) (b8) This sets enable/disable PIPE buffer ready interrupt. When this "1", interrupt occurs INTR "1". URST (USB Reset Detect) (b7) This selects whether DVST reset detection. register initialized reset detection, irrespective value this bit. SADR (SetAddress Execute) (b6) This selects whether DVST SetAddress execution. details, refer DVST bit. (10) SCFG (SetConfiguration Execute) (b5) This selects whether DVST SetConfiguration execution. details, refer DVST bit. (11) SUSP (Suspend Detect) (b4) This selects whether DVST suspend detection. (12) WDST (Control Write Transfer Data Stage Complete) (b3) This selects whether CTRT when transited status stage after data stage during control write transfer. (13) RDST (Control Read Transfer Data Stage Complete) (b2) This selects whether CTRT when transited status stage after data stage during control read transfer.
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(14) CMPL (Control Transfer Complete) (b1) This selects whether CTRT when status stage completes during control transfer. (15) SERR (Control Transfer Sequence Error) (b0) This selects whether CTRT when sequence error detected during control transfer. Note: Refer "3.3 Interrupt" detail.
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M66591GP
2.20 Configuration Register
Configuration Register (INTPinCfg1)
<Address: H'42>
INTL
INTA
15~2 INTL
name Reserved. "0". Edge sense Level sense Active High Active Interrupt Output Sense INTA Interrupt Output Polarity
Function
<H/W reset: H'0000> <S/W reset: <USB reset:
INTL (Interrupt Output Sense) (b1) This selects interrupt signal output type. When edge sense selected, interrupt signal negated when interrupt factors have been cleared. However, when other interrupt factor still cleared, signal asserted once again. duration negation 650ns. When level sense selected, signal kept asserted until interrupt factors cleared. INTA (Interrupt Output Polarity) (b0) This sets interrupt signal output polarity.
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2.21 Configuration Register
Configuration Register (INTPinCfg2)
<Address: H'44>
PIPEB_RE6 PIPEB_RE5 PIPEB_RE4 PIPEB_RE3 PIPEB_RE2 PIPEB_RE1 DCP_RE
15~7 PIPEB_RE6
name Reserved. "0".
Function Disable INTR Enable INTR Disable INTR Enable INTR Disable INTR Enable INTR Disable INTR Enable INTR Disable INTR Enable INTR Disable INTR Enable INTR Disable INTR Enable INTR
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
PIPE6 Buffer Ready Interrupt Enable PIPEB_RE5 PIPE5 Buffer Ready Interrupt Enable PIPEB_RE4 PIPE4 Buffer Ready Interrupt Enable PIPEB_RE3 PIPE3 Buffer Ready Interrupt Enable PIPEB_RE2 PIPE2 Buffer Ready Interrupt Enable PIPEB_RE1 PIPE1 Buffer Ready Interrupt Enable DCP_RE DCP_FIFO Buffer Ready Interrupt Enable
PIPEB_RE6 (PIPE6 Buffer Ready Interrupt Enable) Bits (b6) This select whether INTR Interrupt Status Register when PIPEB_RDY6 Interrupt Status Register "1". PIPEB_RE5 (PIPE5 Buffer Ready Interrupt Enable) Bits (b5) This select whether INTR Interrupt Status Register when PIPEB_RDY5 Interrupt Status Register "1". PIPEB_RE4 (PIPE4 Buffer Ready Interrupt Enable) Bits (b4) This select whether INTR Interrupt Status Register when PIPEB_RDY4 Interrupt Status Register "1". PIPEB_RE3 (PIPE3 Buffer Ready Interrupt Enable) Bits (b3) This select whether INTR Interrupt Status Register when PIPEB_RDY3 Interrupt Status Register "1". PIPEB_RE2 (PIPE2 Buffer Ready Interrupt Enable) Bits (b2) This select whether INTR Interrupt Status Register when PIPEB_RDY2 Interrupt Status Register "1". PIPEB_RE1 (PIPE1 Buffer Ready Interrupt Enable) Bits (b1) This select whether INTR Interrupt Status Register when PIPEB_RDY1 Interrupt Status Register "1". DCP_RE (DCP_FIFO Buffer Ready Interrupt Enable) (b0) This selects whether INTR Interrupt Status Register when DCP_RDY Interrupt Status Register "1".
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2.22 Configuration Register
Configuration Register (INTPinCfg3)
<Address: H'48>
PIPEB_NRE6 PIPEB_NRE5 PIPEB_NRE4 PIPEB_NRE3 PIPEB_NRE2 PIPEB_NRE1 DCP_NRE
15~7 PIPEB_NRE6
name Reserved. "0".
Function Disable INTN Enable INTN Disable INTN Enable INTN Disable INTN Enable INTN Disable INTN Enable INTN Disable INTN Enable INTN Disable INTN Enable INTN Disable INTN Enable INTN
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
PIPE6 Buffer Ready Interrupt Enable PIPEB_NRE5 PIPE5 Buffer Ready Interrupt Enable PIPEB_NRE4 PIPE4 Buffer Ready Interrupt Enable PIPEB_NRE3 PIPE3 Buffer Ready Interrupt Enable PIPEB_NRE2 PIPE2 Buffer Ready Interrupt Enable PIPEB_NRE1 PIPE1 Buffer Ready Interrupt Enable DCP_NRE
DCP_FIFO Buffer Ready Interrupt Enable
PIPEB_NRE6 (PIPE6 Buffer Ready Interrupt Enable) Bits (b6) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY6 Interrupt Status Register "1". PIPEB_NRE5 (PIPE5 Buffer Ready Interrupt Enable) Bits (b5) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY5 Interrupt Status Register "1". PIPEB_NRE4 (PIPE4 Buffer Ready Interrupt Enable) Bits (b4) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY4 Interrupt Status Register "1". PIPEB_NRE3 (PIPE3 Buffer Ready Interrupt Enable) Bits (b3) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY3 Interrupt Status Register "1". PIPEB_NRE2 (PIPE2 Buffer Ready Interrupt Enable) Bits (b2) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY2 Interrupt Status Register "1". PIPEB_NRE1 (PIPE1 Buffer Ready Interrupt Enable) Bits (b1) These bits select whether INTN Interrupt Status Register when PIPEB_NRDY1 Interrupt Status Register "1". DCP_NRE (DCP_FIFO Buffer Ready Interrupt Enable) (b0) This selects whether INTN Interrupt Status Register when _NRDY Interrupt Status Register "1".
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2.23 Configuration Register
Configuration Register (INTPinCfg4)
<Address: H'4C>
PIPEB_EMPE6 PIPEB_EMPE5 PIPEB_EMPE4 PIPEB_EMPE3 PIPEB_EMPE2 PIPEB_EMPE1 DCP_EMPE
15~7 PIPEB_EMPE6
name Reserved. "0".
Function Disable BEMP Enable BEMP Disable BEMP Enable BEMP Disable BEMP Enable BEMP Disable BEMP Enable BEMP Disable BEMP Enable BEMP Disable BEMP Enable BEMP Disable BEMP Enable BEMP
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
PIPE6 Buffer Empty/Size-Error Interrupt Enable PIPEB_EMPE5 PIPE5 Buffer Empty/Size-Error Interrupt Enable PIPEB_EMPE4 PIPE4 Buffer Empty/Size-Error Interrupt Enable PIPEB_EMPE3 PIPE3 Buffer Empty/Size-Error Interrupt Enable PIPEB_EMPE2 PIPE2 Buffer Empty/Size-Error Interrupt Enable PIPEB_EMPE1 PIPE1 Buffer Empty/Size-Error Interrupt Enable DCP_EMPE DCP_FIFO Buffer Empty/Size-Error Interrupt Enable
PIPEB_EMPE6 (PIPE6 Buffer Empty/Size Error Interrupt Enable) Bits (b6) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR6 Interrupt Status Register "1". PIPEB_EMPE5 (PIPE5 Buffer Empty/Size Error Interrupt Enable) Bits (b5) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR5 Interrupt Status Register "1". PIPEB_EMPE4 (PIPE4 Buffer Empty/Size Error Interrupt Enable) Bits (b4) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR4 Interrupt Status Register "1". PIPEB_EMPE3 (PIPE3 Buffer Empty/Size Error Interrupt Enable) Bits (b3) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR3 Interrupt Status Register "1". PIPEB_EMPE2 (PIPE2 Buffer Empty/Size Error Interrupt Enable) Bits (b2) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR2 Interrupt Status Register "1". PIPEB_EMPE1 (PIPE1 Buffer Empty/Size Error Interrupt Enable) Bits (b1) These bits select whether BEMP Interrupt Status Register when PIPEB_EMP_OVR1 Interrupt Status Register "1". DCP_EMPE (DCP_FIFO Buffer Empty/Size Error Interrupt Enable) (b0) This selects whether BEMP Interrupt Status Register when DCP_EMP_OVR Interrupt Status Register "1".
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2.24 Interrupt Status Register
Interrupt Status Register (INTStatus0)
<Address: H'60>
INTN
DVST
CTRT
BEMP
DVSQ [2:0]
VALID
CTSQ [2:0]
VBUSINT RESM
INTR VBUSSTS
VBUSINT VBUS Interrupt
name Read
Function occurrence interrupt Occurrence interrupt Clear interrupt
<H/W reset: B'0000 0000 ?000 0000> <S/W reset: B'0000 0000 ?000 0000> <USB reset: B'-1 -001
Write Invalid when internal clock supplied (Ignored when written) Cancel interrupt clear status when internal clock supplied RESM Resume Interrupt Read occurrence interrupt Occurrence interrupt Clear interrupt Invalid when internal clock supplied (Ignored when written) Cancel interrupt clear status when internal clock supplied Reserved. "0". DVST Device State Transition Interrupt Read CTRT Control Transfer Stage Transition Interrupt BEMP PIPE Buffer Empty/Size Error Interrupt occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Invalid (Ignored when written) INTN PIPE Buffer Ready Interrupt Read occurrence interrupt Occurrence interrupt Invalid (Ignored when written) INTR PIPE Buffer Ready Interrupt Read occurrence interrupt Occurrence interrupt Invalid (Ignored when written)
Write
Write
Read
Write
Read
Write
Write
Write
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VBUSSTS VBUS Level Port name Read input High input Invalid (Ignored when written) DVSQ [2:0] Device State Read 000: Powered state 001: Default state 010: Address state 011: Configured state 1xx: Suspended state Write Invalid (Ignored when written) VALID Setup Packet Detect Read CTSQ [2:0] Control Transfer Stage detection Receiving setup packet Clear this VALID Invalid (Ignored when written) Function
Write
Write
Read 000: Idle setup stage 001: Control read transfer data stage 010: Control read transfer status stage 011: Control write transfer data stage 100: Control write transfer status stage 101: Control write data transfer status stage 110: Control transfer sequence error 111: Reserved Write Invalid (Ignored when written)
Note: optional value. VBUSINT (VBUS Interrupt) (b15) This indicates change VBUS input. This when VBUS input changes (from High from High Low). This even while internal clock supplied (SCLK Transceiver Control Register "0".). This cleared writing "0". case internal clock supplied (when SCKE Transceiver Control Register "0"), necessary write after writing "0". RESM (Resume Interrupt) (b14) This when state changed from suspended (DVST bits "1xx") state->K state State->"SE0". This even while internal clock supplied (SCLK Transceiver Control Register "0".). This cleared writing "0". case internal clock supplied (when SCKE Transceiver Control Register "0"), necessary write after writing "0". DVST (Device State Transition Interrupt) (b12) This indicates transition device state. device state transition interrupt includes following four factors: reset detect SET_ADDRESS execute SET_CONFIGURATION execute Suspend detect These four factors individually enable/disable. This cleared writing "0". This cleared when internal clock (SCLK) supplied. Writing this affect.
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CTRT (Control Transfer Stage Transition Interrupt) (b11) This indicates transition stage control transfers. control transfer stage transition interrupt includes following fifth factors: Setup stage complete Control write transfer status stage transition Control read transfer status stage transition Control transfer complete Control transfer sequence error These five factors individually enable/disable, excepting setup stage complete. This cleared writing "0". This cleared when internal clock (SCLK) supplied. Writing this affect. BEMP (PIPE Buffer Empty/Size Error Interrupt) (b10) This indicates occurrence buffer empty buffer size over error. When either PIPEB_EMP_OVR [6:1] bits DCP_EMP_OVR Interrupt Status Register "1", this "1". This cleared clearing bits Interrupt Status Register INTN (PIPE Buffer Ready Interrupt) (b9) This indicates been responded host because buffer ready state. When either PIPEB_ NRDY [6:1] bits DCP_ NRDY Interrupt Status Register "1", this "1". This cleared clearing bits Interrupt Status Register INTR (PIPE Buffer Ready Interrupt) (b8) This indicates buffer ready state (that read/write). When either PIPEB_ [6:1] bits DCP_ Interrupt Status Register "1", this "1". This cleared clearing bits Interrupt Status Register VBUSSTS (VBUS Level Port) (b7) This indicates VBUS state. When this changes, VBUSINT "1". This capable reading correct value even internal clock (SCLK) supplied. this directly reflects status VBUS pin, processing reading this three times filter chattering required when executing attach/detach processing using this value. DVSQ [2:0] (Device State) Bits (b6-b4) These bits indicate present device states. device state conforms description concerning device state chapter Universal Serial Specification Revision 2.0. state after hardware resetting Powered state. state after software resetting Powered state. state after resetting Default state. Execution SET_ADDRESS (Address !="0") brings transition into address state, while execution SET_ADDRESS (Address="0") brings transition into default state. Execution SET_CONFIGURATION (Configuration !="0") brings transition into configured state, while execution SET_CONFIGURATION (Configuration="0")" brings transition into address state. Detection suspend brings transition into suspend state. (10) VALID (Setup Packet Detect) (b3) This indicates that setup packet been received. When setup packet completely received, this "1". interrupt does occur with this bit. This cleared writing "0". This cleared when internal clock (SCLK) supplied. Writing this affect. writing enabled [1:0] bits Control Register while this "1". Rev.1.00 Nov. 2004 page
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(11) CTSQ [2:0] (Control Transfer Stage) Bits (b2-b0) These bits indicate present stage control transfer.
Note clearing VBUSINT/RESM/SOFR/DVST/CTST status bits: order continuously clear status bits while VBUSINT/RESM/SOFR/DVST/CTST status bits being multiplexed, access cycle time 100ns more required from clear next clear. example, where both DVST status CTST status simultaneously set, access cycle required from when written DVST when written until CTST 100ns more. Also this time, able clear DVST CTST same time.
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2.25 Interrupt Status Register
Interrupt Status Register (INTStatus1)
<Address: H'64>
PIPEB_RDY6 PIPEB_RDY5 PIPEB_RDY4 PIPEB_RDY3 PIPEB_RDY2 PIPEB_RDY1 DCP_RDY
15~7 PIPEB_RDY6
name Reserved. "0". Read PIPE6 Buffer Ready Interrupt
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written)
Write
PIPEB_RDY5 PIPE5 Buffer Ready Interrupt
Read
Write
PIPEB_RDY4 PIPE4 Buffer Ready Interrupt
Read
Write
PIPEB_RDY3 PIPE3 Buffer Ready Interrupt
Read
Write
PIPEB_RDY2 PIPE2 Buffer Ready Interrupt
Read
Write
PIPEB_RDY1 PIPE1 Buffer Ready Interrupt
Read
Write
DCP_RDY Default Control PIPE Buffer Ready Interrupt
Read
Write
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PIPEB_RDY6 (PIPE6 Buffer Ready Interrupt) Bits (b6) This indicates that PIPE6 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. PIPEB_RDY5 (PIPE5 Buffer Ready Interrupt) Bits (b5) This indicates that PIPE5 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. PIPEB_RDY4 (PIPE4 Buffer Ready Interrupt) Bits (b4) This indicates that PIPE4 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. PIPEB_RDY3 (PIPE3 Buffer Ready Interrupt) Bits (b3) This indicates that PIPE3 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. PIPEB_RDY2 (PIPE2 Buffer Ready Interrupt) Bits (b2) This indicates that PIPE2 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. PIPEB_RDY1 (PIPE1 Buffer Ready Interrupt) Bits (b1) This indicates that PIPE1 buffer kept read ready state. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. DCP_RDY (Default Control PIPE Buffer Ready Interrupt) (b0) This indicates that default control PIPE buffer kept read ready state. When data packet been received properly control write transfer, this "1". When transmission FIFO buffer kept write ready state control read transfer, this "1". default control PIPE buffer empty/size-error interrupt confirm completion control read transfer. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect.
Note clearing buffer ready interrupt (PIPEB_RDY6-PIPEB_RDY1/DCP_RDY) status bits: order continuously clear status bits while PIPEB_RDY6-PIPEB_RDY1/DCP_RDY status bits being multiplexed, access cycle time 100ns more required from clear next clear. example, where both PIPEB_RDY1 status PIPEB_RDY2 status simultaneously set, access cycle required from when written PIPEB_RDY1 until when written PIPEB_RDY2 100ns more. Also this time, able clear PIPEB_RDY1 PIPEB_RDY2 same time. Rev.1.00 Nov. 2004 page
M66591GP
2.26 Interrupt Status Register
Interrupt Status Register (INTStatus2)
<Address: H'68>
PIPEB_NRDY6 PIPEB_NRDY5 PIPEB_NRDY4 PIPEB_NRDY3 PIPEB_NRDY2 PIPEB_NRDY1 DCP_NRDY
15~7 PIPEB_NRDY6
name Reserved. "0". Read PIPE6 Buffer Ready Interrupt
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written)
Write
PIPEB_NRDY5 PIPE5 Buffer Ready Interrupt
Read
Write
PIPEB_NRDY4 PIPE4 Buffer Ready Interrupt
Read
Write
PIPEB_NRDY3 PIPE3 Buffer Ready Interrupt
Read
Write
PIPEB_NRDY2 PIPE2 Buffer Ready Interrupt
Read
Write
PIPEB_NRDY1 PIPE1 Buffer Ready Interrupt
Read
Write
DCP_NRDY Default Control PIPE Buffer Ready Interrupt
Read
Write
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PIPEB_NRDY6 (PIPE6 Buffer Ready Interrupt) Bits (b6) This when token/OUT token received with PIPE6 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_NRDY5 (PIPE5 Buffer Ready Interrupt) Bits (b5) This when token/OUT token received with PIPE5 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_NRDY4 (PIPE4 Buffer Ready Interrupt) Bits (b4) This when token/OUT token received with PIPE4 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE4 Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_NRDY3 (PIPE3 Buffer Ready Interrupt) Bits (b3) This when token/OUT token received with PIPE3 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_NRDY2 (PIPE2 Buffer Ready Interrupt) Bits (b2) This when token/OUT token received with PIPE2 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_NRDY1 (PIPE1 Buffer Ready Interrupt) Bits (b1) This when token/OUT token received with PIPE1 buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits PIPE Control Register "01"(BUF). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. DCP_NRDY (Default Control PIPE Buffer Ready Interrupt) (b0) This when token/OUT token received with buffer ready state. ready status means state which response been issued host disabling transmit/receive while [1:0] bits Control Register "01" (BUF). This response status stage control transfer. This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect. Rev.1.00 Nov. 2004 page
M66591GP
Note clearing buffer ready interrupt status bits: order continuously clear status bits while status bits being multiplexed, access cycle time 100ns more required from clear next clear. example, where both PIPEB_NRDY1 status PIPEB_NRDY2 status simultaneously set, access cycle required from when written PIPEB_NRDY1 until when written PIPEB_NRDY2 100ns more. Also this time, enable clear PIPEB_NRDY1 PIPEB_NRDY2 same time.
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2.27 Interrupt Status Register
Interrupt Status Register (INTStatus3) <Address: H'6C>
PIPEB_EMP PIPEB_EMP PIPEB_EMP PIPEB_EMP PIPEB_EMP PIPEB_EMP DCP_EMP_ _OVR6 _OVR5 _OVR4 _OVR3 _OVR2 _OVR1
15~7
name Reserved. "0". PIPEB_EMP_OVR6 PIPE6 Buffer Empty/Size Error Interrupt Read
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written) occurrence interrupt Occurrence interrupt Clear interrupt Invalid (Ignored when written)
Write
PIPEB_EMP_OVR5 PIPE5 Buffer Empty/Size Error Interrupt
Read
Write
PIPEB_EMP_OVR4 PIPE4 Buffer Empty/Size Error Interrupt
Read
Write
PIPEB_EMP_OVR3 PIPE3 Buffer Empty/Size Error Interrupt
Read
Write
PIPEB_EMP_OVR2 PIPE2 Buffer Empty/Size Error Interrupt
Read
Write
PIPEB_EMP_OVR1 PIPE1 Buffer Empty/Size Error Interrupt
Read
Write
DCP_EMP_OVR Default Control PIPE Buffer Empty/Size- Error Interrupt
Read
Write
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PIPEB_EMP_OVR6 (PIPE6 Buffer Empty/Size-Error Interrupt) Bits (b6) This indicates that received data size exceeds maximum packet size that buffers PIPE6 empty. When transfer direction When data stored buffers PIPE6 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE6 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_EMP_OVR5 (PIPE5 Buffer Empty/Size-Error Interrupt) Bits (b5) This indicates that received data size exceeds maximum packet size that buffers PIPE5 empty. When transfer direction When data stored buffers PIPE5 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE5 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_EMP_OVR4 (PIPE4 Buffer Empty/Size-Error Interrupt) Bits (b4) This indicates that received data size exceeds maximum packet size that buffers PIPE4 empty. When transfer direction When data stored buffers PIPE4 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE4 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_EMP_OVR3 (PIPE3 Buffer Empty/Size-Error Interrupt) Bits (b3) This indicates that received data size exceeds maximum packet size that buffers PIPE3 empty. When transfer direction When data stored buffers PIPE3 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE3 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect.
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PIPEB_EMP_OVR2 (PIPE2 Buffer Empty/Size-Error Interrupt) Bits (b2) This indicates that received data size exceeds maximum packet size that buffers PIPE2 empty. When transfer direction When data stored buffers PIPE2 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE2 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. PIPEB_EMP_OVR1 (PIPE1 Buffer Empty/Size-Error Interrupt) Bits (b1) This indicates that received data size exceeds maximum packet size that buffers PIPE1 empty. When transfer direction When data stored buffers PIPE1 have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size which been received exceeded packet size PIPE1 (size over detect), this "1". [1:0] bits PIPE Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing these bits affect. DCP_EMP_OVR (Default Control PIPE Buffer Empty/Size Error Interrupt) (b0) This indicates that received data size exceeds maximum packet size that transmit buffers empty. When transfer direction When data stored transmit buffers have been transmitted (buffer empty), this "1". When transfer direction OUT: When data packet size having been received exceeded preset value DCP_MXPS [6:0] Configuration Register (size over detect), this "1". this time, [1:0] bits Control Register "1X" (STALL). This cleared writing "0". This cleared when internal clock supplied (SCLK Transceiver Control Register "0".). Writing this affect.
Note clearing buffer empty interrupt status bits: order continuously clear status bits while status bits being multiplexed, access cycle time 100ns more required from clear next clear. example, where both PIPEB_EMP_OVR1 status PIPEB_EMP_OVR2 status simultaneously set, access cycle required from when written PIPEB_EMP_OVR1 until when written PIPEB_EMP_OVR2 100ns more. Also this time, able clear PIPEB_EMP_OVR1 PIPEB_EMP_OVR2 same time.
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M66591GP
2.28 Address Register
Address Register (USBAddress)
<Address: H'74>
USB_Addr [6:0]
15~7 USB_Addr [6:0] Address
name Reserved. "0". Read
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: H'0000>
address assigned host Write Invalid (Ignored when written)
USB_Addr [6:0] (USB Address) Bits (b6-b0) These bits store address which been assigned SET_ADDRESS device request host. These bits automatically respond SET_ADDRESS device request they renewed address completion control transfer status stage.
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2.29 Request Register
Request Register (USBReq0)
<Address: H'78>
bRequest [7:0]
bmRequestType [7:0]
15~8 bRequest [7:0] Request
name Read
Function Request received setup stage Write Invalid (Ignored when written)
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: H'0000>
bmRequestType [7:0] Request Type
Read Request type received setup stage Write Invalid (Ignored when written)
bRequest [7:0] (Request) Bits (b15-b8) These bits store bRequest device request received setup stage control transfer. bmRequestType [7:0] (Request Type) Bits (b7-b0) These bits store bmRequestType device request received setup stage control transfer.
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2.30 Request Register
Request Register (USBReq1)
<Address: H'7A>
wValue [15:0]
15~0 wValue [15:0] Value
name Read
Function Value received setup stage Write Invalid (Ignored when written)
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: H'0000>
wValue [15:0] (Value) Bits (b15-b0) These bits store wValue device request received setup stage control transfer.
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2.31 Request Register
Request Register (USBReq2)
<Address: H'7C>
wIndex [15:0]
15~0 wIndex [15:0] Index
name Read
Function Index received setup stage Write Invalid (Ignored when written)
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: H'0000>
wIndex [15:0] (Index) Bits (b15-b0) These bits store wIndex device request received setup stage control transfer.
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2.32 Request Register
Request Register (USBReq3)
<Address: H'7E>
wLength [15:0]
15~0 wLength [15:0] Length
name Read
Function Length received setup stage Write Invalid (Ignored when written)
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: H'0000>
wLength [15:0] (Length) Bits (b15-b0) These bits store wLength device request received setup stage control transfer.
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2.33 Configuration Register
Configuration Register (DCPCfg1)
<Address: H'82>
CNTMD
15~9 CNTMD
name Reserved. "0".
Function Non-continuous transmit/receive mode Continuous transmit/receive mode
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Continuous Transmit/Receive Mode Reserved. "0".
CNTMD (Continuous Transmit/Receive Mode) Bits (b8) These bits transmit/receive mode data stage control read/write transfer. case control read transfer: CNTMD "0": Non-continuous transmit mode transmit completes under conditions follows: Transmits data equivalent size DCP_MXPS [6:0] bits Configuration Register transmits short packet setting BVAL C_FIFO Port Control Register "1". writing completes under conditions follows: Writes buffer data equivalent size DCP_MXPS [6:0] bits. (BVAL changes "1"). Writes BVAL bit. CNTMD "1": Continuous transmit mode transmit completes under conditions follows: Transmits data equivalent size SDLN [8:0] bits Continuous Transmit Data Length Register transmits short packet setting BVAL "1". writing completes under conditions follows: Writes buffer data equivalent size SDLN [8:0] bits. (BVAL changes "1"). Writes BVAL bit. case control write transfer: CNTMD "0": Non-continuous receive mode. receive completes receiving packet under condition follows: Receives data equivalent size DCP_MXPS [6:0] bits Configuration Register Receives short packet. CNTMD "1": Continuous receive mode. receive completes receiving several packets under condition follows: Receives data equivalent bytes buffer size DCP. Receives short packet.
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2.34 Configuration Register
Configuration Register (DCPCfg2)
<Address: H'84>
DCP_MXPS [6:0]
15~7 DCP_MXPS [6:0]
name Reserved. "0".
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Upper limit transmit/receive data packet transfer (Settable only 8,16,32
Maximum Packet Size
DCP_MXPS [6:0] (DCP Maximum Packet Size) Bits (b6-b0) These bits upper limit (byte count) transmit/receive data packet transfer data stage. these bits, available during operation Full-Speed mode, during operation Hi-Speed mode. Other values permitted. time transmitting, data equivalent size these bits read from buffer transmission. When buffer does have data equivalent size these bits, data transmitted short packet. time receiving, data equivalent size these bits written buffer. received packet data larger than size these bits, DCP_EMP_OVR Interrupt Status Register "1". When initializing DCP, sure these bits before setting bits Control Register "01". Also, when changing value these bits, sure beforehand bits Control Register "00" (NAK).
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M66591GP
2.35 Control Register
Control Register (DCPCtrl)
BSTS
<Address: H'88>
SQCLR
NYETMD
CCPL
[1:0]
BSTS
name Control PIPE Buffer Status buffer
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: -000>
Disables read data buffer write data Enables read data buffer write data buffer
14~9
Reserved. "0". SQCLR Sequence Toggle Clear Write Invalid (Ignored when written) Sequence clear
Reserved. "0". NYETMD NYET Response Mode Automatic response Mode (ACK/NYET automatically selected.) response only mode (Always with response. NYET response.)
Reserved. "0". CCPL Control Transfer Completion Enable response status stage Normal completion response status stage (ACK response/zero-length packet transmit) response response STALL response
[1:0] Response
BSTS (Control PIPE Buffer Status) (b15) This indicates buffer status DCP. When ISEL C_FIFO Port Control Register "0", this indicates control write (OUT) buffer status. When ISEL "1", this indicates control read (IN) buffer status. SQCLR (Sequence Toggle Clear) (b8) This clears sequence sets data data stage "DATA1". Further, data setup stage status stage controlled hardware. sequence toggled hardware control transfers after sequence cleared. With reset, sequence toggle cleared. Further, with setup token having been received, sequence automatically cleared hardware data data stage "DATA1". Writing this invalid. This always read "0". Before setting this bit, sure [1:0] bits "00" (NAK). Note: clear more sequence toggle bits PIPE continuously, access cycle time 200ns more required from SQCLR PIPE access next SQCLR PIPE access. example, when sequence toggle bits both PIPE1 PIPE2 cleared, access cycle required from when written SQCLR PIPE1 when written SQCLR PIPE2 200ns more.
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M66591GP
NYETMD (NYET Response Mode) (b4) This sets NYET response mode. Automatic response mode (ACK/NYET automatically selected.) response only mode (Always with response. NYET response.) This valid when [1:0] bits "01"(BUF) case control write transfer operated Hi-Speed mode. other cases, this invalid. automatic response mode, hardware automatically selects appropriate response (NAK/ACK/NYET) according buffer statuses below. However, response executed instead NYET response when short packet received. When buffer receive data packet buffer full, response executed. When empty space existing buffer equal more than twice large packet size before receiving data packet, response executed. When empty space existing buffer less than twice large packet size before receiving data packet, NYET response executed. response only mode, device does transmit NYET packet. ACK/NAK response executed. CCPL (Control Transfer Completion Enable) (b2) This controls status stage control transfer. When this "1", operations below executed status stage control transfer notifies normal completion control transfer: When control write transfer, transmits zero-length packet after receiving token bits "01". When control read transfer, executes response host after receiving packet following token bits "01". When this "0", response executed host after receiving token/OUT token status stage control transfer. This automatically cleared receiving setup token. [1:0] (Response PID) Bits (b1-b0) These bits response host data/status stage control transfer. setup stage, response always executed independent these bits. Further, when receiving setup token, these bits automatically response ("00") hardware. When VALID to"1", writing these bits invalid. response response executed independent buffer status. response Either response, NYET response, response, DATA0 response, DATA1 response executed according value NYETMD sequence toggle bit, buffer status. STALL response STALL response executed independent buffer status. When data exceeding packet size (MXPS) been received sequence error occurred control write transfer, these bits automatically "1x".
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M66591GP
2.36 PIPE Configuration Select Register
PIPE Configuration Select Register (PipeCfgSel)
<Address: H'8C>
PIPE_SEL [2:0]
15~3 PIPE_SEL [2:0] PIPE Select
name Reserved. "0".
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset:
Designate PIPE access configuration register 000: 001: 010: 011: 100: 101: 110: 110-111: None select Select PIPE1 Select PIPE2 Select PIPE3 Select PIPE4 Select PIPE5 Select PIPE6 None select
PIPE_SEL [2:0] (PIPE Select PID) Bits (b2-b0) There "PIPE Configuration Register" each PIPE internal M66591. PIPE Configuration Window Register window register these registers. These bits designate PIPE PIPE configuration setting PIPE Configuration Window Register Refer Figure
PIPE Configuration Window Register
PIPE1 PIPE Configuration Register PIPE2 PIPE Configuration Register PIPE3 PIPE Configuration Register PIPE4 PIPE Configuration Register PIPE5 PIPE Configuration Register PIPE6 PIPE Configuration Register
PIPE Configuration Select Register
M66591
PIPE_SEL [2:0] bits
Figure reference PIPE configuration
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M66591GP
2.37 PIPE Configuration Window Register
PIPE Configuration Window Register (PipeCfgWin0)
<Address: H'90>
ITMD
BFRE
EP_NUM [2:0]
DBLB CNTMD
PIPE Enable
name Disable PIPE Enable PIPE
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: B'00-
Reserved. "0". ITMD Interrupt Transfer Toggle Mode Enable toggle mode Disable toggle mode This function only used PIPE5 PIPE6
12~11
Reserved. "0". BFRE Buffer Ready Interrupt Mode DBLB Double Buffer Mode (Bulk Transfer Only) CNTMD Continuous Transmit/Receive Mode mode mode Single buffer mode Double buffer mode Non-continuous transmit/receive mode Continuous transmit/receive mode this
<During operation Full-Speed mode>
<During operation Hi-Speed mode> Reserved. "0". Transfer Direction Reserved. "0". EP_NUM [2:0] Endpoint Number Read 000: select PIPE 001: (PIPE1) 010: (PIPE2) 011: (PIPE3) 100: (PIPE4) 101: (PIPE5) 110: (PIPE6) Other than those above: Invalid Write Invalid (Ignored when written) (Receives data from host) (Transmits data host)
(PIPE Enable) (b15) This sets enable/disable using PIPE having been selected PIPE_SEL [2:0] bits PIPE Configuration Select Register. Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~6) "00" (NAK).
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M66591GP
ITMD (Interrupt Transfer Toggle Mode) (b13) This sets enable/disable data resend function interrupt transfer. This valid only PIPE5 PIPE6. written this ignored PIPE1 PIPE4 which concern bulk transfer, which this "0". When interrupt transfer toggle mode disabled, data transmitted next transmission toggling data buffer, even received after transmitting data. this case, BVAL C_FIFO Port Control Register cleared PIPEB _RDY Interrupt Status Register "1". When interrupt transfer toggle mode enabled, normal toggle sequence executed. When transmission completes normally, date buffer toggled transmit next data. case cannot received after data transmitted, date buffer toggled, same data buffer resent. Before setting this bit, sure [1:0] bits PIPE Control Register (i=5~6) "00" (NAK). BFRE (Buffer Ready Interrupt Mode) (b10) This sets operation mode buffer ready interrupt when PIPE been OUT. mode mode details, refer "3.3.6 PIPE Buffer Ready Interrupt". This valid only PIPE1 PIPE4. written this ignored PIPE5 PIPE6. Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~4) "00" (NAK). DBLB (Double Buffer Mode (Bulk Transfer Only)) (b9) This sets PIPE single buffer mode double buffer mode. This valid only PIPE1 PIPE2. written this ignored PIPE3 PIPE6 which concern single buffer configuration Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~2) "00" (NAK). CNTMD (Continuous Transmit/Receive Mode) (b8) This sets transmit/receive mode bulk transfer. This valid only PIPE1 PIPE4. written this ignored PIPE5 PIPE6. During operation Full-Speed mode CNTMD "0": Non-continuous transmit/receive mode transmit completes under following conditions when setting PIPE Transmits data equal bytes Transmits short packet transmits zero-length packet writing completes under following conditions when setting PIPE Writes buffer data equal bytes Writes BVAL C_FIFO Port Control Register receive completes under following conditions when setting PIPE OUT: Receives data equal bytes Receives short packet receives zero-length packet CNTMD "1": Continuous transmit/receive mode transmit completes under following conditions when setting PIPE data equal bytes automatically transmitted multiple times data equal bytes transmitted. Transmits short packet transmits zero-length packet writing completes under following conditions when setting PIPE numbers data writing buffer equal bytes Write BVAL bit. receive completes under following conditions when setting PIPE OUT: data equal bytes automatically received multiple times data equal bytes received. Receives short packet receives zero-length packet When value been TRCNT [15:0] D0_FIFO Port Control Register correspondent with number packet receipts. Only non-continuous transmit/receive mode enables operated during operation Hi-Speed mode. this case, however, this needs "1". Rev.1.00 Nov. 2004 page
M66591GP transmit completes under following conditions when setting PIPE Transmits data equal bytes Transmits short packet transmits zero-length packet writing completes under following conditions when setting PIPE Writes buffer data equal bytes Writes BVAL C_FIFO Port Control Register receive completes under following conditions when setting PIPE OUT: Receives data equal bytes Receives short packet transmits zero-length packet Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~4) "00" (NAK). (Transfer Direction) (b4) This sets transfer direction PIPE. This valid only PIPE1 PIPE4. written this ignored PIPE5 PIPE6 which concern direction setting. After switching transfer direction, clear buffer BCLR bits C_FIFO Port Control Register D0_FIFO Port Control Register Before setting this bit, sure [1:0] bits PIPE Control Register (i=1~4) "00" (NAK). EP_NUM [2:0] (Endpoint Number) Bits (b2-b0) These bits read endpoint number PIPE having been PIPE_SEL [2:0] bits PIPE Configuration Select Register. endpoint number fixed, same PIPE number. endpoint number PIPE1 (EP1). endpoint number PIPE2 (EP2). endpoint number PIPE3 (EP3). endpoint number PIPE4 (EP4). endpoint number PIPE5 (EP5). endpoint number PIPE6 (EP6). These bits read only. writing ignored.
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M66591GP
2.38 PIPE Control Register (i=1~4)
PIPE Control Register (Pipe1Ctrl) PIPE Control Register (Pipe2Ctrl) PIPE Control Register (Pipe3Ctrl) PIPE Control Register (Pipe4Ctrl)
BSTS
<Address: H'A0> <Address: H'A2> <Address: H'A4> <Address: H'A6>
NYETMD
ACLR SQCLR
[1:0]
BSTS Buffer Status
name buffer
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: -00>
Disables read data buffer write data Enables read data buffer write data buffer
14~10
Reserved. "0". ACLR Buffer Automatic Clear Mode Write Disable buffer automatic clear Enable buffer automatic clear
SQCLR Sequence Clear
Write Invalid Sequence clear
Reserved. "0". NYETMD NYET Handshake Mode Automatic response mode (ACK/NYET automatically selected.) response only mode (Always with response. NYET response.)
Reserved. "0". [1:0] Response response response STALL response
BSTS (Buffer Status) (b15) This indicates buffer status PIPE1 PIPE4. ACLR (Buffer Automatic Clear Mode) (b9) When this "1", buffers CPU-side/SIE-side cleared. This automatically cleared completion buffer clear, make sure write after setting "1". When [1:0] bits "01" (BUF) during setting buffer this "1", response executed received token. response returned host after data being received. this time, this received data written buffer. Also, when [1:0] bits have been sets "00"/"1x" (NAK/STALL), NAK/STALL response executed. Only SIE-side buffers write completion CPU-side buffer cleared setting this during setting buffer. clear SIE-side buffers, follow procedure below. [1:0] bits "00" (NAK) This This cleared [1:0] bits "01" (ACK)
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M66591GP
SQCLR (Sequence Clear) (b8) This clears sequence PIPE1 PIPE4 next data "DATA0". sequence toggled through hardware control transfers after sequence cleared. With reset, sequence toggle cleared. necessary clear sequence software. Writing this invalid. This always read "0". Before setting this bit, sure [1:0] bits "00" (NAK). Note: clear more sequence toggle bits PIPE continuously, access cycle time 200ns more required from SQCLR PIPE access next SQCLR PIPE access. example, when sequence toggle bits both PIPE1 PIPE2 cleared, access cycle required from when written SQCLR PIPE1 when written SQCLR PIPE2 200ns more.
NYETMD (NYET Handshake Mode) (b4) This sets NYET response mode. Automatic response mode (ACK/NYET automatically selected.) response only mode (Always with response. NYET response.) This valid when [1:0] bits transfer "01"(BUF) case bulk transfer operated Hi-Speed mode. other case, this invalid. automatic response mode, hardware automatically selects appropriate response (NAK/ACK/NYET) according buffer status below: When buffer receive data packet buffer full, response executed. When empty space existing buffer equal more than twice large packet size before receiving data packet, response executed. When empty space existing buffer less than twice large packet size before receiving data packet, NYET response executed. response only mode, device does transmit NYET packet. ACK/NAK response executed. [1:0] (Response PID) Bits (b1-b0) These bits response PIPE1 PIPE4. response response executed irrespective buffer status. response response selected according buffer status, value NYETMD value sequence toggle bit. When NYETMD "00" bulk transfer, NYET response executed following conditions: When non-continuous transmit/receive mode single buffer mode. When buffer CPU-side empty non-continuous transmit/receive mode double buffer mode before receiving data packet. STALL response STALL response executed irrespective buffer status. When data packet exceeding packet size (512 bytes when Hi-Speed, bytes when Full-Speed) PIPE1 PIPE4 been received while setting transfer direction PIPE OUT, these bits automatically "1x". STALL response, follow procedure below accordance with this value before setting: "10" when [1:0] "00" "11" when [1:0] "01"
Rev.1.00 Nov. 2004 page
M66591GP
2.39 PIPE Control Register (i=5~6)
PIPE Control Register (Pipe5Ctrl) PIPE Control Register (Pipe6Ctrl)
BSTS
<Address: H'A8> <Address: H'AA>
ACLR SQCLR
[1:0]
BSTS Buffer Status
name buffer
Function
<H/W reset: H'0000> <S/W reset: H'0000> <USB reset: -00>
Disables read data buffer write data Enables read data buffer write data buffer
14~10
Reserved. "0". ACLR Buffer Automatic Clear Mode Write Disable buffer automatic clear Enable buffer automatic clear
SQCLR Sequence Clear
Write Invalid Sequence clear
Reserved. "0". [1:0] Response response response STALL response
BSTS (Buffer Status) (b15) This indicates buffer status PIPE5 PIPE6. ACLR (Buffer Automatic Clear Mode) (b9) When this "1", buffers CPU-side/SIE-side cleared. This automatically cleared completion buffer clear, make sure write after setting "1". Only SIE-side buffers write completion CPU-side buffer cleared setting this bit. clear SIE-side buffers, follow procedure below. [1:0] bits "00" (NAK) This sets This cleared [1:0] bits "01" (ACK) SQCLR (Sequence Clear) (b8) This clears sequence PIPE5 PIPE6, next data "DATA0". sequence toggled through hardware control transfers after sequence cleared. With reset, sequence toggle cleared. necessary clear sequence software. Writing this invalid. This always read "0". Before setting this bit, sure [1:0] bits "00" (NAK). Note: clear more sequence toggle bits PIPE continuously, access cycle time 200ns more required from SQCLR PIPE access next SQCLR PIPE access. example, when sequence toggle bits both PIPE1 PIPE2 cleared, access cycle required from when written SQCLR PIPE1 when written SQCLR PIPE2 200ns more.
Rev.1.00 Nov. 2004 page
M66591GP
[1:0] (Response PID) Bits (b1-b0) These bits response PIPE5 PIPE6. response response executed independent buffer status. response response selected according buffer status value sequence toggle bit. STALL response STALL response executed independent buffer status. STALL response, follow procedure below accordance with this value before setting. "10" when [1:0] "00" "11" when [1:0] "01"
Rev.1.00 Nov. 2004 page
M66591GP
M66591
OPERATIONS
System Control
3.1.1 Clock
M66591 able crystal oscillator external clock input. Oscillation factor selected XTAL [1:0] bits Transceiver Control Register internal clock supply disable enable controlled XCKE bit, RCKE bit, SCKE Transceiver Control Register clock control diagram shown Figure 3.1.
Clock Control Block XCKE (bit13)
Enable/Disable
RCKE (bit12)
Enable/Disable
PLLC (bit11)
SCKE (bit10)
Enable/Disable
Enable/Disable
Input Clock
Oscillation Buffer
Clock Generator
Factor
Internal Clock
Xtal (bit15 bit14) Reference Clock
Figure M66591 clock control diagram
When enable disable clock oscillation, clock stable waiting time necessary enabling disabling these bits mentioned above. process order waiting time shown
Table process order waiting time enabling disabling clock
Operation Enable Clock Oscillation Process Order XCKE RCKE PLLC SCKE Disable Clock Oscillation SCKE PLLC RCKE XCKE Waiting Time After Setting 1.5ms (Unnecessary when external clock input) -8.3µs -3µs
Note: Because waiting time difference according used crystal oscillator, necessary appropriate oscillation waiting time evaluation. necessary bits which described below before enabling clock supply. Xtal [1:0] bits, USBE Transceiver Control Register LDRV Data FIFO/DMA Control Configuration Register DreqA Data FIFO/DMA Control Configuration Register INTL INTA Configuration Register
Rev.1.00 Nov. 2004 page
M66591GP
3.1.2
Reset
M66591 three types reset, hardware reset, software reset register setting (USBE bit), reset. hardware reset will clear value register. software reset retains values Transceiver Control Register0, Transceiver Control Register Data FIFO/DMA Control Configuration Register Data FIFO/DMA Control Configuration Register Data FIFO/DMA Control Configuration Register C_FIFO Port Register D0_FIFO Port Register Interrupt Configuration Register reset, register values excepting those HS/FS Mode Register, Address Register, Request Register Request Register Request Register Request Register bits CCPL Control Register bits PIPE Control Register 1-6) retained. details reset state, refer each register.
3.1.3
Pull-up Resistor Control
M66591 includes TR_ON output power source (+3.3V) line pull-up input control pull-up ON/OFF. 1.5K resistors pull line connected between TR_ON pin, controlling pull-up ON/OFF RpuE Transceiver Control Register connection pull-up resistor peripheral connection connector, refer Figure 3.2. (The VBUS must connected 1~10µF capacitor conforming Universal Serial Specification Revision 2.0.)
VBUS 1~10µF
lines need impedance
TR_ON 1.5K 1.2K REFIN
control processing.
Vbus
Connector
M66591
Figure Connection M66591 Connector
Rev.1.00 Nov. 2004 page
M66591GP
M66591 Initial Setting Clock Control
This chapter explains method initial setting, detection method attach/detach host, execution method clock control remote wakeup suspend/resume concerning M66591.
3.2.1
M66591 Initial Setting
initial setting process M66591, operation enabled input VBUS confirmed polling VBUSSTS Interrupt Status Register According input status VBUS pin, either VBUS interrupt waiting process attach processing executed. VBUSSTS "0", M66591 connected host, enable VBUS interrupt wait connection host. VBUSSTS "1", M66591 already connected host before initial setting, execute attach processing. detailed process flowchart shown Figure 3.3. Further, VBUS directly input from VBUS connector, chattering removal process software required confirmation input status.
Initial
Clearing registers
Clear necessary registers M66591.
Setting XTAL
Enable clock M66591 according oscillator used system.
Enabling ope
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