Facsimile Image Data Processor REJ03F0276-0200 Rev.2.00 2008

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Facsimile Image Data Processor REJ03F0276-0200 Rev.2.00 2008

Datasheet Thumbnail

Top Searches for this datasheet

M66335FP
Facsimile Image Data Processor
REJ03F0276-0200 Rev.2.00 2008
M66335 facsimile image processing controller turn into binary signals analog signals which have been output through photo-electric conversion image sensor. image processing functions includes peak value detection, uniformity correction, resolution change, compensation, correction, detection background/character levels, error diffusion, separation image zones, designation regions. This controller contains only analog processing circuit, converter 7-bit flash type image processing memory, also image sensor interface circuit CODEC (Coder Decoder). Therefore, this alone capable image processing.
Features
High speed scan (Max ms/line, ms/line) Compatibility with pixels/mm, pixels/mm) image sensor Generation control signals image sensor (CCD, CIS) CCD: CK1, CK2, contact sensor (CIS): CK1, Built-in analog processing circuit (equivalent M64291) Sample hold circuit Gain control circuit Black level clamping circuit Reference internal power supply converter Built-in converter 7-bit flash type Built-in image processing memories Uniformity correction memory, Line memory, Error memory, correction memory External output interface converted binary data Serial output M66330) output External output interface multivalued data transfer data compensated uniformity Various image processing functions Uniformity correction Resolution change from 200% step) compensation (2-dimensional processing, capable correction each character/photo) correction (capable correction each character/photo) Detection background/character levels Change pseudo-halftone Error diffusion tone steps through 6-bit processing) Organized dither tone steps through matrix) Image zone separation (2-dimensional processing) single power supply
Application
Facsimile, word processor image scanner
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Block Diagram
ADIN Vri+ Vri-
AVcc
DVcc
Analog control
Image processing sequence control signal
SYSCK ACCK
LEVAJ BCMI BCMV GCAO BCMO PTIMB
7-bit converter Analog signal processing circuit
Image zone separation
Detection background/ character levels Resolution change compensation Selection conversion binary processing
Image interface
Uniformity correction
correction table
SRDYB SVID SCLK STIMB DAKB RESETB
Error diffusion control
Sensor control
Correction data memory
Conversion table memory
Line memory
Error memory
Dither matrix
Organized dither
interface
AGND
DGND
Arrangement
interface TEST6 TEST5 TEST4 TEST3 TEST2 Test TEST1 TEST0 TESTI TESTO
interface
interface System clock
RESET SYSCK
M66335FP
DGND DVCC black reference output white reference output ADIN input AVCC Vri+ white reference input AGND Vri- black reference input BCMO BCMV Control signal BCMI analog signal processing
Single-line ACCK cycle clock SVID CODEC SCLK interface STIM SRDY Sensor PTIM interface Sensor interface AVCC Control LEVAJ signal analog signal AGND processing GCAO
Connection
(Top view)
Outline: PRQP0080GB-A (80P6N-A)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Table Image Processing Functions
Image Processing Functions Reading range Resolution Reading speed Uniformity correction correction Specifications Remarks
pixels/mm, pixels/mm
(for horizontal scanning direction)
Typ: ms/line; Max: ms/line White correction, black correction Correction range: Logarithmic correction
Controlled through system correction memory built-in Capable correction each
character/photo Correction memory built-in Capable correction each character/photo clock Correction memory built-in Readable from/writable
compensation
Laplacian filter circuit through 2dimensional processing
Simple conversion binary
Floating slice system through
detection circuit background/character levels
Pseudo-halftone
Error diffusion: 6-bit processing (for
tone steps) Organized dither: matrix (for tone steps) luminance difference
Error buffer memory built-in bits dither memory
built-in
Image zone separation Image reduction
2-dimensional processing through Range reduction rate:
100% step)
Capable outputting average
line dropped line subsequent line instead both lines
Image enlargement
Range enlargement rate: 100%
200% step)
Capable outputting average
line repeated line subsequent line instead repeated line
Image sensor control signal Analog processing
image sensor (clock duty: 75%) image sensor sample/hold circuit, gain control
amplifier, black level clamping circuit, 7-bit converter built-in.
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Item Sensor interface Name Input/Output Output Function Outputs shift pulse signal transfer electric charges from sensor's photoconductor component transferring component start signal start sensor reading circuit CIS. Outputs clock pulse signal sequentially transfer signaling electric charges from sensor's transferring component clock pulse signal shift register sensor reading circuit CIS. Reversed-phase pulses Outputs reset pulse return voltage floating capacitor sensor initial one. Outputs pulse motor control signal reading roller. Transfer start ready signal data from CODEC Defines data transfer section CODEC Clock signal transfer image data CODEC Outputs image data serial CODEC request signal external controller output parallel image data through acknowledge signal from external controller response above signal Single-line termination interrupt System clock input Single-line cycle clock Input system reset. cycle counter, register, F/F, latch reset. Chip select signal access M66335 Control signal read data from M66335 Control signal write data M66335 Address signal access various registers inside M66335 8-bit buffer Positive power supply Test input pin. Hold this "L". Test output pin. this open. Analog power supply (rated supply voltage: Digital power supply (rated supply voltage: Analog ground Digital ground input analog signals output from (Signals from input through capacity coupling those from CIS, with clamping levels, input directly.) control frequency characteristic gain control circuit control level output signals gain control circuit. output voltage, VGCAO, obtained following equation: VGCAO VLEVAJ VIN, where, VLEVAJ: voltage LEVAJ VIN: input signal gain gain control circuit signal element corresponding signal level clamped through input clamping circuit CIS3 input level CIS1 CIS2 input. Signal output gain control circuit
Output
PTIM SRDY STIM SCLK SVID SYSCK ACCK RESET Others TESTI, TESTO AVCC DVCC AGND DGND
Output Output Output Input Output Output Output Output Input Output Input Output Input Input Input Input Input Input/Output Input Output Input
CODEC interface
interface
Clock interface
Power supply Sensor signal input part Gain control circuit
LEVAJ
Input Input
GCAO
Output
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Description (cont.)
Item Black level clamping circuit Name BCMI BCMV BCMO Vri+ Input/Output Input Input Output Input Function Signal input black clamping circuit. this with capacity coupling with GCAO pin. black level clamping voltage. Sets black level signals output from BCMO signal processing. Signal output black level clamping circuit Output circuit generate full-scale point reference voltage (3.8 Connected with through buffer inside change reference voltage range, input voltage from this pin. Output circuit generate zero point reference voltage (1.8 Connected with through buffer inside change reference voltage range, input voltage from this pin. Signal input converting circuit. this connecting with BCMO with GCAO CIS. Input signals voltage range (1.8 through VBL. Output circuit generating full-scale reference voltage (3.8 Connected inside with converter. Output circuit generating zero point reference voltage (1.8 Connected inside with converter.
converter
Vri-
Input
ADIN
Input
Output Output
Absolute Maximum Ratings
+75°C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Analog supply voltage Supply voltage Reference voltage (white) Reference voltage (black) Analog input voltage Storage temperature Symbol AVCC DVCC VAIN Tstg Ratings -0.3 +6.5 -0.3 -0.3 AVCC -0.3 AVCC -0.3 AVCC +150 Unit
Recommended Operational Conditions
Item Supply voltage (for digital system component) voltage Input voltage Analog supply voltage Analog voltage Supply voltage (for digital system component) voltage Input range: AVCC; AGND Operating temperature Note: Symbol AVCC AGND DVCC DGND VAIN Topr 4.75 4.75 4.75 5.25 5.25 5.25 Unit Vp-p
Connect analog system component digital system component separately power supply evaluation board noise prevention.
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Electrical Characteristics
+75°C, unless otherwise noted)
Item input voltage input voltage Positive direction input threshold Negative direction input threshold Hysteresis value output voltage output voltage output voltage output voltage input current input current input current state input current state Analog input current Reference resistance Differential non-linear error Static current dissipation (during standby) Symbol IOZH IOZL IAIN ICCS ±1.0 0.55 0.55 -1.0 -5.0 Unit 5.25 VCC, Test Conditions
5.25 5.25 5.25 5.25 5.25 5.25
Timing Conditions
+75°C, unless otherwise noted)
Item System clock cycle System clock pulse width System clock pulse width System clock rise time System clock fall time Read pulse width Set-up time before read Set-up time before read Set-up time before read Hold time after read Hold time after read Hold time after read Write pulse width Set-up time before write Set-up time before write Set-up time before write Hold time after write Hold time after write Hold time after write Hold time after STIM SRDY Symbol (SYS) (SYS) (SYS) (SYS) (SYS) (RD) (CS-RD) (A-RD) (DAK-RD) (RD-CS) (RD-A) (RD-DAK) (WR) (CS-WR) (A-WR) (D-WR) (WR-CS) (WR-A) (WR-D) (STIM-SRDY) Unit
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Switching Characteristics
+75°C, unless otherwise noted)
Item Enable time data output after read Disable time data output after read Propagation time output after read Symbol tPZL (RD-D) tPZH (RD-D) tPLZ (RD-D) tPHZ (RD-D) tPHL (RD-DRO) Unit Test Conditions
Test Circuit
Input Output Tested device
Item tPLH, tPHL tPLZ tPHZ tPZL tPZH
Open Closed Closed Closed Open
Open Open Closed Open Closed
Characteristics (10% 90%) pulse generator (PG): Capacitance includes stray capacitance connections input capacitance probe.
System Clock
(SYS) (SYS) (SYS) (SYS) SYSCK
(SYS)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Operation Mode
M66335 three basic operations. Peak value detection: Adjusting peak value analog signals output from analog circuit white reference voltage (VWL) converter built M66335. Generation data uniformity correction: Generating data white reference original sheet uniformity correction sensor unit writing them memory correction built-in M66335. Read: Reading original sheets, performing image processing read image data, outputting serial parallel indicated converted binary data. M66335 capable performing transfer multivalued data (6-bit data after correction about uniformities. These three basic operations performed following mode sequences sensor sensor. sensor through register (SENS). Sensor
mode
peak value line cycle detected setting command register "H". escape this mode, command after line cycle cycle lines more) passed since start. This operation mode started setting UNIF command register after setting UMODE: (white correction) register UNIFM: (only white correction) register Starting UNIF command also makes system generate data nonuniformity correction white correction (for line cycle). escape this mode, UNIF command after line cycle cycle lines more) passed since start. read operation mode started setting SCAN command register "H". escape this mode, SCAN command "L".
UNIF mode (white)
SCAN mode
Sensor
mode
peak value line cycle detected setting command register "H". escape this mode, command after line cycle cycle lines more) passed since start. When this operation mode started UNIF command after setting UMODE: (black correction) register UNIFM: (black white correction) register system also generates black data nonuniformity correction black correction (for line cycle). escape this mode, UNIF command after line cycle cycle lines more) passed since start. case only white correction, setting necessary. Follow instruction below. When this operation mode started UNIF command register after setting UMODE: (white correction) register UNIFM: (only white correction) register system also generates white data non-uniformity correction white correction (for line cycle). escape this mode, UNIF command after line cycle cycle lines more) passed since start. reading operation started setting SCAN command register "H". escape this mode, SCAN mode "L". signal operations data flow each basic operation shown page flowchart page
UNIF mode (black)
UNIF mode (white)
SCAN mode
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Operations Signals Peak Value Detection Operation
BCAO GCAO VWL, ADIN Vri+, Vri-
Analog control
Image processing sequence control signal
Image zone separation
ACCK SYSCK STIMB SCLK SVID
BCMV BCMI LEVAJ
Image sensor
Analog signal processing circuit
7-bit converter
Detection background/ character levels
Uniformity correction
Resolution change
compensation
correction table
Error diffusion
Selection processing conversion binary
Image interface
control Dither matrix Organized dither
PTIMB
Sensor control
Correction data memory
Conversion table memory
Line memory
Error memory
interface
SRDYB DAKB RESETB
CODEC
Flow Data Creation Data Uniformity Correction
BCAO GCAO VWL, Vri+, Vri-
ADIN
Analog control
Image processing sequence control signal
Image zone separation
Detection background/ character levels
ACCK SYSCK STIMB SCLK SVID
BCMV BCMI LEVAJ
Image sensor
Analog signal processing circuit
7-bit converter
Uniformity correction
Resolution change
compensation
correction table
Error diffusion
Selection processing conversion binary
Image interface
control Correction data memory Conversion table memory Line memory Error memory Dither matrix Organized dither
PTIMB
Sensor control
interface
SRDYB DAKB RESETB
CODEC
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Flow Data Reading Operation (for Output Serial: Binary Data)
BCAO GCAO VWL, Vri+, Vri- ACCK SYSCK STIMB SCLK SVID
Detection background/ character levels
ADIN
Analog control
Image processing sequence control signal
Image zone separation Selection processing conversion binary Image interface
BCMV BCMI LEVAJ
Image sensor
Analog signal processing circuit
7-bit converter
Uniformity correction
Resolution change
compensation
correction table
Error diffusion
control Dither matrix Organized dither
PTIMB
Sensor control
Correction data memory
Conversion table memory
Line memory
Error memory
interface
SRDYB DAKB RESETB
CODEC
image data correction compensation data
Flow Data Reading Operation (for Output Parallel: Binary Data)
BCAO GCAO VWL, Vri+, Vri- ACCK SYSCK STIMB SCLK SVID
Detection background/ character levels Selection processing conversion binary
ADIN
Analog control
Image processing sequence control signal
Image zone separation Image interface
BCMV BCMI LEVAJ
Image sensor
Analog signal processing circuit
7-bit converter
Uniformity correction
Resolution change
compensation
correction table
Error diffusion
control Dither matrix Organized dither
PTIMB
Sensor control
Correction data memory
Conversion table memory
Line memory
Error memory
interface
SRDYB DAKB RESETB
CODEC
image data correction compensation data
Flow Signals Reading Operation (for Multivated Data)
BCAO GCAO ADIN VWL, Vri+, Vri- ACCK SYSCK STIMB SCLK SVID
Detection background/ character levels
Analog control
Image processing sequence control signal
Image zone separation Selection processing conversion binary Image interface
BCMV BCMI LEVAJ
Image sensor
Analog signal processing circuit
7-bit converter
Uniformity correction
Resolution change
compensation
correction table
Error diffusion
control Correction data memory Conversion table memory Line memory Error memory Dither matrix Organized dither
PTIMB
Sensor control
interface
SRDYB DAKB RESETB
CODEC
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Line Cycle Reading Sequence
relationship between line cycle reading sequence M66335 shown figure relationship between CODEC interface operations reading sequence shown figure that between interface operations reading sequence shown figure Single-line cycle (1/ACCK) Defines processing time line M66335. single-line cycle decided line cycle counter value registers (PRE_DATA), pixel transfer clock. pixel transfer clock 1/16 SYSCK. line cycle (1/ACCK) [NS] line cycle counter value pixel transfer clock cycle [NS] (PRE_DATA pixel transfer clock cycle [NS] (PRE_DATA 16/SYSCK [NS] After loading PRE_DATA value, line cycle counter generates addresses following gate signals while counting down with pixel transfer clock. Sensor start pulse (SH) Image sensor start pulse. point start pulse decided uniformity correction range (UNIFG) value register [ST_PL] ST_PL value must according following formulas each image sensor type. CCD: ST_PL dummy pixels sensor CIS: ST_PL Uniformity correction range (UNIFG) Defines range where uniformity correction performed. This range corresponds width sensor A4). relationship between sensor width uniformity correction range, table range (AGCG) Defines range where peak value detection performed. This range corresponds sensor width A4). Auto gain control performed whole width sensor (solid line) mode narrower width (dashed line) than sensor width SCAN mode. relationship between sensor width range, table Original sheet reading width Defines reading width original sheets. original sheet widths narrower than sensor width, reading range (dashed line) set, using sensor center base center point. Therefore, points original sheet should based sensor center. relationship between sensor width original sheet reading width, table Pulse motor control signal (PTIM) Generates control signals pulse motor reading roller.
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
PRE_DATA loading Countdown Line cycle (ACCK) Sensor start pulse (SH) ST_PL Uniformity correction range (UNIFG) range (AGCG) Register (SENS_W) Registers (PRE_DATA) Register (SENS_W) Register (ST_PL) Relationship with registers
Register (SENS_W) Register (SOURCE) Register (SENS_W) Register (OFFSET)
Original sheet reading range Pulse motor control (PTIM) line cycle
Figure Line Cycle Reading Sequence
ACCK SRDYB <SRDYB> (SSCAN) STIMB SCLK SVID PTIMB <INTCLR> Output section <INTCLR> Register setting (SSCAN) Internal signal
SRDYB: taken with flow when scanning started PTIMB output. (SSCAN: During period that STIMB converted binary data output. SRDYB: taken with flow ACCK, when reading line ends. (SSCAN: asserted with flow SSCAN. (INT: When ready reading next line, INTCLR generated negated, then SRDYB
Figure CODEC Interface Operations Reading Sequence (Binary Data Output: Serial Output)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
ACCK <SRDYB> (SSCAN)
DAKB (Counter reset) (DMAFIN) <INTCLR> PTIMB
Output section <SRDYB>, <INTCLR> Register setting (SSCAN), (DMAFIN), (counter reset) Internal signal
SRDYB: taken with flow when scanning started PTIMB output. (SSCAN: SRDYB: taken with flow ACCK, when reading line ends. (SSCAN: internal counter reset signal generated with flow SSCAN, asserted with flow SSCAN. After internal counter reset, transfer started. (The internal counter counted each time pixel transferred.) When value internal counter reaches output pixel number, DMAFIN shifts negated with flow form DMAFIN asserted with flow DMAFIN. When ready reading next line, INTCLR generated negated, then SRDYB
Figure Interface Operations Reading Sequence (Multivated Data Output) Table Gate Signal Ranges Sensor Widths
Sensor Width Gate Signal Uniformity correction range (UNIFG) range (AGCG) mode SCAN mode Resolution 2103/55 4207/111 2103/55 4207/111 2018/130 4037/261 1943/215 3887/431 1943/215 3887/431 1584/564 3169/1129
Table Original Sheet Reading Widths According Original Sheet Widths Sensor Widths
Sensor Width Original Sheet Width Resolution 2102/54 4206/110 2102/54 4206/110 1942/214 3886/430
When original sheets narrower than sensor width, original sheet width with registers (OFFSET, OUTLENGTH): (Region designation function)
Left address Right address
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Image Processing Function
M66335 converts image signals input from image sensor into binary data. This includes simple conversion characters change images with various densities into pseudo-half-tone. Before conversion, distortions characteristic degradations which signals from image sensor almost always have must corrected compensated. Image zone separation must also performed realize optimal conversion-to-binary image possible shortest transmission time. Functions required image processing follows. Peak value detection Uniformity correction Resolution change (enlargement, reduction averaging) compensation correction Background/character level detection (simple conversion binary) Change pseudo-halftone Organized dither Error diffusion Image zone separation Designation regions Peak Value Detection Because converter M66335 uses input dynamic range Vp-p, reference voltages (VWL, VBL) corresponding peak value fixed. peak value analog signals output from analog processing circuit must detected before those signals input converter order adjust analog signal peak value full-scale value converter. peak value detection performed reading white data from sensor mode selected from three modes (AGC, UNIF SCAN) M66335. shown figure preprocessing peak value detection increase gain gain control performed line cycle gain control processing decrease gain when converter over-flows performed another line cycle after start command (register AGC) mode. result, gain changes shown figure
Peak value detection Line cycle
Preprocessing peak value detection (increasing gain)
Gain control peak value (decreasing gain)
Figure Peak Value Detection
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Preprocessing peak value detection After completion preprocessing peak value detection White data output level last pixel line adjusted VWL. line line peak value sensor output line adjusted VWL. Gain control peak value After completion gain control peak value
Figure Changes Gain Peak Value Detection
Uniformity Correction Uniformity correction correct shading distortion less light each light source faded light around lens, high frequency distortion characteristic variations pixel pixel image sensor. shown figure M66335 makes blocks each pixels, creates uniformity correction data each block, write them built-in correction memory (SRAM: 1024 word bits) UNIF mode selected from three modes (AGC, UNIF SCAN). correction data created each pixels read from built-in correction memory correct input image data consecutively SCAN mode. With register (UNIFS) "1", uniformity implemented. With register (RES) "1", uniformity correction performed block pixels. uniformity correction, white correction combination black correction white correction selected according types image sensors shown table This register (SENS, UMODE) register (UNIFM). perform both black correction white correction, black correction must done first. M66335 implements correction correction range shown figure white correction data beyond correction range 50%, correction exactly performed shown figure Therefore, ensure that input signals within range.
Black level
High frequency distortion Shading distortion
White level
line
Figure Waveform White Data Output from Image Sensor
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Table Uniformity Correction Image Sensor
Register Type Sensor Register (SENS) Creation Uniformity Correction Data Register (UMODE) Period black correction: Period white correction: Selection Correction Mode Register (UNIFM)
Image Sensor
Correction White correction White correction Black correction White correction
White correction black correction Analog signal input White data
White correction Analog signal input White data
Black data line
line
Correction over-range data white correction) Analog signal input White data
White data over correction range
Section over correction range line
Figure Uniformity Correction
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Resolution Change Resolution change controlled through horizontal scanning direction through vertical scanning direction. sequence resolution change shown figure
Horizontal Scanning Direction scaling factor written from register (CNV_D) built-in resolution change memory (100 bit) operations. MSSEL register must (which specifies horizontal scanning direction) before scaling factor written memory. procedure specify CNV_D follows.
Case Reduction Data written resolution change memory have following meaning. "0": pixel output. "1": pixel output. (Example reduction 75%) written memory. intervals should equal possible obtain image with better quality.
Case Enlargement Data written resolution change memory have following meaning. "0": pixel output. "1": pixels output. (Example enlargement 150%) written memory. intervals should equal possible obtain image with better quality reduction.
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Vertical Scanning Direction Processing lines implement scaling factor vertical scanning direction decided each line through register. MSSEL register must (which specifies vertical scanning direction), either written register (CNV_D) before processing each line. timing this setting period between first transition signal (synchronized with that ACCK) that signal (the start taking SRDY signal in). procedure specify CNV_D follows.
Case Reduction CNV_D indicates current line read. "0": line data output. "1": line data output.
Case Enlargement CNV_D indicates next line read. "0": line data output with PTIM generated (paper driven). "1": line data output with PTIM generated (paper driven). (Paper driven: same line read again.)
Resolution change
Enlargement/reduction CONVX/CONVY.
Specifying enlargement/reduction horizontal/vertical scanning Specifying horizontal scanning Setting scaling factor resolution change horizontal scanning direction Specifying vertical scanning Setting scaling factor resolution change vertical scanning direction Start reading single line
MSSEL Data setting CNV_D (100 bits quantity) MSSEL Data setting CNV_D quantity) Setting SRDY
generated?
reading single line
Page end?
Figure Sequence Resolution Change Setting PTIMB signal control signals pulse motor reading roller. sequence reduction shown figure that enlargement figure
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
ACCK <SCAN> (START) <SRDYB> (SSCAN) STIMB SCLK SVID PTIMB <CNV_D> <INTCLR>
Output section <SCAN>, <SRDYB>, <CNV_D>, <INTCLR>: register setting (START), (SSCAN): internal signals
Reduced line Reduced line
initial setting, enlargement/reduction setting (CNV_D) horizontal scanning implemented. Then, after system switched into setting mode enlargement/reduction vertical scanning, first line set. With flow ACCK, SCAN command taken when system comes into standby mode SRDYB. (START: With flow SRDYB: taken when scanning starts PTIMB output. (SSCAN: During period that STIMB converted binary data output while data reduced lines output because STIMB them With flow ACCK, SRDYB: taken when reading single line completed. (SSCAN: With flow SSCAN, asserted. (INT: With ready reading next line, enlargement/reduction setting (CNV_D) vertical scanning implemented; INTCLR generated; negated; then SRDYB
Figure Reduction Processing Sequence
ACCK <SCAN> (START) <SRDYB> (SSCAN) STIMB SCLK SVID PTIMB <CNV_D> <INTCLR>
Output section <SCAN>, <SRDYB>, <CNV_D>, <INTCLR>: (START), (SSCAN): register setting internal signals
Enlarged line
Enlarged line
initial setting, enlargement/reduction setting (CNV_D) horizontal scanning implemented. Then, after system switched into setting mode enlargement/reduction vertical scanning, first line set. With flow ACCK, SCAN command taken when system comes into standby mode SRDYB. (START: With flow SRDYB: taken when scanning starts PTIMB output while output enlarged lines. (SSCAN: During period that STIMB converted binary data output. With flow ACCK, SRDYB: taken when reading single line completed. (SSCAN: With flow SSCAN, asserted. (INT: With ready reading next line, enlargement/reduction setting (CNV_D) vertical scanning implemented; INTCLR generated; negated; then SRDYB
Figure Enlargement Processing Sequence
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Compensation shown figure image data characters pictures photoelectrically converted sensor unit show degradation resolution. compensation function M66335 restores resolution those data expands apparent dynamic range strengthening high-pass frequency constituent with Laplacian filter.
Photoelectric conversion Photoelectric conversion
Original (character)
Image signal
compensation
Data after compensation
Photoelectric conversion
Original (photo)
Image signal
compensation
Data after compensation Resolution compensation Where, compensation coefficient register (MTF_C, MTF_I) above equation, according register MODE (selection conversion-into-binary mode) follows: MODE: (simple binary) MTF_C MODE: (organized dither) MTF_I MODE: (image zone separation) separation (character) MTF_C image zone separation (photo) MTF_I image zone MODE: (error diffusion) MTF_I
Figure Compensation
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Correction correction according sensitivity characteristics (logarithmic characteristics) human eyes implemented approximate image data natural images. this, M66335 writes correction table built-in SRAM read corrected values corresponding read image data values from SRAM. 0.45 considered optimal correction thermal head printers. Figure shows characteristics example 0.45. correction processing through register GAMMA follows. conversion table value image zone separation (character) conversion table value image zone separation (photo) GAMMA: conversion table value image zone separation (character) image zone separation (photo) procedures inputting/outputting data, refer section writing to/reading from correction memory. GAMMA: GAMMA: GAMMA:
Image data
(Address) (Output) correction memory
Data after correction
White
Image data after correction (memory output)
DOUT
0.45
Dlow
(DIN Dlow) DOUT
Black Black:
Image data (address)
White:
Figure Correction Means Conversion Table
(Dlow Dup) DOUT Dlow Dlow (Dup DIN) DOUT
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Background/Character Level Detection M66335 uses fixed threshold system floating threshold system, where optimal threshold simple conversion-to-binary objective pixels continually generated constantly detecting background/character levels. Accordingly, threshold value proper image data generated without processing data. threshold value used areas converted binary when simple conversion-to-binary image zone separation selected mode conversion binary reading data. register (MODE) Background level counter When image data greater (lighter light) than current value input, this counter counts approximate data. When image data smaller (darker light) than current value input, this counter counts down approximate data. Setting rate count-up/count-down following data input: register (MAX_UP, MAX_DOWN) Setting lowest limit background levels: register (LL_MAX) Character level counter When image data greater (lighter light) than current value input, this counter counts approximate data. When image data smaller (darker light) than current value input, this counter counts down approximate data. Setting rate count-down following data input: register (MIN_UP) Setting highest limit character levels: register (UL_MIN)
Image data
Background level detection counter Generation threshold value Character level detection counter
Comparison
Converted binary data
This slope decided through MAX_UP. This slope decided through MAX_DOWN. Fixing background level White level Background level Lowest limit background level (LL_MAX)
Input data
Threshold level Character level Highest limit character level (UL_MIN) Black level
This slope decided through MIN_UP.
Fixing character level
Threshold level (background level point character level) character level threshold factor conversion binary: register (SLICE) Lowest limit background level (LL_MAX) highest limit character level (UL_MIN)
Figure Background/Character Levels
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Error Diffusion error diffusion, which conditional determination method, locally diffuses density errors between original image result obtain best approximation. This generates images with good compatibility gradation resolution. This operated selecting error diffusion conversion-into-binary mode selection. register (MODE) error diffusion, dithers well density errors added image data. dithers data commonly used dither matrix. register (ERROR) correction must performed error diffusion. Organized dither M66335 built-in SRAM with configuration words bits organized dither memory. initial setting, write threshold value proper preferred dither pattern dither memory after setting dither matrix size. register (DITH) register (DITH_D) procedure inputting/outputting data, refer section writing to/reading from dither memory.
Dither matrix
Integrated error klEm (Note
(white) (black)
Weighting error filter
Error (Note
Notes Characterized using difference from corrected value rather than that from original pixel Fmn. Errors before point remark integrated.
Error buffer memory Preceding line Current line
klEm (dither
register (error) register (dither addition factor)
Figure Error Diffusion Method
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Image Zone Separation make data conversion each image zone, black white image separated into zones converted binary gradation zones. binary zone processed through simple conversion binary gradation zone through error diffusion. register
black white image, each window gradation zone (photo) does have large difference luminance With this characteristic gradation zone, distinguished from conversion-into-binary zone through following method. Lmax: maximum illumination window Lmin: minimum illumination window Determining inequality Lmax Lmin (because zone converted binary large difference luminance it.): register Difference (SEPA_A) Determining inequality Lmin (for wholly white area): register Minimum (SEPA_B) Determining inequality Lmax (for wholly black area): register Maximum (SEPA_C) window satisfies determination inequalities simple conversion binary applied. window does satisfy determination inequalities change pseudo-halftone applied. White level Difference
Lmax
Minimum
Lmin
Maximum
Input data
Lmin
Black level
Lmax Lmin Lmax
Figure Image Zone Separation
Region Designation Function sensor width fixed region designation function output only data region defined designated terms output data after resolution change after uniformity correction multivalued data). Registers (OFFSET, OUTLENGTH)
Output width Designated region
OFFSET
OUTLENGTH
Figure Cut-out Function
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
CODEC Interface (Binary Data Output)
Serial Output
SRDYB
STIMB
(Equal scale, reduced scale) SCLK SVID
(Enlarged scale) SCLK
SVID Unit: 1/SYSCK
Note:
decided through registers (ST_PL) (OFFSET), through registers (OUTLENGTH).
Parallel Output
Pixel SCLK SVID
Note:
3-line handshake SRDY, STIM, which interface with CODEC, same serial output.
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Interface (Multivalued Output)
transfer data after non-uniformity correction performed setting P_O) register (existence output) that register (multivalue). With this setting, neither enlargement, reduction, resolution set.
SSCAN
(DMA counter reset signal) DAKB
(DMA counter signal) (DMAFIN)
<7:2>
(XXXX): internal signal
completion reading line, with flow SSCAN, reset signal entered counter. With flow reset signal, shifts "H", when transfer becomes ready. With DAKB flow RDB, shifts "L", when multivalued data output <7:2> during period that "L". With flow DAKB, counter counts shifts "H", when transfer becomes ready again. cycle above repeated until counter counts reach number output pixels registers OUTLENGTH subtracted one. that repetitive operation, DMAFIN shifts terminate transfer when reaches number. With flow DMAFIN, shifts "H", when interrupt. Reading resumed from next line negating signal through register (INTCLR).
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Writing to/Reading from Dither Memory, Correction Memory, Uniformity Correction Memory, Resolution Change Memory
sequences writing dither pattern reading from SRAM with configuration words bits which built M66335 organized dither shown below.
Writing dither memory (MPU M66335) Initial setting Initial setting Memory address Memory address
(Input)
DATA
DATA
Reading from dither memory (M66335 MPU) Initial setting
Initial setting
Memory address
Memory address
(Input) (Output)
DATA
DATA
(DITH) register define dither matrix size. (CNTRST) register reset address counter dither memory. DITH_D selected register DATA written memory. address counter dither memory incremented edge first transition (For writing) DITH_D selected register DATA dither memory read into D0). address counter dither memory incremented edge first transition (For reading)
Dither Matrix Addresses
Matrix
Matrix
Matrix
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP sequences writing correction table reading from SRAM with configuration words bits which built M66335 correction shown below.
Writing correction memory (MPU M66335) Initial setting Memory address Memory address
(Input)
DATA
DATA
Reading from correction memory (M66335 MPU)
Initial setting
Memory address
Memory address
(Input) (Output)
DATA
DATA
(CNTRST) register reset address counter correction memory. GAMMA_D selected register DATA written memory. address counter correction memory incremented edge first transition WRB. (For writing) GAMMA_D selected register DATA correction memory read into D0). address counter correction memory incremented edge first transition RDB. (For reading)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Uniformity correction data written read from SRAM uniformity correction built M66335 through bus. With this operation, uniformity data temporarily saved backup memory when power off. sequences writing reading uniformity correction data shown below.
Writing uniformity correction memory (MPU M66335) Initial setting Initial setting Memory address Memory address
(Input)
DATA
DATA
Reading from uniformity correction memory (M66335 MPU) Initial setting Initial setting Memory address Memory address
(Input) (Output)
DATA
DATA
(black correction) (white correction) (Umode) register (CNTRST) register reset address counter uniformity correction memory. UNIF_D selected register DATA written memory. address counter uniformity correction memory incremented edge first transition WRB. (For writing) UNIF_D selected register DATA uniformity correction memory read into D0). address counter uniformity correction memory incremented edge first transition RDB. (For reading)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP sequences writing resolution change table reading from SRAM with configuration words which built M66335 resolution change shown below.
Writing resolution change memory (MPU M66335) Initial setting Initial setting Memory address Memory address
(Input)
DATA
DATA
Reading from resolution change memory (M66335 MPU) Initial setting Initial setting Memory address Memory address
(Input) (Output)
DATA
DATA
(horizontal scan) (MSSEL) register (CNTRST) register reset address counter resolution change memory. CNV_D selected register DATA (D0) written memory. address counter resolution change memory incremented edge first transition WRB. (For writing) CNV_D selected register DATA resolution change memory read into (D0). address counter resolution change memory incremented edge first transition RDB. (For reading)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP List M66335FP Registers
Default INTCLR GAIN <7:0> UNIF_D <5:0> AGCSTP SRDYS OUTLENGTH <7:0> OUTLENGTH <12:8> CNV_D SRDYB MAX_UP <1:0> MSSEL DITH <1:0> CONVX <1:0> ERROR <1:0> RESET SOURCE SENS S/H_W LCMPS SENS_W SH_W UNIFS BLCMPS UNIF SCAN CIS3 UMODE UNIFM CIS2 CNTRST CIS1
PRE_DATA (7:0) PRE_DATA (13:8) ST_PL (7:0) CONVY <1:0> MTF_C <1:0> SEPA_A (5:0) SEPA_B (5:0) SEPA_C (5:0) MAX_DOWN <1:0> UL_MIN <5:0> LL_MAX <5:0> GAMMA_D (5:0) DITH_D (5:0) OFFSET <7:0> OFFSET <12:8> MIN_UP <1:0> GAMMA <1:0> SLICE <2:0> MTF_I <1:0> MODE <1:0>
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Register Structure
Address RESET SENS
SENS_W
UNIF
SCAN
UMODE
(Default value: 00H)
RESET: System Reset Normal mode Reset mode
With system reset during period that write pulse "L". Write only
SENS: Sensor Type CIS: (75% clock duty)
SENS_W: Reading Width Sensor Controls start/stop mode.
AGC: Mode Stop Start
UNIF: UNIF Mode Stop Start
Controls start/stop UNIF mode.
SCAN: SCAN Mode Stop Start
Controls start/stop SCAN mode.
UMODE: Uniformity Correction UNIF Mode Black Correction White Correction Only White Correction Black correction White correction White correction
SOURCE
S/H_W
S/H_W
UNIFS
UNIFM
CNTRST (Default value: 00H)
SOURCE: Reading Width Original
S/H_W: Pulse Width Normal (quadruple system clock cycle) Normal multiplied
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
Description SH_W: Pulse Width Normal times system clock cycle) Reverse normal multiplied
UNIFS: Uniformity Correction Valid Invalid output form form MSB.
P_O: Output Without output With output
M_B: Processing Mode Binary Multivalue
With multivalue selected, data (6-bit) after nonuniformity correction output through transfer.
UNIF: Uniformity Correction SCAN White correction Black correction white correction With counter reset during period that write pulse "L". built-in addresses reset. Write only
CIS3 CIS2 CIS1 (Default value: 00H)
CNTRST: Address Counter Reset Normal mode Reset mode
LCMPS
BLCMPS
RES: Resolution
Invalid Valid
LCMPS: Line Clamping
BLS: Clamping Invalid Valid
BLCMPS: Black Level Line Clamping Invalid Valid
Sensors Compatible with Image Sensor Interfaces CIS1: sensors with input level higher CIS2: sensors with input level under CIS3: sensors capable line clamping
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
(Default value: 00H)
PRE_DATA <7:0>
PRE_DATA <7:0> lowest order bits single-line cycle counter value
(Default value: 00H)
PRE_DATA <13:8>
PRE_DATA <13:8> highest order bits single-line cycle counter value
(Default value: 00H)
ST_PL <7:0>
ST_PL <7:0> start pulse position sensor ST_PL (dummy pixels sensor
MSSEL CONVX CONVY (Default value: 00H)
GAMMA
MSSEL: Horizontal Vertical Setting Horizontal Vertical When "with averaging" selected: enlargement: inserted lines average preceding current one. reduction: subsequent lines from removed lines average removed current one. With setting dpi, enlargement cannot set.
AVE: Averaging Processing With averaging Without averaging
CONVX: Enlargement/Reduction Mode Horizontal Scanning Direction Original scale Enlargement Reduction
CONVY: Enlargement/Reduction Mode Horizontal Scanning Direction Original scale Enlargement Reduction
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
Description GAMMA: Correction Processing Character, photo: Character, photo: download value Character: photo: download value Character: download value; photo:
Note: Judgment between character photo based result image zone separation.
DITH MODE SLICE (Default value: 00H)
POL: Conversion-to-Binary Output Mode White: black: White: black:
DITH: Dither Matrix Size
MODE: Selection Conversion-to-Binary Mode Simple binary Organized dither Image zone separation (simple binary error diffusion) Error diffusion
SLICE: Threshold Factor Conversion Binary 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
ERROR MTF_C MTF_I (Default value: 00H)
Error (Base) Strong (7/8) Strong (7/8) Weak (3/4) Weak (3/4)
ERROR Rate Dither Addition Errors Weak (1/8) Strong (1/4) Weak (1/8) Strong (1/4)
MTF_C: Compensation Factor
Note: This valid when MODE simple binary image zone separation (character).
MTF_I: Compensation Factor
Note: This valid when MODE organized dither, error diffusion image zone separation (photo).
(Default value: 00H)
SEPA_A
SEPA_A Image zone separation parameter (differential)
(Default value: 00H)
SEPA_B
SEPA_B Image zone separation parameter (minimum)
(Default value: 00H)
SEPA_C
SEPA_C Image zone separation parameter (maximum)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
(Default value: 00H)
MAX_UP
MAX_DOWN
MIN_UP
MAX_UP: Background Level Detection Clock Counter Ordinary (single pixel cycle) Slow (single pixel cycle) Fast (single pixel cycle) Fastest (single pixel cycle)
MAX_DOWN: Background Level Detection Clock Down Counter Ordinary (single pixel cycle) 128) Slow (single pixel cycle) 256) Fast (single pixel cycle) Fastest (single pixel cycle)
MIN_UP: Character Level Detection Clock Counter Ordinary (single pixel cycle) 128) Slow (single pixel cycle) 256) Fast (single pixel cycle) Fastest (single pixel cycle)
(Default value: 1FH)
UL_MIN
UL_MIN Detection background/character levels Highest limit character levels
(Default value: 20H)
LL_MAX
LL_MAX Detection background/character levels Lowest limit background levels Lowest limit background levels (LL_MAX) highest limit character levels (UL_MIN)
GAMMA_D <5:0>
GAMMA_D Built-in memory data
DITH_D <5:0>
DITH_D Built-in dither memory data
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
(Default value: 00H)
OFFSET <7:0>
OFFSET <7:0> Offset cut-out Lowest order bits
OFFSET <12:8> (Default value: 00H)
OFFSET <12:8> Offset cut-out Highest order bits
(Default value: 00H)
OUTLENGTH <7:0>
OUTLENGTH <7:0> output pixels Lowest order bits
(Default value: 00H)
OUTLENGTH <12:8>
OUTLENGTH <12:8> output pixels Highest order bits Note: OUTLENGTH <12:8> must multiple number output pixels multiple remainder division must omitted.
CNV_D
CNV_D Indication enlargement/reduction
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Address
AGCSTP SRDYS SRDYB (Default value: 00H)
AGCSTP: Gain Control Counter Gain control counter valid. Gain fixed.
SRDYS: SRDY Control SRDY control through register SRDY control through external case data control through register, SDRYB input must always "H". control through register, SRDY register must controlled line line. Write only
SRDYB: Data Transfer Start Ready Transfer allowed. Transfer allowed.
INTCLR
signals negated accessing this address.
GAIN <7:0>
reading: current gain value gain control counter read. writing: gain value gain control counter set. However, this valid only AGCSTP
With UMODE access uniformity correction memory black correction available. With UMODE access uniformity correction memory white correction available.
UNIF <5:0>
UNIF_D Built- uniformity correction memory data
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Description Operations Analog Circuits
configuration analog processing circuits shown figure
Sensor Selection Circuit four types sensors table connected circuit.
Register CIS1 CIS2 CIS3 Sensor Type sensor sensor which outputs light voltages (white voltage) lower sensor which outputs light voltages (white voltage) lower sensor which output shielding pixels each line
<CCD mode>
Black mVp-p White Blanking element
Signaling element
amplitudes sensor signals multiplied through operating amplifiers directly after switch select mode. (The waveforms signals inverted same time.) result, sensor signals input sample hold circuit have dark voltage
Shielding pixel part
Effective pixel part
<CIS1 mode>
White Black ±200 Signaling element
amplitude signals input from sensor halved. Then, their reference potential shifted result, sensor signals input sample hold circuit have dark voltage
<CIS2 mode>
White Black ±200 Signaling element
reference potential signals input from sensor shifted result, sensor signals input sample hold circuit have dark voltage
<CIS3 mode>
White Vp-p Black Clamping level Shielding pixel part Signaling element Effective pixel part
Sensor signals with dark voltage clamped line clamping input directly input sample hold circuit.
Line Clamping Circuit This circuit used (line clamping mode) CIS3. reference voltage (dark voltage) output shielding pixel part sensor sampled LCMP (line clamping pulses) shifted internal reference voltage This used CIS1 CIS2 input sensor (set constantly). register (LCMPS)
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Sample Hold Circuit Clamping Circuit mode, clamping, well line clamping, performed. blanking elements each pixel sensor output sampled BTCMP (bit clamping pulses). differences signals from reference potential sampled clamping circuit input gain control circuit next step signaling elements. turn clamping, invalid, that reference potential will fixed internal reference potential register (BLS) Gain Control Circuit amplifying factor (gain) must adjusted that amplitudes sensor signals come within dynamic range converter. gain through automatic gain control mode (register directly through register (GAIN <7:0>). gain changes within following ranges according sensor used.
Mode CIS1 CIS2 CIS3 Amplifying Factor Signals (Gain)
mode, gain control counter greatest gain initial state then counted down each time overflow output from converter. count (gain) gain control counter directly read/written through register (GAIN <7:0>). counting operation counter controlled through register (AGCSTP).
Internal Reference Voltage Internal reference voltage source analog circuits: this generates reference voltage (2.2 line clamping circuit, sample hold circuit, clamping circuit. converter reference voltage generation circuit: this generates (white level reference voltage (black level reference voltage converter. Black Level Clamping Circuit This circuit adjust level reference voltage converter from analog circuits. black clamping circuit used CID3 mode. (See figure GCAO BCMI capacity-coupled. output reference potential shielding pixel part sensor signals applied BCMV (black level reference voltage converter. BLCMP (black level clamping pulses) generated concurrently with shielding pixel part each line. turn this circuit, BLCMPS invalid apply black level reference voltage converter BCMV pin. register (BLCMPS) CIS1 CIS2 mode, LEVAJ used. (See figure Voltage applied LEVAJ that reference potential output GCAO adjusted (black level reference voltage converter. voltage input LEVAJ follows. VLEVAJ VVBL VGCAO VLEVAJ where, lowest limit dark voltage sensor gain (multiplying factor) gain control circuit VIN: signals input from sensor
REJ03F0276-0200 Rev.2.00 2008 Page
AVcc DVcc BCMI BCMO
M66335FP
GCAO LEVAJ BCMV
AVDD MCIS <3:1>, MCCD BTCMP
GCAO LEVAJ BCMV BLCMP BCMI BCMO
MCIS1
Sample hold circuit
Level shift circuit (2.2
LCMP MCIS <3:1>, MCCD
REJ03F0276-0200 Rev.2.00 2008 Page
MCIS2
BTCMP BLCMP
MCIS3
LCMP MCCD
Gain control circuit clamping circuit
Black level clamping circuit
AGCSEL <7:0>
RESET ADCK GAIN <7:0>
Input clamping circuit
Reference voltage generating circuit converter
Digital circuit
Internal reference voltage source analog circuits
Vri- AGND AVcc DVcc Vref- Vri+ Vref+
VREFH VREFL ADIN ADCK RESET AGND DGND
<7:1>
<6:0>
converter
Figure Circuit Configuration Analog Part M66335FP
AGND DGND Vri- Vri+ ADIN
VVBL
M66335FP
Analog Circuit Timing Chart (for Mode/Bit Clamping)
Register Mode (bit clamping) Address Signal Setting SENS LCMPS BLCMPS CIS3 CIS2 CIS1
Non-signaling part signal output LCMP BTCMP GCAO signal output BLCMP
Shielding pixel part
Effective pixel part
BCMO signal output clock output
Non-signaling part
Shielding pixel part
Effective pixel part
Unit: 1/SYSCK
signal output
LCMP
BTCMP
GCAO signal output BLCMP
BCMO signal output clock output
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Analog Circuit Timing Chart (for Mode/Line Clamping)
Register Mode (line clamping) Address Signal Setting SENS LCMPS BLCMPS CIS3 CIS2 CIS1
Non-signaling part signal output LCMP BTCMP GCAO signal output BLCMP
Shielding pixel part
Effective pixel part
BCMO signal output clock output
Non-signaling part signal output
Shielding pixel part
Effective pixel part
Unit: 1/SYSCK
LCMP BTCMP
GCAO signal output
BLCMP
BCMO signal output clock output
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Analog Circuit Timing Chart (for CIS1 Mode)
Register Mode CIS1 Address Signal Setting SENS LCMPS BLCMPS CIS3 CIS2 CIS1
signal output LCMP BTCMP
GCAO signal output
clock
output
Unit: 1/SYSCK
signal output LCMP BTCMP
GCAO signal output clock
output
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Analog Circuit Timing Chart (for CIS2 Mode)
Register Mode CIS2 Address Signal Setting SENS LCMPS BLCMPS CIS3 CIS2 CIS1
signal output
LCMP BTCMP
GCAO signal output
clock
output
Unit: 1/SYSCK
signal output LCMP BTCMP
GCAO signal output clock
output
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Analog Circuit Timing Chart (for CIS3 Mode)
Register Mode CIS3 Address Signal Setting SENS LCMPS BLCMPS CIS3 CIS2 CIS1
Non-signaling part signal output LCMP BTCMP GCAO signal output BLCMP BCMO signal output clock output
Shielding pixel part
Effective pixel part
Non-signaling part
Shielding pixel part
Effective pixel part
Unit: 1/SYSCK
signal output LCMP
BTCMP
GCAO signal output
BLCMP BCMO signal output clock
output
REJ03F0276-0200 Rev.2.00 2008 Page
LEVAJ BCMV
M66335FP
AVcc
DVcc
GCAO LEVAJ BCMV BCMI BCMO
(bold line): signal line
(dashed line): clock line
AVDD
MCIS <3:1>, MCCD
BTCMP
GCAO LEVAJ BCMV BLCMP BCMI BCMO
Sensor output MCCD clamping circuit AGCSEL <7:0> Reference voltage generating circuit converter
LCMP
Gain control circuit Black level clamping circuit
Black
mVp-p
White
Input clamping circuit
Signaling element
Blanking element
Internal reference voltage source analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+
AGND
VREFH VREFL ADIN ADCK RESET AGND DGND
converter
Figure External Connections Analog Part (for Mode/Bit Clamping)
AGND
DGND
Vri-
Vri+
ADIN
REJ03F0276-0200 Rev.2.00 2008 Page
MCIS1 Sample hold circuit
Level shift circuit (2.2
LCMP MCIS <3:1>, MCCD
MCIS2
BTCMP BLCMP RESET ADCK GAIN <7:0>
MCIS3
Digital circuit
<7:1>
<6:0>
LEVAJ GCAO LEVAJ BCMV BCMI BCMO BCMV
M66335FP
AVcc
DVcc
(bold line): signal line
(dashed line): clock line
GCAO LEVAJ BCMV BLCMP BCMI BCMO
AVDD
MCIS <3:1>, MCCD
BTCMP
Sample hold circuit
LCMP MCCD clamping circuit Input clamping circuit
Gain control circuit Black level clamping circuit
Black
Signaling element Blanking element
mVp-p
White
Reference voltage generating circuit converter
Internal reference voltage source analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+
AGND
VREFH VREFL ADIN ADCK RESET AGND DGND
converter
Figure External Connections Analog Part (for Mode/Line Clamping)
AGND
DGND
Vri-
Vri+
ADIN
REJ03F0276-0200 Rev.2.00 2008 Page
MCIS1
Level shift circuit (2.2
LCMP MCIS <3:1>, MCCD
MCIS2
BTCMP BLCMP RESET ADCK GAIN <7:0>
MCIS3
AGCSEL <7:0>
Digital circuit
<7:1>
<6:0>
M66335FP
BCMV
AVcc
DVcc
GCAO LEVAJ BCMV BCMI BCMO
(bold line): signal line
(dashed line): clock line
GCAO LEVAJ BCMV BLCMP BCMI BCMO
AVDD
MCIS <3:1>, MCCD
BTCMP
Sensor output MCCD clamping circuit AGCSEL <7:0>
LCMP
Gain control circuit Black level clamping circuit
Black White
Input clamping circuit Reference voltage generating circuit converter
±200
Internal reference voltage source analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+
AGND
VREFH VREFL ADIN ADCK RESET AGND DGND
that following equation will hold. VLEVAJ VVBL (1.8 Where,
converter
minimum limit dark voltage sensor
gain gain control circuit
Figure External Connections Analog Part (for CIS1 Mode)
MCIS1 Sample hold circuit
Level shift circuit (2.2
AGND
DGND
Vri-
Vri+
VLEVAJ
ADIN
REJ03F0276-0200 Rev.2.00 2008 Page
LCMP MCIS <3:1>, MCCD
Sensor output MCIS2
BTCMP BLCMP RESET ADCK GAIN <7:0>
MCIS3
Digital circuit
<7:1>
<6:0>
case pixel clock MHz)
M66335FP
BCMV
AVcc
DVcc
GCAO LEVAJ BCMV BCMI BCMO
(bold line): signal line
(dashed line): clock line
GCAO LEVAJ BCMV BLCMP BCMI BCMO
AVDD
MCIS <3:1>, MCCD
BTCMP
Sensor output
LCMP clamping circuit AGCSEL <7:0>
Gain control circuit Black level clamping circuit
Black White
MCCD Input clamping circuit
±200 Reference voltage generating circuit converter
Internal reference voltage source analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+
AGND
VREFH VREFL ADIN ADCK RESET AGND DGND
that following equation will hold. VLEVAJ VVBL (1.8 Where,
converter
minimum limit dark voltage sensor
gain gain control circuit
Figure External Connections Analog Part (for CIS2 Mode)
MCIS1 Sample hold circuit
Level shift circuit (2.2
AGND
DGND
Vri-
Vri+
ADIN
VLEVAJ
REJ03F0276-0200 Rev.2.00 2008 Page
LCMP MCIS <3:1>, MCCD
MCIS2 MCIS3
BTCMP BLCMP RESET ADCK GAIN <7:0>
Digital circuit
<7:1>
<6:0>
LEVAJ BCMV
M66335FP
AVcc
DVcc
GCAO LEVAJ BCMV BCMI BCMO
(bold line): signal line
(dashed line): clock line
GCAO LEVAJ BCMV BLCMP BCMI BCMO
AVDD
MCIS <3:1>, MCCD
MCIS2
Sensor output MCCD clamping circuit AGCSEL <7:0>
LCMP
Gain control circuit
White Input clamping circuit
Vp-p
Black
Shielding pixel part
Signaling part
Reference voltage generating circuit converter
Internal reference voltage source analog circuits Vri- Vref- Vri+ AVcc DVcc Vref+
AGND
VREFH VREFL ADIN ADCK RESET AGND DGND
Figure External Connections Analog Part (for CIS3 Mode)
BTCMP
Sample hold circuit
converter
AGND
DGND
Vri-
Vri+
ADIN
REJ03F0276-0200 Rev.2.00 2008 Page
MCIS1
Level shift circuit (2.2
LCMP MCIS <3:1>, MCCD BTCMP BLCMP Black level clamping circuit RESET ADCK GAIN <7:0>
MCIS3
Digital circuit
<7:1>
<6:0>
M66335FP
Flowchart
Reading Operations (for Sensor)
Start Power Software reset S/H: pulse width Sensor control Cycle counter Start pulse
Image processing parameters
Register Register
Reading original sheet starts.
Image processing function
Register Register
Reading single page
Register
Specifying scaling factor vertical scanning
Register
Register SRDY setting Register
Initial setting
Register
Register Register
generated?
Register
Page end?
Reading original sheet ends.
Writing dither pattern Completed? Writing correction table Next original sheet
light source turned (white reference) Becomes stable. line cycle more) wait
Register
Register
line cycle wait light source turned off.
Transfer continued?
Completed? starts. Register AGC: times ends. Register Register White correction times Register
Peak value detection White correction
Power off? Next original sheet
Next original sheet?
Uniformity correction starts.
line cycle more) wait
Uniformity correction ends.
Power
Specifying vertical scanning resolution
Register
Setting original sheet
Specifying horizontal scanning resolution Completed? Specifying vertical scanning resolution Original sheet width output width
Register
Register
Registers
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP Reading Operations (for Sensor)
Start Power Software reset S/H: pulse width Sensor control Cycle counter Start pulse
Image processing parameters
Register Register
Reading original sheet starts.
Image processing function
Register Register
Reading single page
Register
Specifying scaling factor vertical scanning
Register
Registers SRDY setting
Initial setting
Register
Register Registers Register
generated?
Register
Page end?
Writing dither pattern Completed? Writing correction table Next original sheet
light source turned (white reference) Becomes stable. line cycle more) wait light source turned off.
Reading original sheet ends.
Register
Register
line cycle wait light source turned off.
Transfer continued?
Completed?
Peak value detection
Power off?
starts.
Register AGC: times
ends.
Register
Next original sheet
Next original sheet?
Black correction
Becomes stable.
Uniformity correction mode (black)
Uniformity correction starts.
Registers
Power
Register Black correction: times
line cycle more) wait light source turned (white reference) Becomes stable.
Uniformity correction ends.
Register
Uniformity correction mode (white)
White correction
Registers
Uniformity correction starts.
Register White correction: times
line cycle more) wait
Uniformity correction ends.
Register
Specifying horizontal scanning resolution
Register
Setting original sheet
Writing resolution change table Register
Completed? Register
Specifying vertical scanning resolution Original sheet width output width
Registers
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Interface
Timing Read Operation (M66335 MPU)
(CS-RD)
(RD-CS)
(A-RD) (RD)
(RD-A)
tPZL (RD-D)
tPLZ (RD-D)
tPZH (RD-D)
tPHZ (RD-D)
Timing Write Operation (MPU M66335)
(CS-WR)
(WR-CS)
(A-WR) (WR)
(WR-A)
(D-WR)
(WR-D)
Effective data
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Timing
Timing Read Operation (M66335 System Bus)
SYSCK tPHL (RD-DRQ)
(DAK-RD) (RD)
(RD-DAK)
tPZL (RD-D)
tPLZ (RD-D)
tPZH (RD-D)
tPHZ (RD-D)
Timing CODEC
(STIM-SRDY)
SRDY
STIM SCLK SVID
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Cautions
Access Address gain access address 00h, value built-in (gain control counter) FFh. This requires read GAIN value address before access address write GAIN value address after access (see flowchart
Start Read GAIN value address Access address Write GAIN value address
Flowchart Address Access Flow
Reset M66335FP adopts types reset. These reset functions provided table Table Reset Functions
Function Reset Type Hardware reset (RESET) Software reset register (RESET) Register Initialization Internal Initialization Initialization
REJ03F0276-0200 Rev.2.00 2008 Page
M66335FP
Package Dimensions
JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Reference Symbol
Dimension Millimeters
Index mark
Detail
REJ03F0276-0200 Rev.2.00 2008 Page
19.8 20.0 20.2 13.8 14.0 14.2 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.35 0.45 0.13 0.15 0.65 0.95 0.10
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: This document provided reference purposes only that Renesas customers select appropriate Renesas products their use. Renesas neither makes warranties representations with respect accuracy completeness information contained this document grants license intellectual property rights other rights Renesas third party with respect information this document. Renesas shall have liability damages infringement intellectual property other rights arising information this document, including, limited product data, diagrams, charts, programs, algorithms, application circuit examples. should products technology described this document purpose military applications such development weapons mass destruction purpose other military use. When exporting products technology described herein, should follow applicable export control laws regulations, procedures required such laws regulations. information included this document such product data, diagrams, charts, programs, algorithms, application circuit examples, current date this document issued. Such information, however, subject change without prior notice. Before purchasing using Renesas products listed this document, please confirm latest product information with Renesas sales office. Also, please regular careful attention additional different information disclosed Renesas such that disclosed through website. (http://www.renesas.com Renesas used reasonable care compiling information included this document, Renesas assumes liability whatsoever damages incurred result errors omissions information included this document. When using otherwise relying information this document, should evaluate information light total system before deciding about applicability such information intended application. Renesas makes representations, warranties guaranties regarding suitability products particular application specifically disclaims liability arising application information this document Renesas products. With exception products specified Renesas suitable automobile applications, Renesas products designed, manufactured tested applications otherwise systems failure malfunction which cause direct threat human life create risk human injury which require especially high quality reliability such safety systems, equipment systems transportation traffic, healthcare, combustion control, aerospace aeronautics, nuclear power, undersea communication transmission. considering products such purposes, please contact Renesas sales office beforehand. Renesas shall have liability damages arising uses forth above. Notwithstanding preceding paragraph, should Renesas products purposes listed below: artificial life support devices systems surgical implantations healthcare intervention (e.g., excision, administration medication, etc.) other purposes that pose direct threat human life Renesas shall have liability damages arising uses forth above purchasers elect Renesas products foregoing applications shall indemnify hold harmless Renesas Technology Corp., affiliated companies their officers, directors, employees against damages arising such applications. should products described herein within range specified Renesas, especially with respect maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation other product characteristics. Renesas shall have liability malfunctions damages arising Renesas products beyond such specified ranges. Although Renesas endeavors improve quality reliability products, products have specific characteristics such occurrence failure certain rate malfunctions under certain conditions. Please sure implement safety measures guard against possibility physical injury, injury damage caused fire event failure Renesas product, such safety design hardware software including limited redundancy, fire control malfunction prevention, appropriate treatment aging degradation other applicable measures. Among others, since evaluation microcomputer software alone very difficult, please evaluate safety final products system manufactured you. case Renesas products listed this document detached from products which Renesas products attached affixed, risk accident such swallowing infants small children very high. should implement safety measures that Renesas products easily detached from your products. Renesas shall have liability damages arising such detachment. This document reproduced duplicated, form, whole part, without prior written approval from Renesas. Please contact Renesas sales office have questions regarding information contained this document, Renesas semiconductor products, have other inquiries.
RENESAS SALES OFFICES
Refer latest detailed information. Renesas Technology America, Inc. Holger Way, Jose, 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> 2715-2888, Fax: <886> 3518-3399 Renesas Technology Singapore Pte. Ltd. Harbour Front Avenue, #06-10, Keppel Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 796-3115, Fax: <82> 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Unit 906, Block Menara Amcorp, Amcorp Trade Centre, No.18, Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
2008. Renesas Technology Corp., rights reserved. Printed Japan.
Colophon .7.2

Facsimile Image Data Processor REJ03F0276-0200 Rev.2.00 2008

Top Searches for this datasheet

Other recent searches