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8-Bit Driver with Shift Register Latched 3-State Outputs REJ03F01
Top Searches for this datasheetM66312P/FP 8-Bit Driver with Shift Register Latched 3-State Outputs REJ03F0178-0201 Rev.2.01 2008 M66312 array driver having 8-bit serial input parallel output shiftregister function with 3-state output latch. This product guarantees output electric current which sufficient drive, capable flowing bits continuously same time, either cathode common anode common LED. addition, this product been designed complete CMOS, power consumption greatly reduced when compared with conventional BIPOLAR Bi-CMOS products. Features High output current High speed (clock frequency): (typ) power dissipation: µW/package (max) (VCC 25°C, quiescent state) 3-state output (except serial data output) Wide operating temperature range: +85°C Application array drive PRINTER array drive BUTTON TELEPHONE REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Block Diagram Parallel data outputs Serial data output Output Latch Serial enable clock data input input input Shift clock input Direct reset input Arrangement M66312P/FP Parallel data outputs Parallel data output Serial data input Output enable input Latch clock input Shift clock input Direct reset input Serial data output (Top view) Outline: PRDP0016AA-A (16P4) PRSP0016DE-A (16P2N-A) REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Functional M66312 uses silicon gate CMOS process, realizes high-speed high-output currents sufficient drive while maintaining power consumption allowance high noises. Each shiftregister consists flip-flops having independent clocks shifting latching. clock input, shift clock input latch clock input independent from each other, shift latch operations being made when changes "H". Serial data input data input first-step shiftregister signal shifts shiting registers when pulse impressed CKS. When "H", signal shifts. When "L", signal shifts. When pulse impressed CKL, contents shifting register that time stored latching register, they appear output from through 3-state outputs. extend number bits, serial data output used output 8-bit shift register. connecting CKL, shift register state delayed clock cycle output through When reset input low, shift register will reset. reset through low-level, must changed from low-level high-level after shift register reset When output-enable input high, through will become high impedance state, changed. Even changed, shift operation affected. Function Table (Note) Input Operation Mode Reset Shift latch Shift Latch Shift Latch Latch state Parallel Data Output Serial Data Output operation Shift Note Change from low-level high-level Output state before changed Irrelevant Contents shift register before changed Contents shift register after High impedance REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Absolute Maximum Ratings +85°C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current Output current output Supply/GND current Power dissipation Storage temperature range Note: Symbol Tstg Ratings -0.5 +7.0 -0.5 -0.5 ±132 +150 Unit VCC, (Note) Conditions M66312FP; +70°C, 85°C derated mW/°C. Recommended Operating Conditions +85°C, unless otherwise noted) Item Supply voltage Input voltage Output voltage Operating temperature range Input rising falling time Symbol Topr Limits Unit REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Electrical Characteristics (VCC 5.5V, unless otherwise noted) Limits Item High-level input voltage Low-level Input voltage High-level output voltage High-level output voltage Low-level output voltage Low-level output voltage High-level input current Low-level input current state highlevel output current state lowlevel output current Quiescent supply current IOZH VCC-0.1 (note) 25°C VCC-0.1 3.70(note) +85°C VCC-0.1 3.55(note) VCC-0.1 0.85 (note) Unit Conditions VCC-0.1 VCC-0.1 VIH, VIH, VIH, VIH, -0.1 -1.0 10.0 VCC, GND, VIH, IOZL -1.0 -10.0 40.0 VCC, GND, Note: Limits single operating state REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Switching Characteristics (VCC Limits Item Maximum clock frequency Low-level high-level high-level low-level output propagation time CKS-SQH High-level low-level output propagation time RSQH Low-level high-level high-level low-level output propagation time CKL-QA Output disable time from low-level high-level OE-QA Output enable time lowlevel high-level OE-QA Note: Test Circuit Input Output Symbol fmax tPLH tPHL 25°C +85°C Unit Conditions (Note) tPHL tPLH tPHL (Note) tPLZ tPHZ tPZL tPZH (Note) (Note) Item tPLH, tPHL tPLZ tPHZ tPZL tPZH Open Close Open Close Open Open Open Close Open Close pulse generator (PG) following characteristics (10% 90%): capacitance includes stray wiring capacitance probe input capacitance. Timing Requirements (VCC Limits Item CKS, CKL, pulse width setup time with respect setup time with respect hold time with respect recovery time with respect Symbol trec 25°C +85°C Unit Conditions REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Timing Chart tPLH tPHL tPLH tPHL trec tPHL tPZL tPLZ tPZH tPHZ REJ03F0178-0201 Rev.2.01 2008 Page M66312P/FP Package Dimensions JEITA Package Code P-DIP16-6.3x19-2.54 RENESAS Code PRDP0016AA-A Previous Code 16P4 MASS[Typ.] 1.0g NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET. Reference Symbol Dimension Millimeters SEATING PLANE 7.32 18.8 6.15 0.51 0.22 2.29 7.62 19.0 7.92 19.2 6.45 0.27 2.54 0.34 2.79 JEITA Package Code P-SOP16-5.3x10.1-1.27 RENESAS Code PRSP0016DE-A Previous Code 16P2N-A MASS[Typ.] 0.2g NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET. Index mark Reference Symbol Dimension Millimeters Detail 10.0 10.1 10.2 0.35 0.18 0.25 1.12 1.27 1.42 REJ03F0178-0201 Rev.2.01 2008 Page Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: This document provided reference purposes only that Renesas customers select appropriate Renesas products their use. Renesas neither makes warranties representations with respect accuracy completeness information contained this document grants license intellectual property rights other rights Renesas third party with respect information this document. Renesas shall have liability damages infringement intellectual property other rights arising information this document, including, limited product data, diagrams, charts, programs, algorithms, application circuit examples. should products technology described this document purpose military applications such development weapons mass destruction purpose other military use. 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