262144-word 8-bit 3-FIFO MEMORY REJ03F0156-0310 Rev. 03.10 Apr.4.
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M66288FP
262144-word 8-bit 3-FIFO MEMORY
REJ03F0156-0310 Rev. 03.10 Apr.4.2008
M66288FP high-speed field memory with three FIFO (First First Out) memories 262144-word 8-bit configuration (2M-bit), which uses high-performance silicon gate CMOS process technology. three FIFO memories consists FIFO memories 262144-word 4-bit (1M-bit). Eight types operation performed mode settings.
Features
Memory configuration High speed cycle High speed access Output hold Supply voltage Variable length delay Eight modes selected Write Read function operated completely independently asynchronously Output type state output Package 100pin 14x14mm body LQFP (PLQP0100KB-A, 100P6Q-A) Total memory capacity 6M-bit (static memory). Eight types memory configurations selected. 12.5 (Min.) fmax 80MHz (Max.) (Min.) Internal 0.18
Application
W-CDMA base station, Digital PPC, Digital television,
Configuration (Top view)
MODE1 MODE2 MODE3 RRESC RRESB RRESA VccIO VccIO RCKC RCKB RCKA
VccIO Vcc18 VccIO Vcc18 TEST1 TEST2
Vcc18 VccIO VccIO Vcc18
M66288FP
WCKB
WRESB
WCKA
WRESA
WCKC
WRESC
VccIO
VccIO
TEST3
Vcc18
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page
VccIO
M66288FP
Mode Descriptions Drawing
256K-word MODE
DA<7:0> WCKA WRESA 256K-w 8-bit FIFO 256K-w 8-bit FIFO QA<7:0> RCKA RRESA
1K-word 1024-word
12-bit MODE
QA<7:0> RCKA RRESA
DA<7:0> WCKA WRESA 256K-w 8-bit FIFO QA<7:0> RCKA RRESA
8-bit MODE
DA<7:0> WCKA WRESA 256K-w 8-bit FIFO
MODE
DA<11:0> WCKA WRESA 256K-w 12-bit FIFO QA<11:0> RCKA RRESA
DA<11:0> WCKA WRESA
MODE
256K-w 12-bit FIFO QA<11:0> RCKA RRESA
DB<7:0> WCKB WRESB
QB<7:0> RCKB RRESB
256K-w 8-bit FIFO
QB<7:0>
256K-w 8-bit FIFO
QB<7:0>
DB<11:0> WCKB
256K-w 8-bit FIFO
256K-w 12-bit FIFO
QB<11:0> RCKB RRESB
DC<7:0> WCKC WRESC
256K-w 8-bit FIFO
QC<7:0> RCKC RRESC
256K-w 8-bit FIFO
DC<7:0>
QC<7:0> RCKC RRESC
WRESB
256K-w 12-bit FIFO
QB<11:0>
QC<7:0>
WCKC WRESC
three pieces 256K-word 8-bit FIFO operated completely independently. 3-system individual input 3-system individual output
three pieces 256K-word 8-bit FIFO cascade-connected. (Note 1-system input simultaneous output line delay data.
pieces 256K-word 8-bit FIFO cascade-connected and, piece 256K-word 8-bit FIFO operated completely independently. (Note 1-system input 1-system input simultaneous output line delay data. 1-system output
pieces 256K-word 12-bit FIFO operated completely independently. (Note 2-system individual input. 2-system individual output.
pieces 256K-word 12-bit FIFO cascade-connected (Note Note 1-system input simultaneous output line delay data.
768K-word MODE
DA<7:0> WCKA WRESA 768K-w 8-bit FIFO
512K-word 256K-word 8-bit MODE
QA<7:0> RCKA RRESA DA<7:0> WCKA WRESA 512K-w 8-bit FIFO QA<7:0> RCKA RRESA DA<11:0> WCKA WRESA
512K-word 12-bit MODE
512K-w 12-bit FIFO QA<11:0> RCKA RRESA
DC<7:0> WCKC WRESC
256K-w 8-bit FIFO
QC<7:0> RCKC RRESC
piece 768K-word 8-bit FIFO operated completely independently. 1-system input 1-system output
piece 512K-word 8-bit FIFO piece 256K-word 8-bit FIFO operated completely independently. 2-system individual input 2-system individual output
piece 512K-word 12-bit FIFO operated completely independently. (Note 1-system input 1-system output
Note1: Write read operation FIFO after line controlled read system line FIFO. Maximum number words this mode 256K-word. Line delay achieved without outer connection. Note2: Please refer assignment tables "Operation Description" Mode Mode Mode assignment external pins, Dx<11:0> Qx<11:0> when used 12-bit interface.
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M66288FP
Block Diagram
Data input DA<7:0>
DB<7:0>
DC<7:0>
INPUT BUFFER
Mode setting Mode setting input input MODE<3:1> MODE<3:1> Write control inputs A-system WRITE CONTROL CIRCUIT
MODE CONTROL CIRCUIT
Read control inputs A-system READ CONTROL CIRCUIT RCKA RRESA Read control inputs B-system RCKB RRESB Read control inputs C-system RCKC RRESC
WRITE ADDRESS COUNTER
WCKA WRESA Write control inputs B-system WCKB WRESB Write control inputs C-system WCKC WRESC Test setting input Test setting input TEST<3:1> TEST<3:1> Vcc18
MEMORY ARRAY
256K-WORD 8-BIT 256K-word 8bit READ ADDRESS COUNTER
256K-word 4bit 256K-WORD 4-BIT 256K-word 4bit 256K-WORD 4-BIT 256K-word 8bit 256K-WORD 8-BIT
MODE CONTROL CIRCUIT
OUTPUT BUFFER
VccIO
Data output Data output QA<7:0> QA<7:0>
QB<7:0>
QB<7:0>
QC<7:0>
QC<7:0>
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M66288FP
Function Descriptions
name Name Write clock input Input Output Input Number pins Function They write clock inputs.
Write enable input
Input
They write enable control inputs. When they "L", write enable status provided. They write reset inputs initialize write address counter internal FIFO. When they "L", write reset status provided. They read clock inputs.
WRES
Write reset input
Input
Read clock input
Input
Read enable input
Input
They read enable control inputs. When they "L", read enable status provided. They read reset inputs initialize read address counter internal FIFO. When they "L", read reset status provided. They 8-bit input data bus.
RRES
Read reset input
Input
<7:0>
Data input
Input
<7:0>
Data output
Output
They 8-bit output data bus.
MODE<3:1>
Mode setting input
Input
They operation mode setting inputs. setting, refer Mode setting table Page5. They test setting inputs. Setting TEST1 depends rising time system power supply. further details, refer page TEST2 TEST3 should fixed "L". This power supply I/O. This power supply internal circuit. This ground pin.
TEST<3:1>
Test setting input
Input
VccIO Vcc18
Power supply Power supply internal circuit Ground
Note: name shows A-system, B-system, C-system.
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Mode Setting
MODE<3:1> should shown below select operation modes. MODE MODE MODE Operation mode MODE MODE MODE MODE MODE MODE MODE MODE
Mode1 Operation
<Mode
DA<7:0> WCKA WRESA
256K-w 8-bit FIFO(A)
QA<7:0> RCKA RRESA
mode three pieces 256K-word 8-bit FIFO controlled completely independently. Taking FIFO example, operation FIFO memory described below. operation FIFO FIFO same that FIFO (A).
DB<7:0> WCKB WRESB
256K-w 8-bit FIFO(B)
QB<7:0> RCKB RRESB
When write enable input "L", contents data input DA<7:0> written into FIFO synchronization with rising write clock input WCKA. this time, write address counter FIFO incremented. When "H", this disable write data into FIFO write address
DC<7:0> WCKC WRESC
256K-w 8-bit FIFO(C)
QC<7:0> RCKC RRESC
counter FIFO incremented. When write reset input WRESA "L", write address counter FIFO initialized. When read enable input "L", contents FIFO outputted data output QA<7:0> synchronization with rising read clock input RCKA. this time, read address counter FIFO incremented. When "H", this disable read data from FIFO read address counter FIFO incremented. Also QA<7:0> become high impedance state. When read reset input RRESA "L", read address counter FIFO initialized.
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Mode2 Operation
<Mode mode three pieces 256K-word 8-bit FIFO cascade-connected possible generate delay data 3-lines without external wiring. When write enable input "L", contents data input DA<7:0> written into FIFO synchronization with rising write clock input WCKA. this time, write address counter FIFO incremented. When "H", this disable write data into FIFO write address counter FIFO incremented. When write reset input WRESA "L", write address counter FIFO initialized. When read enable input "L", contents FIFO (A), FIFO FIFO outputted each QA<7:0>, QB<7:0>, QC<7:0> synchronization with rising read clock input RCKA. this time, read address counters FIFOs incremented. Also data upper FIFO written into lower FIFO synchronization with rising RCKA. this time, write address counters FIFO FIFO incremented simultaneously. When "H", this disable read data from FIFO (A), FIFO FIFO read address counter each FIFO incremented. data outputs become high impedance state. this also disable write data into FIFO FIFO write address counter FIFO FIFO incremented. When read reset input RRESA "L", read address counter FIFO write/read address counters FIFO FIFO initialized. mode only pins A-system, QB<7:0> QC<7:0> used. Therefore, write/read control pins B/C-system, DB<7:0> DC<7:0> should fixed "H".
Note: Write read operation FIFO FIFO after line controlled read system line FIFO (A). Maximum number words this mode 256K-word.
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Mode3 Operation
<Mode
DA<7:0> WCKA WRESA
256K-w 8-bit FIFO(A)
QA<7:0> RCKA RRESA
mode pieces 256K-word 8-bit FIFO cascade-connected other FIFO configured completely independently. This makes possible generate delay data 2-lines without external wiring control other independent FIFO memory.
256K-w 8-bit FIFO(B)
QB<7:0>
When write enable input "L", contents data input DA<7:0> written into FIFO synchronization with rising write clock input WCKA. this time, write address counter FIFO incremented. When "H", this disable write data into FIFO write address counter FIFO incremented. When write reset input WRESA "L", write address counter FIFO initialized. When read enable input "L", contents FIFO FIFO outputted each QA<7:0> QB<7:0> synchronization with rising read clock input RCKA. this time, read address counters FIFO FIFO incremented. Also data FIFO written into FIFO synchronization with rising RCKA. this time, write address counter FIFO incremented simultaneously. When "H", this disable read data from FIFO FIFO read address counter each FIFO incremented. QA<7:0> QB<7:0> become high impedance state. this also disable write data into FIFO write address counter FIFO incremented. When read reset input RRESA "L", read address counter FIFO write/read address counter FIFO initialized. operation FIFO same that mode mode only pins A/C-system QB<7:0> used. Therefore write/read control pins B-system DB<7:0> should fixed "H".
DC<7:0> WCKC WRESC
256K-w 8-bit FIFO(C)
QC<7:0> RCKC RRESC
Note: Write read operation FIFO line controlled read system line FIFO (A). Maximum number words this mode 256K-word.
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Mode4 Operation
<Mode
DA<7:0> DB<3:0> WCKA WRESA
256K-w 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA
mode pieces 256K-word 12-bit FIFO controlled completely independently. Taking FIFO example, operation FIFO memory described below. operation FIFO same that FIFO (A). When write enable input "L", contents data input DA<7:0> DB<3:0> written into FIFO synchronization with rising write clock
DC<7:0> DB<7:4> WCKB WRESB
256K-w 12-bit FIFO(B)
QC<7:0> QB<7:4> RCKB RRESB
input WCKA. this time, write address counter FIFO incremented. When "H", this disable write data into FIFO(A) write address counter FIFO incremented. When write reset input WRESA "L", write address counter FIFO initialized. When read enable input "L", contents FIFO outputted data output QA<7:0> QB<3:0> synchronization with rising read clock input RCKA. this time, read address counter FIFO incremented. When "H", this disable read data from FIFO read address counter FIFO incremented. Also QA<7:0> QB<3:0> become high impedance state. When read reset input RRESA "L", read address counter FIFO initialized. Also, 12-bit buses FIFO FIFO shown table below. mode only pins A/B-system, DC<7:0> QC<7:0> used. Therefore write/read control pins C-system should fixed "H".
External Data input name FIFO DA<7> 11th-bit DA<6> -bit DA<5> -bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit
External Data output name FIFO QA<7> 11th-bit QA<6> -bit QA<5> -bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit
External Data input name FIFO DC<7> 11th-bit DC<6> -bit DC<5> -bit DC<4> 8th-bit DC<3> 7th-bit DC<2> 6th-bit DC<1> 5th-bit DC<0> 4th-bit DB<7> 3rd-bit DB<6> 2nd-bit DB<5> 1st-bit DB<4> 0th-bit
External Data output Name FIFO QC<7> 11th-bit QC<6> -bit QC<5> -bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit
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Mode5 Operation <Mode mode pieces 256K-word 12-bit FIFO cascade-connected possible generate delay data 2-lines without external wiring. When write enable input "L", contents data input DA<7:0> DB<3:0> written into FIFO synchronization with rising write clock input WCKA. this time, write address counter FIFO incremented. When "H", this disable write data into FIFO write address counter FIFO incremented. When write reset input WRESA "L", write address counter FIFO initialized. When read enable input "L", contents FIFO FIFO outputted each QA<7:0>, QB<3:0> QC<7:0>,QB<7:4> synchronization with rising read clock input RCKA. this time, read address counters FIFO FIFO incremented. Also data FIFO written into FIFO synchronization with rising RCKA. this time, write address counter FIFO incremented simultaneously. When "H", this disable read data from FIFO FIFO read address counter each FIFO incremented. Also data outputs become high impedance state. this also disable write data into FIFO write address counter FIFO incremented. When read reset input RRESA "L", read address counter FIFO write /read address counter FIFO initialized. Also, 12-bit buses FIFO FIFO shown table below. mode only pins A-system, DB<3:0>, QB<7:0> QC<7:0> used. Therefore write/read control pins B/C-system, DB<7:4> DC<7:0> should fixed "H". External Data input Name FIFO DA<7> 11th-bit DA<6> 10th-bit DA<5> 9th-bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit External Data output name FIFO QA<7> 11th-bit QA<6> 10th-bit QA<5> 9th-bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit External Data output Name FIFO QC<7> 11th-bit QC<6> 10th-bit QC<5> 9th-bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit
DA<7:0> DB<3:0> WCKA WRESA
256K-w 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA
256K-w 12-bit FIFO(B)
QC<7:0> QB<7:4>
Note: Write read operation FIFO(B) line controlled read system line FIFO(A). Maximum number words this mode 256K-word.
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Mode6 Operation
<Mode mode FIFO memory 768K-word 8-bit composition
DA<7:0> WCKA WRESA
controlled.
QA<7:0> RCKA RRESA
768K-w 8-bit FIFO(A)
operation FIFO same that mode mode only pins A-system used. Therefore, input pins B/C-system should fixed "H". Also QB<7:0> QC<7:0> become high impedance state.
Mode7 Operation
<Mode
DA<7:0> WCKA WRESA
512K-w 8-bit FIFO(A)
QA<7:0> RCKA RRESA
mode 512K-word 8-bit FIFO 256K-word 8-bit FIFO memory controlled completely independently. operation FIFO FIFO same that mode mode only pins A/C-system used. Therefore, input pins B-system should fixed "H".
DC<7:0> WCKC WRESC
Also QB<7:0> become high impedance state.
QC<7:0> RCKC RRESC
256K-w 8-bit FIFO(B)
Mode8 Operation
<Mode
DA<7:0> DB<3:0> WCKA WRESA
512K-w 12-bit FIFO(A)
QA<7:0> QB<3:0> RCKA RRESA
mode FIFO memory 512K-word 12-bit composition controlled. operation FIFO same that mode Also, please 12-bit buses FIFO mentioned table mode FIFO (A). mode only pins A-system, DB<3:0> QB<3:0> used. Therefore, write/read control pins B/C-system, DB<7:4> DC<7:0> should fixed "H". Also QB<7:4> QC<7:0> become high impedance state.
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Electrical Characteristics
Absolute Maximum Ratings
Symbol VCC18 VCCIO Tstg
70°C, unless otherwise noted)
Parameter Supply voltage (1.8 power supply Supply voltage (3.3 power supply Input voltage Output voltage Maximum power dissipation Storage temperature
Conditions value based
Ratings -0.3~+2.5 -0.3~+3.8 -0.3~VCCIO+0.3 -0.3~VCCIO+0.3 -55~150
Unit
Recommended Operating Conditions
Symbol VCC18 VCCIO Topr Parameter Supply voltage internal circuit (1.8 power supply Supply voltage (3.3 power supply Operating ambient temperature Test conditions value based Min. 1.62 Limits Typ. Unit Max. 1.98
Characteristics 70°C, Vcc18 0.18 VccIO unless otherwise noted)
Symbol IOZH IOZL ICC18 ICCIO Parameter input voltage input voltage output voltage output voltage input current input current state output current state output current Average operating supply current (1.8 Average operating supply current (3.3 Input capacitance state output capacitance -4mA VCCIO VCCIO VCC18 0.18 VCCIO repeat Output open tWCK tRCK 12.5 VccIO Test conditions value based Min. VccIO Limits Typ. Unit Max. VccIO
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Power
After power-on, this initializes some circuits internal FIFO (1.8 using built-in power-on reset circuit. This power-on reset performed using VCC18 system power supply. Either following conditions should according power-on time VCC18. When power-on time VCC18 msec less: Some circuits internal FIFO initialized built-in power-on reset circuit. restriction imposed power-on sequence between VCC18 VCCIO system power supply. When powering again after power-on, provide interval more VCC18. this time, TEST1 (pin should fixed "L".
1ms(max)
100ms(min)
VCC18 Vcc18
Vcc18 VCC18 Vcc18 VCC18
Vcc18 VCC18
When power-on time VCC18 more than msec: Some circuits internal FIFO should initialized TEST1 (pin pin. Input initialize reset pulse more after power supplies (VCCIO, VCC18) reach level. There problem even reaching level which power supply.
3.0V~3.6V 3.0V~3.6V
VCCIO VccIO
VCCIO VccIO
more 1.62V~1.98V
Vcc18 VCC18
VCC18 Vcc18
200ns(min)
200ns(min)
VCCIO VccIO
TEST1
Note: Some circuits internal FIFO initialized TEST1 even power-on time Vcc18 msec less.
Note: Important matter; Provide write reset cycles read reset cycles cycles more, respectively after reaches specified voltage after power-on. When inputting reset pulse using TEST1 (pin pin, provide write reset cycles read reset cycles cycles more, respectively after inputting reset pulse power-on. There problem this reset operation total cycles more achieved, even discontinuous reset input made.
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Timing Requirements
70°C, Vcc18 0.18 VccIO unless otherwise noted)
Symbol WCKH WCKL RCKH RCKL RESS RESH NRESS NRESH NWES NWEH NRES NREH Write clock (WCK) cycle
Parameter Min. 12.5 12.5 Write clock (WCK) pulse width Write clock (WCK) pulse width Read clock (RCK) cycle Read clock (RCK) pulse width Read clock (RCK) pulse width Input data setup time Input data hold time Reset setup time Reset hold time Reset non-select setup time Reset non-select hold time Write enable setup time Write enable hold time Write enable non-select setup time Write enable non-select hold time Read enable setup time Read enable hold time Read enable non-select setup time Read enable non-select hold time Input pulse rise fall time
Limits Typ. Max.
Unit
Switching Characteristics
70°C, Vcc18 0.18 VccIO unless otherwise noted)
Symbol ODIS Output access time Output hold time
Parameter Min.
Limits Typ. Max.
Unit
Output enable time Output disable time
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Switching Characteristics Measurement Circuit
tAC, tOEN, tODIS
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Input pulse level Decision voltage input VCCIO VCCIO that decision).
Close Open Close Open Open Close Open Close
Input pulse rise/fall time Decision voltage output VCCIO (However, tODIS (LZ) output amplitude tODIS (HZ) load capacitance includes floating capacitance connection input capacitance probe.
tODIS tOEN Measurement Condition
VccIO
VccIO
tODIS(HZ) tOEN(ZH) VccIO
tODIS(LZ) tOEN(ZL)
VccIO
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Operating Timing
Write Cycle
cycle
cycle
cycle
Disable cycle
cycle
cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
(n+1)
(n+2)
(n+3)
(n+4)
WRES
Write Reset Cycle
cycle
cycle
Reset cycle
cycle
cycle
tWCK WRES tNRESH tRESS tRESH tNRESS
(n-1)
case
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Combination Cycle Write Reset Write Enable
cycle
cycle
cycle
Disable cycle
cycle
cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
tNRESH tRESS tRESH tNRESS WRES (n+1) (n+2)
Note: There restrictions WRES.
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Read Cycle
cycle
cycle
cycle
Disable cycle
cycle
cycle
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
(n+1) (n+2) RRES tODIS HIGH-Z tOEN (n+3) (n+4)
Read Reset Cycle
cycle
cycle
Reset cycle
cycle
cycle
tRCK RRES tNRESH tRESS tRESH tNRESS
(n-1)
case
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Combination Cycle Read Reset Read Enable
cycle
cycle
cycle
Disable cycle
cycle
cycle
tRCK tNRESH tRESS tRESH tNRESS tRCKH tRCKL tREH tNRES tNREH tRES
RRES (n+1) (n+2) tODIS
HIGH-Z
tOEN
Note: There restrictions RRES.
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Attentions when Write Cycle Read Cycle Approach Each Other
interval cycles more between write cycle read cycle should secured, when write cycle goes ahead read cycle following conditions, that interval less than cycles forbidden. WRES, RRES="H"; RE="L", Both write side read side activated continuously Either write side read side temporarily stopped owing stop When this restriction interval broken these conditions, writing data guaranteed, reading data isn't guaranteed only during breaking also during following cycles after applied. this cycles, read disable read reset cycles counted. following condition exception restrict forbid intervals less than cycles. Either write side read side temporarily stopped owing reset cycles (WRES RRES="L") disable cycles ="H")
Note: Also, when address counter incremented last cycle 1-line then returned cycle, interval cycles more between write read cycles should secured, taking account that they cyclic serial lines.
n+16 cycle n+17 cycle
Write disable cycle
n+18 cycle n+19 cycle n+20 cycle n+21 cycle
n+22 cycle n+23 cycle
n+16 n+17 n+18 n+19 n+20 n+21 n+22 n+23
m15; WRES,RRES=H; "m", interval between write cycle read cycle WE,RE=L
cycle
cycle
cycle
cycle
cycle
cycle
cycle
cycle
Read disable cycle
HIGH-Z invalid invalid
read data defined owing write disable cycle.
read data forbidden cycles undefined.
read data cycles after forbidden cycles undefined.
conditions that read cycle goes ahead write cycle that write cycle read cycle accordant, exceptions restriction forbid intervals less than 15cycles.
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Variable Length Delay Bits
1-line length (cycle number) each mode shown table. Operation MODE 1-line length MODE MODE 262144-cycle MODE 786432-cycle MODE 524288-cycle (A-system), 262144-cycle (C-system) MODE 524288-cycle following, case MODE MODE (1-line length 262144-cycle) explained example.
1-line (262144-bit) Delay
read cycles, output data read (first) rising edge (i.e. start cycle write cycles, input data written (second) rising edge (i.e. cycle 1-line delay made easily according control method following figure.
Reset cycle cycle cycle cycle 262142 cycle 262143 cycle 262144 cycle (0') 262145 cycle (1') 262146 cycle (2')
tRESS tRESH WRES RRES
(262141)
(262142)
(262143)
(0')
(1')
(2')
262144 cycle
N-bit Delay
(Reset cycle corresponding delay length)
Reset cycle cycle cycle cycle cycle Reset cycle cycle (0') cycle (1') cycle (2')
tRESS tRESH WRES RRES tRESS tRESH
(n-1)
(0')
(1')
(2')
Delay length
262144
Note: interval cycles more between write cycle read cycle should secured read data written certain cycle.
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M66288FP
N-bit Delay
(Sliding timings WRES RRES cycle corresponding delay length)
Reset cycle cycle cycle cycle cycle Reset cycle cycle cycle cycle cycle cycle cycle cycle cycle
side side
tRESS tRESH WRES tRESS tRESH RRES
(n-2) (n-1)
(n+1) (n+2) (n+3)
Delay length
262144
N-bit Delay
(Sliding address disabling cycle corresponding delay length)
Reset cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
side side
tRESS tRESH WRES RRES
(n-2) (n-1)
tNREH tRES
(n+1) (n+2) (n+3)
Delay length HIGH-Z
262144
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page
M66288FP
Shortest Reading Written Data Cycle when Write Read Operated Asynchronously
interval cycles more between write cycle read cycle should secured should inputted cycles more based beginning write cycle timing read written data (data fetched rising edge shown following figure) with cycles write side. read side, cycles should started after completion n+15 cycles write side following figure). Output data becomes undefined when these restrictions filled.
Reference
cycles more required WCK. cycle cycle cycle n+14 cycle n+15 cycle n+16 cycle n+17 cycle n+18 cycle n+19 cycle
(n-1)
(n+1)
(n+14)
(n+15)
(n+16)
(n+17)
(n+18)
(n+19)
cycles more required RCK.
cycle cycle
cycle
invalid
(n+1)
Longest Reading Written Data Cycle: 1-line Delay
Data output cycle <1>* read immediately before until start cycle <1>* read side start cycle <2>* write side over each other.
REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page
M66288FP
PACKAGE OUTLINE
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REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page
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