5120 8-Bit Line Memory REJ03F0254-0200 Rev.2.00 2007 M66281F

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5120 8-Bit Line Memory REJ03F0254-0200 Rev.2.00 2007 M66281F

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M66281FP
5120 8-Bit Line Memory
REJ03F0254-0200 Rev.2.00 2007
M66281FP high speed line memory that uses high performance silicon gate CMOS process technology adopts FIFO (First First Out) structure consisting 5120 words bits Since memory available simultaneously output line delay line delay data, M66281FP optimal compensation data multiple lines.
Features
Memory configuration: 5120 words bits (dynamic memory) High speed cycle: (Min) High speed access: (Max) Output hold: (Min) Reading writing operations completely carried independently asynchronously Variable length delay Input/output: direct connection allowable Output: states Q07: line delay Q17: line delay
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
Data outputs
Data outputs
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
Write enable input WRESB Write reset input Write clock input
Read enable input
Memory array 5120 words bits Memory only line delay data Memory only line delay data
RRESB Read reset input
Read clock input
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Arrangement
WRESB
RRESB
M66281FP
(Top view) Outline: PRQP0048JA-A (48P6S-A)
connection
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Absolute Maximum Ratings
70°C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Note: Symbol Tstg Ratings -0.3 +4.6 -0.3 -0.3 Unit Conditions Value based
63°C. 63°C derated
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating temperature Symbol Topr 3.15 Unit
Electrical Characteristics
70°C, unless otherwise noted)
Item High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Symbol Unit WEB, WRESB, WCK, REB, RRESB, RCK, WEB, WRESB, WCK, REB, RRESB, RCK, Test Conditions
Low-level input current
-1.0
Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
IOZH IOZL
-5.0
VCC, GND, Output open tWCK, tRCK
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Function
When write enable input "L", contents data inputs written into memory only line delay data synchronization with rising edge write clock input perform writing operation. When this case, write address counter memory only line delay data incremented simultaneously. When "H", writing operation inhibited write address counter memory only line delay data stops. When write reset input WRESB "L", write address counter memory only line delay data initialized. When read enable input "L", contents memory only line delay data output data outputs contents memory only line delay data output synchronization with rising edge read clock input perform reading operation. When this case, read address counters memory only line delay data memory only line delay data incremented simultaneously. addition, data written into memory only line delay data synchronization with rising edge RCK. When this case, write address counter memory only line delay data then incremented. When "H", operation reading data from memory only line delay from memory only line delay data inhibited read address counter each memory stops. Outputs placed high impedance state. addition, write address counter memory only line delay data then stops. When read reset input RRESB "L", read address counters memory only line delay data well write address counter read address counter memory only line delay data then initialized.
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Switching Characteristics
70°C, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time Symbol tOEN tODIS Unit
Timing Requirements
70°C, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) pulse width Write clock (WCK) pulse width Read clock (RCK) cycle Read clock (RCK) pulse width Read clock (RCK) pulse width Input data setup time Input data hold time Reset setup time WCK/RCK Reset hold time WCK/RCK Reset non-selection setup time WCK/RCK Reset non-selection hold time WCK/RCK setup time hold time non-selection setup time non-selection hold time setup time hold time non-selection setup time non-selection hold time Input pulse up/down time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH Unit
Notes: Perform reset operation after turning power supply. line access, following conditions must satisfied: high-level period 5120 tWCK WRESB low-level period high-level period 5120 tRCK RRESB low-level period
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Switching Characteristics Measurement Circuit
tAC, tOEN, tODIS
Input pulse level:
Input pulse up/down time: Judging voltage Input:
Output: (However, tODIS (LZ) judged with output amplitude, while tODIS (HZ) judged with output amplitude) Load capacitance includes floating capacity connected lines input capacitance probe.
Item tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Close Open Close Open Open Close Open Close
tODIS tOEN Measurement Condition
tODIS (HZ) tODIS (LZ) tOEN (ZL) tOEN (ZH)
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Operation Timing
Write Cycle
cycle cycle cycle Disable cycle cycle cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WRESB
Write Reset Cycle
cycle cycle Reset cycle cycle cycle cycle
tWCK tNRESH tRESS tRESH tNRESS
WRESB
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP Matters that Needs Attention when Stops
cycle cycle cycle Disable cycle
tWCK tNWES
Period writing data into memory
Period writing data into memory WRESB
Input data cycle read rising edge after cycle writing operation starts low-level period cycle. writing operation complete falling edge after cycle. stop reading write data cycle, enter before rising edge after cycle. When cycle next cycle disable cycle, cycle requires entered after disable cycle well.
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP Read Cycle
cycle cycle cycle Disable cycle cycle cycle
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tODIS
tOEN
(Q1n)
HIGH-Z
RRESB
Read Reset Cycle
cycle cycle Reset cycle cycle cycle cycle
tRCK tNRESH tRESS tRESH tNRESS
RRESB
(Q1n)
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP Notes Reading Written Data Read Disable When writing operation performed cycle cycle writing side read disable period after cycle reading side, output cycle cycle after read enable invalid. output cycle after, however, data written read disable period output.
cycle cycle cycle cycle cycle cycle cycle cycle cycle
cycle
Disable cycle
cycle
cycle cycle
tODIS HIGH-Z
tOEN
(Q1n)
Invalid
Invalid
WRESB RRESB
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Variable Length Delay
Line (5120 Bits) Delay Input data written rising edge after write cycle output data read rising edge before read cycle easily make line delay.
5120 cycle 5121 cycle 5122 cycle (0') (1') (2')
cycle
cycle
cycle
5118 cycle 5119 cycle
tRESS tRESH
WRESB RRESB
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycle
(Q1n)
WEB,
n-bit Delay (Reset cycles according delay length)
cycle cycle cycle (0') cycle cycle cycle (1') (2') (3')
cycle
cycle
cycle
tRESS tRESH tRESS tRESH
WRESB RRESB
(0')
(1')
(2')
(3')
cycle
(Q1n)
WEB,
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP n-bit Delay (Slides input timings WRESB RRESB cycles according delay length)
cycle cycle cycle cycle cycle cycle cycle cycle cycle
tRESS tRESH
WRESB
tRESS tRESH
RRESB
cycle
(Q1n)
WEB,
n-bit Delay (Slides address disabling period according delay length)
cycle cycle cycle cycle cycle cycle cycle cycle
tRESS tRESH
WRESB RRESB
tNREH tRES
cycle
(Q1n)
HIGH-Z
Invalid
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP Reading Shortest n-cycle Write Data (Reading side cycle ends after writing side cycle) When reading side cycle ends before writing side cycle, output cycle made invalid. following diagram, reading side cycle writing side cycle overlap each other. This example read cycle data shortest time. When this case, reading operation cycle invalid.
cycle
cycle
cycle
cycle
cycle
cycle
cycle
(Q1n)
Invalid
Reading Longest n-cycle Write Data "n": Line Delay (When writing side n-cycle starts, reading side cycle then starts) Output cycle <1>* read until start reading side cycle start writing side cycle <2>* overlap each other.
cycle <1>*
cycle <2>*
cycle <2>*
<1>*
<1>*
<2>*
<2>*
<2>*
cycle <0>*
cycle <1>*
cycle <1>*
(Q1n)
<0>*
<0>*
<1>*
<1>*
<1>*
Note: <0>*, <1>* <2>* indicate value lines.
REJ03F0254-0200 Rev.2.00 2007 Page
M66281FP
Application Example
Scan Resolution Compensation Circuit with Laplacian Filter
line image data
M66281 line delay
line image data
Adder
Compensated image data
Subtractor
line delay
scan direction
Main scan direction
line line line Laplacian coefficient
REJ03F0254-0200 Rev.2.00 2007 Page
Adder
line image data
M66281FP
Package Dimensions
JEITA Package Code P-QFP48-7x10-0.65 RENESAS Code PRQP0048JA-A Previous Code 48P6S-A MASS[Typ.] 0.3g
Reference Symbol
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Dimension Millimeters
Index mark
Detail
REJ03F0254-0200 Rev.2.00 2007 Page
10.0 10.2 1.85 11.7 12.0 12.3 2.15 0.25 0.35 0.13 0.15 0.65 0.13 0.10 0.775 0.575
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5120 8-Bit Line Memory REJ03F0254-0200 Rev.2.00 2007 M66281F

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