5120 8-Bit Line Memory REJ03F0253-0200 Rev.2.00 2007 M66280F

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5120 8-Bit Line Memory REJ03F0253-0200 Rev.2.00 2007 M66280F

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M66280FP
5120 8-Bit Line Memory
REJ03F0253-0200 Rev.2.00 2007
M66280FP high speed line memory that uses high performance silicon gate CMOS process technology adopts FIFO (First First Out) structure consisting 5120 words bits. M66280FP, performing reading writing operations different cycles independently asynchronously, optimal buffer memory used between equipment different data processing speeds.
Features
Memory configuration: 5120 words bits (dynamic memory) High speed cycle: (Min) High speed access: (Max) Output hold: (Min) Reading writing operations completely carried independently asynchronously Variable length delay Input/output: direct connection allowable Output: states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
Data outputs
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
Write enable input WRESB Write reset input Write clock input
Read enable input
Memory array 5120 bits
RRESB Read reset input
Read clock input
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Arrangement
M66280FP RRESB
Data output Read enable input Read reset input Read clock input
Data input Write enable input
WRESB Write reset input
Write clock input
Data output
Data input
(Top view) Outline: PRSP0024GA-A (24P2Q-A)
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Absolute Maximum Ratings
70°C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Symbol Tstg Ratings -0.3 +4.6 -0.3 -0.3 Unit 25°C Conditions Value based
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating temperature Symbol Topr 3.15 Unit
Electrical Characteristics
70°C, unless otherwise noted)
Item High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Symbol 0.55 Unit Test Conditions
WEB, WRESB, WCK, REB, RRESB, RCK, WEB, WRESB, WCK, REB, RRESB, RCK,
Low-level input current
-1.0
Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
IOZH IOZL
-5.0
VCC, GND, Output open tWCK, tRCK
Function
When write enable input "L", contents data inputs read synchronization with rising edge write clock input perform writing operation. When this case, write address counter also incremented simultaneously. When "H", writing operation inhibited write address counter stops. When write reset input WRESB "L", write address counter initialized. When read enable input "L", contents memory output data outputs synchronization with rising edge read clock input perform reading operation. When this case, read address counter incremented simultaneously. When "H", reading operation inhibited read address counter stops. outputs placed high impedance state. When read reset input RRESB "L", read address counter initialized.
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Switching Characteristics
70°C, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time Symbol tOEN tODIS Unit
Timing Requirements
70°C, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) pulse width Write clock (WCK) pulse width Read clock (RCK) cycle Read clock (RCK) pulse width Read clock (RCK) pulse width Input data setup time Input data hold time Reset setup time WCK/RCK Reset hold time WCK/RCK Reset non-selection setup time WCK/RCK Reset non-selection hold time WCK/RCK setup time hold time non-selection setup time non-selection hold time setup time hold time non-selection setup time non-selection hold time Input pulse up/down time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH Unit
Notes: Perform reset operation after turning power supply. line access, following conditions must satisfied: high-level period 5120 tWCK WRESB low-level period high-level period 5120 tRCK RRESB low-level period
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Switching Characteristics Measurement Circuit
tAC, tOEN, tODIS
Input pulse level:
Input pulse up/down time: Judging voltage Input:
Output: (However, tODIS (LZ) judged with output amplitude, while tODIS (HZ) judged with output amplitude) Load capacitance includes floating capacity connected lines input capacitance probe.
Item tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Close Open Close Open Open Close Open Close
tODIS tOEN Measurement Condition
tODIS (HZ) tODIS (LZ) tOEN (ZL) tOEN (ZH)
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Operation Timing
Write Cycle
cycle cycle cycle Disable cycle cycle cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WRESB
Write Reset Cycle
cycle cycle Reset cycle cycle cycle cycle
tWCK tNRESH tRESS tRESH tNRESS
WRESB
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP Matters that Needs Attention when Stops
cycle cycle cycle Disable cycle
tWCK tNWES
Period writing data into memory
Period writing data into memory WRESB
Input data cycle read rising edge after cycle writing operation starts low-level period cycle. writing operation complete falling edge after cycle. stop reading write data cycle, enter before rising edge after cycle. When cycle next cycle disable cycle, cycle requires entered after disable cycle well.
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP Read Cycle
cycle cycle cycle Disable cycle cycle cycle
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tODIS
tOEN
HIGH-Z
RRESB
Read Reset Cycle
cycle cycle Reset cycle cycle cycle cycle
tRCK tNRESH tRESS tRESH tNRESS
RRESB
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Variable Length Delay
Line (5120 Bits) Delay Input data written rising edge after write cycle output data read rising edge before read cycle easily make line delay.
cycle cycle cycle 5118 cycle 5119 cycle 5120 cycle 5121 cycle 5122 cycle (0') (1') (2')
tRESS tRESH
WRESB RRESB
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycle
WEB,
n-bit Delay (Reset cycles according delay length)
cycle cycle
cycle
cycle cycle
cycle (0')
cycle cycle cycle (1') (2') (3')
tRESS tRESH
tRESS tRESH
WRESB RRESB
(0')
(1')
(2')
(3')
cycle
WEB,
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP n-bit Delay (Slides input timings WRESB RRESB cycles according delay length)
cycle cycle cycle cycle cycle cycle cycle cycle cycle
tRESS tRESH
WRESB
tRESS tRESH
RRESB
cycle
WEB,
n-bit Delay (Slides address disabling period according delay length)
cycle cycle cycle cycle cycle cycle cycle cycle
tRESS tRESH
WRESB RRESB
tNREH tRES
cycle HIGH-Z
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP Reading Shortest n-cycle Write Data (Reading side cycle starts after writing side cycle) When reading side cycle starts before writing side cycle, output cycle made invalid. following diagram, reading operation cycle invalid.
cycle
cycle
cycle
cycle
cycle
cycle
cycle
Invalid
Reading Longest n-cycle Write Data "n": Line Delay (When writing side n-cycle <2>* starts, reading side cycle <1>* then starts) Output cycle <1>* read until start reading side cycle start writing side cycle <2>* overlap each other.
cycle <1>*
cycle <2>*
cycle <2>*
<1>*
<1>*
<2>*
<2>*
<2>*
cycle <0>*
cycle <1>*
cycle <1>*
<0>*
<0>*
<1>*
<1>*
<1>*
Note: <0>*, <1>* <2>* indicate value lines.
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Application Example
Scan Resolution Compensation Circuit with Laplacian Filter
line image data
M66280
line image data
Adder
line delay
Compensated image data
Subtractor
M66280
line image data
Adder
line delay
scan direction
Main scan direction
line line line Laplacian coefficient
REJ03F0253-0200 Rev.2.00 2007 Page
M66280FP
Package Dimensions
JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Index mark
Reference Symbol
Dimension Millimeters
Detail
10.0 10.1 10.2 0.35 0.45 0.18 0.25 0.65 0.95 0.10
REJ03F0253-0200 Rev.2.00 2007 Page
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5120 8-Bit Line Memory REJ03F0253-0200 Rev.2.00 2007 M66280F

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