Operation Panel Controller REJ03F0267-0200 Rev.2.00 2008 M66

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Operation Panel Controller REJ03F0267-0200 Rev.2.00 2008 M66

Datasheet Thumbnail

Top Searches for this datasheet

M66271FP
Operation Panel Controller
REJ03F0267-0200 Rev.2.00 2008
M66271FP graphic display-only controller displaying high duty matrix type which used widely PPC, multi-function telephones. capable controlling monochrome system dots. built-in 9600-byte VRAM display data memory. VRAM addresses externally opened. Address mapping memory space allows direct addressing display data from MPU, thus providing efficient display data processing such drawing. built-in arbiter circuit (cycle steal system) which gives priority display access allows timing-free access from VRAM, preventing display screen distortion. provides interface with 8-bit/16-bit with READY (WAIT) pin. this function module built-in system lessening connect pins between MPU.
Features
Displayable Monochrome matrix type 76800 dots (equivalent dots) Maximum display duty: 1/240 (set line) 1/255 (Max) Display memory Built-in 9600-byte (76800-bit) VRAM (equivalent screen dots LCD) addresses built-in VRAM externally opened. Interface with Capability switching 8-bit type MPU/16-bit type With WAIT output (Accessing register from without WAIT output. Accessing VRAM from with WAIT output.) Capability controlling LWR/HWR interface with 16-bit MPU. Interface with display data 4-bit parallel output kinds control signals: Display functions Graphic display only (characters drawn graphically) Binary display only (without tone display function) Vertical scrolling allowed within memory range (small size only) Additional function module built-in system kinds interface with MPU: <4:1>, <7:0>, IOCS, LWR, Accessing VRAM from through register Capability interfacing with 8-bit type only single power supply 80-pin
Application
PPC/FAX operation panel, display/operation panel other equipment Multi-function/public telephones PDA/electronic notebook/information terminal Other applications using 76800 dots less
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Block Diagram
address
<13:0>
Address buffer
LCDENB
control signal Display data transfer clock Display data latch pulse First line marker signal alternating signal
Control register
display timing control circuit
data
<15:0>
Data buffer
VRAM
Control register chip select VRAM chip select
IOCS High write strobe write strobe Read strobe 8/16 select MPUSEL Reset RESET high enable clock MPUCLK Wait WAIT
9600-byte
display data control circuit
<3:0> data
display
control circuit
arbiter timing control Clock control
(Basic timing control)
Oscillator input Oscillator output
OSC1 OSC2
(Cycle steal control)
Block Diagram case module built-In system)
pins
address
<4:1>
Address buffer
LCDENB
Control register
display timing control circuit
control signal Display data transfer clock Display data latch pulse First line marker signal alternating signal
data
<7:0>
Data buffer
VRAM address index register Data port register
VRAM 9600-byte
display data control circuit
Control register chip select
IOCS
<3:0>
display data
write strobe Read strobe
control circuit
Oscillator input Oscillator output
OSC1 OSC2
Clock control
(Basic timing control)
arbiter timing control
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Display data transfer clock
Display data latch pulse First line marker
display data
Oscillator input
Arrangement
Oscillator output
OSC1 OSC2
Control register chip select High write strobe write strobe Read strobe VRAM chip select Wait clock Reset 8/16 select high enable
REJ03F0267-0200 Rev.2.00 2008 Page
IOCS WAIT MPUCLK RESET MPUSEL
M66271FP
(Top view)
address
alternating signal LCDENB control signal <15> <14> <13> <12> data <11> <10>
data
Outline: PRQP0080GB-A (80P6N-A)
N.C: connection
<13> <12> <11> address <10>
M66271FP
Item interface Name <15:0> Input/ Output Input/ Output Input Function data Connect data bus. Selecting 8-bit MPUSEL input, <15:8> connect address Connect address bus. When selecting 8-bit MPU, <13:0>. selecting16-bit MPU, <13:1> address with combining method access internal VRAM (Refer figure <4:0> selecting address control register. Chip select input control register When this "L", select internal control register. Assign space MPU. Chip select input VRAM When this "L", select internal VRAM. Assign memory space MPU. High-write strobe input When this "L", data write internal VRAM. valid only using 16bit controlled byte access HWR. (Refer figure Low-write strobe input When this ''L", data write internal control register VRAM. (Refer figure Read strobe input When this "L", data read from internal control register VRAM. (Refer figure 8/16-bit select input According MPU, "VSS" 8-bit "VDD" 16-bit Reset input reset signal MPU. When this "L", initialize internal control register counter. clock Input clock. Bus-high-enable input This valid when using 16-bit controlled byte access (Refer figure Connect "VDD" when using 8-bit MPU. ''L'' when using additional function module built-in system. WAIT output This signal makes WAIT MPU. Change WAIT ''L'' timing falling edge overlapping with HWR). return synchronizing with rising edge MPUCLK after internal processing. (Output WAIT only when requested access from VRAM during cycle steal access.) Display data Transfer display data with 4-bit parallel signal. Mutually output upper/lower data every output. Display data transfer clock Shift clock transfer display data LCD. Take display data <3:0> falling edge Display data latch pulse This clock both latch pulse display data transfer scanning signal. output when finish transfer display data line. Latch display data transfer scanning signal falling edge First line marker signal Output start pulse scanning line. This signal active, driving scanning line catch falling edge alternating signal output Signal driving alternating current. (ON/OFF) control signal output Output data which mode register (R1) control register. This signal controlling power supply, because LCDENB RESET. Input oscillator Generate internal clock. crystal oscillator external clock signal. Output oscillator Power supply (source Ground connection Number Pins
<13:0>
IOCS MPUSEL RESET MPUCLK
Input Input Input
Input
Input
Input Input
Input Input
WAIT
Output
interface
<3:0>
Output
Output
Output
Output
LCDENB
Output Output
Oscillator Others
OSC1 OSC2
Input Output
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Absolute Maximum Ratings
+70°C unless otherwise noted)
Item Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature Tstg Symbol Ratings -0.3 +6.5 -0.3 -0.3 +150 Unit
Recommended Operating Conditions
+70°C unless otherwise noted)
Item Supply voltage Supply voltage Input voltage Output voltage Operating temperature Symbol Topr Unit
Electrical Characteristics
(VDD 10%, +70°C unless otherwise noted)
Item High-level input voltage inputs except OSC1, RESET Low-level input voltage MPUSEL High-level input voltage Low-level input voltage Positive-going threshold voltage Negative-going threshold voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Operating supply current (Average) OSC1 MPUSEL, RESET Symbol outputs except OSC2 outputs <15:0> OSC2 IOZH IOZL 1.25 Unit Test Conditions fosc MHz, Output open IOCS, Other's (valid)
<15:0>
Stand-by supply current
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Switching Characteristics
(VDD 10%, +70°C,
Item IOCS data access time data access time data access time Output disable time after IOCS Output disable time after Output disable time after WAIT output propagation time after WAIT output propagation time after WAIT output propagation time after WAIT output propagation time after MPUCLK output propagation time after output propagation time after access time output propagation time after output propagation time after LCDENB output propagation time after Data definite time before canceling WAIT Symbol (IOCS-D) (MCS-D) (RD-D) tdis (IOCS-D) tdis (MCS-D) tdis (RD-D) tpHL (MCS-WAIT) tpHL (WR-WAIT) tpHL (RD-WAIT) tpLH (CLK-WAIT) (OSC-CP) tpLH (OSC-LP) tpHL (OSC-LP) (UD) tpLH (OSC-FLM) tpHL (OSC-FLM) (OSC-M) tpLH (OSC-LE) tpHL (OSC-LE) (D-WAIT) Unit
Timing Requirements
(VDD 10%, +70°C) Accessing Control Register
Item IOCS pulse width pulse width Data time before falling edge IOCS Data time before falling edge Data hold time after rising edge IOCS Date hold time after rising edge Address time before falling edge IOCS Address time before falling edge Address time before falling edge Address hold time after rising edge IOCS Address hold time after rising edge Address hold time after rising edge Symbol (IOCS) (LWR) (D-IOCS) (D-LWR) (IOCS-D) (LWR-D) (A-IOCS) (A-LWR) (A-RD) (IOCS-A) (LWR-A) (RD-A) Unit
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Accessing VRAM
Item pulse width pulse width Data time before falling edge Data time before falling edge Data hold time after rising edge Data hold time after rising edge Address time before falling edge Address time before falling edge Address time before falling edge Address hold time after rising edge Address hold time after rising edge Address hold time after rising edge Symbol (MCS) (WR) (D-MCS) (D-WR) (MCS-D) (WR-D) (A-MCS) (A-WR) (A-RD) (MCS-A) (WR-A) (RD-A) Unit
Clock Accessing Display
Item MPUCLK cycle time MPUCLK pulse width MPUCLK pulse width cycle time "H'' pulse width pulse width cycle time pulse width pulse width pulse width Note: Symbol (CLK) (CLK) (CLK) (OSC) (OSC) (OSC) (CP) (CP) (CP) (FLM) (CLK) (OSC) (OSC) (1/n) (OSC) (1/n) (OSC) (1/n) Unit
Clock frequency OSC1 input less than fmax MHz. Limit clock internal operation fmax MHz. When OSC1 more than from external input, clock using division OSCC register. Division with rising edge OSC1 input. Division OSC1 Setting value register
Test Circuit
Item
Closed Open Closed Open
Open Closed Open Closed
Input
<15:0>
tdis (LZ) tdis (HZ) (ZL) (ZH)
Input pulse level: Input pulse rise/fall time: Input decision voltage:
Outputs except <15:0>
Output decision voltage: VDD/2 (However, tdis (LZ) output amplitude tdis
(HZ)
that decision.)
Load capacity include float capacity connection input capacity probe.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Outline
M66271FP graphic display only controller displaying matrix type LCD. This built-in display data memory (VRAM) which equivalent dots LCD. Control register When access control register from side, IOCS, LWR, <4:0> <7:0>. Refer table when control type inputs. Control registers normal mode function exclusive register module built-in system. VRAM When access VRAM from side, MCS, HWR, LWR, BHE, <13:0> <15:0>. enable correspond both 8-bit 16-bit using MPUSEL input. Refer figure table form VRAM input setting 8/16-bit MPU. Cycle steal system Cycle steal interact method transferring display data from VRAM accessing VRAM from basic cycle OSC. Basic timing clocks OSC, assign first clock access from VRAM second clock transfer display data from VRAM LCD. accessing VRAM from MPU, output WAIT. Change WAIT timing falling edge overlapping with LWR/HWR). return synchronizing with rising edge MPUCLK after internal processing. Cycle steal system transfer data with more efficient. This function access with cycle steal method taking WAIT during display term with necessity display data transfer from built-in VRAM LCD. other side, don't output WAIT keeping throughput during horizontal synchronous term with necessity display data transfer from VRAM side. Refer following description cycle steal. Output side display data <3:0> output synchronized with rising edge output bits. output synchronized with falling edge when finish transfer display data line. Enable adjust fittest value frame frequency requested PANEL side with adjusting pulse width register. output, when finish transfer display data line. output alternating signal which signal driving alternating current. M-cycle enable variably M-cycle variable register line unit, enable utilize preventing from being inferior.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Difference VRAM between 8-bit 16-bit
When accessing built-in VRAM 8-bit
(MPUSEL "L", "H", "H": set)
<13:0> <7:0>
<13:0>
VRAM
<7:0> <7:0>
9600-byte
When accessing built-in VRAM 16-bit
(2-1) case byte access (MPUSEL "H", "H": set)
(2-2) case byte access (MPUSEL "H", "H", "H": set)
<13:1>
<13:1> <7:0> <7:0>
<13:1>
VRAM 4800-byte (Lower byte)
<13:1>
<7:0>
<7:0>
VRAM
<7:0> <7:0>
4800-byte (Lower byte)
<13:1>
<13:1>
VRAM
VRAM
4800-byte
<15:8>
(Upper byte)
<15:8> <15:8>
<15:8>
4800-byte
<15:8> <15:8>
(Upper byte)
Figure Difference VRAM between 8-bit 16-bit
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Combination Control Input Pins Interface
Table show conditions input setting when access control register VRAM from MPU. Access control register (Use address <4:0>, Data <7:0>) Table
IOCS Operation Write control register Read from control register Invalid
Writing VRAM (2-1) When 8-bit (MPUSEL "L", "H": set) Table
Address Invalid Write Invalid Even Address Write Invalid Invalid Valid Data Width 8-bit
(2-2) When 16-bit controls byte access with BHE, MPUSEL "H": set) Table
Upper Byte Write Invalid Write Invalid Invalid Invalid Invalid Invalid Lower Byte Write Invalid Invalid Invalid Write Invalid Write Invalid Valid Data Width 16-bit Upper 8-bit Lower 8-bit Lower 8-bit Even "H", enable write
(2-3) When 16-bit controls byte access with HWR, MPUSEL "H": set) Table
Upper Byte Write Write Invalid Invalid Lower Byte Write Invalid Write Invalid Valid Data Width 16-bit Upper 8-bit Lower 8-bit
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Reading from VRAM (3-1) When 8-bit (MPUSEL "L", "H": set) Table
Address Invalid Read Invalid Even Address Read Invalid Invalid Valid Data Width 8-bit
(3-2) When 16-bit (MPUSEL ''H": set) Table
Note: Upper Byte Read Invalid Lower Byte Read Invalid Valid Data Width 16-bit
Avoid setting combination except above, cause error action. "H''
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Description Cycle Steal
Basic Timing Basic timing M66271FP clocks (internal clock after dividing OSC1 input). Assign first clock accessing from VRAM second clock transferring display data from VRAM LCD.
Access from VRAM Data transfer from VRAM
(Internal clock after dividing OSC1 input)
output
(Display data transfer)
Basic cycle
Figure Basic Timing
Operation Cycle Access (During WAIT Output) Writing reading operation VRAM during cycle steal needs cycle best case cycles worst case, according condition internal cycle steal staring access requested from MPU.
Ex.) Assuming that input later than input.
Best case
WAIT
Cycle access
Cycle access
Cycle access
Cycle access
Cycle access
Cancel WAIT, when synchronize with rising edge MPUCLK
MPUCLK
Worst case
WAIT
Cancel WAIT, when synchronize with rising edge MPUCLK
MPUCLK
Figure Operation Cycle Access
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Function Cycle Steal Control M66271FP function processing data line with more efficient. This function access with cycle steal method taking WAIT during display term with necessity display data transfer from built-in VRAM LCD. other side, don't output WAIT keeping throughput during horizontal synchronous term with necessity display data transfer from VRAM side. certainly term accessing with cycle steal method register, controlling error action near horizontal synchronous term.
Ex.) Assuming dots
Line
Output when finish transfer display data with line
<3:0>
Setting register Displaying term (Cycle steal method) (Necessity data transfer from VRAM side) Setting register Horizontal synchronous term necessity data transfer from VRAM side)
Output every transfer display data
4-bit transfer
(Internal signal)
Setting register
Start WAIT according cycle steal access
Access with timing without WAIT MPU.
Start WAIT timing according timing
Figure Function Cycle Steal Control
Handling Oscillator
Crystal oscillator Input from external clock directly
Crystal oscillator OSC1
M66271FP
Clock generator
OSC1
M66271FP
OSC2
Open
OSC2
Note: possible, connect crystal oscillator near pin.
Figure Oscillator
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Additional Function Module Built-in System VRAM address M66271FP externally opened addressing VRAM from directly. When consider module built-in system, connect pins increased. M66271FP additional function module built-in system lessening connect pins. Outline additional function module built-in system. Interface pins with kinds interface with MPU: <4:1>, <7:0>, IOCS, LWR, Method accessing internal VRAM Access internal VRAM through VRAM address index register (IDXL, IDXH) data port register (DP) which used register. following show process accessing VRAM.
Setting MPUSEL,
pins following. "H", "H", WAIT open, MPUCLK "L", MPUSEL "L", "L", "L", <13:5> "L", <15:8> "L", RESET Power reset soft ware reset. case soft ware reset RESET "H": set) Enable change IDXL IDXH, even either.
Select VRAM address index register (IDXL, IDXH), write access address (14-bit) data.
Access after writing mode register (DISP D2)) "0". Always enable access (CSES register "0"), because display signal DISP term wait access. Access without WAIT function.
Select Data port register (DP). Reading/Writing data appointed VRAM address.
VRAM address increased
VRAM address automatically increased when finished access When access continuous address, doesn't need IDXL IDXH.
Application
side <4:1> <7:0> IOCS
M66271FP Segment driver
side
Common driver Graphic PANEL
Crystal Oscillator
Note: module small size only graphics
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Control Register M66271FP kinds control register. mode from control register, IOCS, LWR, <4:0> <7:0>. Kind control register Control Register Table
Kind Register Name Mode register Horizontal display character number register Horizontal synchronous pulse width register Cycle steal enable width register Vertical line number register Display start address register Address
CSES
Data
RESET
DISP
LCDE
Functions Register basic mode. status register cycle steal state. number horizontal display characters line.
Only
OSCC
--------- ------------
-------------- -----------------
pulse width line.
term cycle steal -------------- ---------------- enable access during horizontal synchronous term. number display line --------------- ------------------ vertical direction. display start address --------------- ---------------- VRAM. lower 8-bit ---------- ----------- upper 6-bit SAH. 257FH cycle ---------------- ----------------- alternating signal from Data port register ---------------- ----------------- accessing VRAM through register. address accessing ---------------- IDXL ---------------- VRAM. lower 8-bit IDXL upper 6-bit IDXH. 257FH --------- IDXH ----------- automatically increase continuous address.
cycle variable register Data port register VRAM address index register
Note:
Data port register (DP) VRAM address index register (IDXL, IDXH) exclusive register, when using this module built-in system. When RESET, each register initialize setting which assumed size dots. Then, even each register setting, output signal side, possible alternation LCD.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Description register (2-1) Mode register [R1]
Address 00000 Only CSES wait access Cycle steal access Function Reset
Status register identifying active inactive cycle steal function. during active with cycle steal function. CSES only reading, writing.
Software reset. Surely return reset after reset
Reset Reset
RESET
OSCC Division OSC1 Division Division Division 1/16 Division
division clock internal operation from OSC1 input pin.
When reset, OSCC 000, OSC1 clock doesn't divide. Don't except left table.
DISP Display Display
Control displaying ON/OFF LCD. When reset, DISP display OFF. (D1) "1", when DISP display data <3:0> output reversal mode.
Normal display Reversal display
Control normal/reversal display. When reset, normal display. using permeation method, effect.
LCDE LCDENB output LCDENB output
output data from LCDENB output pin. When reset, LCDE LCDENB output (Vss potential). This function prepared controlling voltage LCD. When power supply after finish each register setting, LCDE "1", supply voltage LCD. Conversely setting power supply OFF, first LCDE "0", voltage OFF. Therefore enable prevent from being unusual voltage This function satisfy need LCD.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP (2-2) Horizontal display characters number register [R2]
Address 00010 Character Number Display Number Function Reset
Note:
number horizontal display characters line extent dots characters) When reset, "28H" characters dots)
Definition number display characters. number display characters means data which corresponding with byte VRAM. case binary, VRAM corresponds display, then character means dots display.
(2-3) Horizontal synchronous pulse width register [R3]
Address 00100 Character Number Function Reset
length horizontal synchronous pulse width which appeared line character unit. Horizontal synchronous pulse output from output pin, changing serial/parallel displaying data. Adjusting this pulse width possible frame frequency fittest value. actual output pulse (LPW setting value 1CP) consideration timing with output.
When reset, "01H" character)
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP (2-4) Cycle steal enable width register [R4]
Address 00110 Character Number Function Reset
During horizontal synchronous term, term access cycle steal method character number unit. Setting value sets below value. When reset, "00H"
Note:
careful with first second byte display data <3:0> output indefinite data when setting value still reset (00H). Surely over 01H. (When select 8-bit MPU, byte indefinite. When 16-bit SAL: byte indefinite. When 16-bit SAL: byte indefinite.)
(2-5) Vertical line number register [R5]
Address 01000 Vertical Line Number Function Reset
combine setting display driving duty LCD. Setting sure adjust number display line LCD. When reset, "F0H" lines).
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP (2-6)
Address 01010
Display start address register [R6,
Display Start Address 0000H 0001H 0002H
Function
Reset 0000H
257FH
01100
output when read SAH. possible display start address extent 257FH 9600 address). Don't over 2580H. When reset, "0000H" Display start address established writing data register. Even only change SAL, surely after SAL. When select 8-bit MPU, start address D0>. When select 16-bit MPU, start address D1>+ D0>. Even selecting 16-bit MPU, enable display start address character unit. case display reading data from VRAM start <15:12>, <D0> "0", start <7:4>, <D0> "1". (Refer figure
(2-7) cycle variable register [R8]
Address 01110 Cycle Toggle change every frame. Toggle change every line (1LP). Toggle change every lines. Toggle change every lines. Function Reset
cycle case 01H, repeat reversal (toggle) every line every count LP). When reset, "00H", toggle signal every frame. recommend this register suitable value user's LCD.
(2-8) Data port register [R9]
Address 10000 Data Port (8-bit) Function Reset (indefinite)
Exclusive data port register module built-in system. Reading writing 8-bit data between VRAM through this register. VRAM address index register (IDXL, IDXH) increased when finished access Output indefinite data when reset.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP (2-9) VRAM address index register [R10, R11]
Address 10010 IDXL
IDXH
Function
Reset 0000H
IDXL Accessing VRAM Address 0000H 0001H 0002H 257FH
10100 IDXH
Exclusive VRAM address index register module built-in system. possible change register only side, because IDXH IDXL independent each other. possible VRAM access address extent 257FH 9600 address). Don't address over 2580H. output when read IDXH When reset, IDXL IDXH "0000H".
Description Display
Relation between Setting Control Register Displaying
horizontal line
Expectant PANEL
Condition control register 76800 dots
horizontal line
Character number horizontal display
Horizontal synchronous pulse width
Vertical line number
<3:0>
Character number dots display Data indefinite
Time processing horizontal line (TH) LPW)
fosc
LPW, CSW: Unit character number SLT: Unit line number fosc: Internal clock frequency after dividing OSC1 input
adjusting LPW, possible frame frequency which requested from PANEL fittest value.
Time processing frame (TFR)
Figure Relation between Setting Control Register Displaying
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Relation between Address VRAM Display
When display start address 0000H
0000H 0001H
VRAM address mapping PANEL
0000H 0001H
VRAM 9600-byte
257EH 257FH
PANEL
257EH 257FH dots
line
When display start address 1000H
0000H 0001H 1000H 1001H
VRAM 9600-byte
1000H 1001H
PANEL
257EH 257FH 0000H 0001H
257EH 257FH
Remark) VRAM address counter return "0000H", after count address "257FH".
Figure Relation between Address VRAM Display
Relation between VRAM Data, Display Display Start Address Register
When select 8-bit
display data Data address VRAM
PANEL
When select 16-bit (SAL: "0")
display data Data address VRAM
PANEL
When select 16-bit (SAL: "1")
Invalid display data
display data Data address VRAM
PANEL
Only upper byte data display start address invalid data (cut data). Output display data normally from next address display start address.
Figure Relation between VRAM Data, Display Display Start Address Register
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Output Signal Side
Ex.) Assuming dots setting characters, characters, lines, OSCC division, toggle line)
Output signal line
OSC1
Division OSC1 Output every display data transfer
<3:0>
Output signal frame
4-bit parallel output Output when finish transfer line display data.
LCDENB output signal
Output finishing transfer first line display data.
Cycle reversing output able register.
OSC1 LCDENB
Reset-1st line frame
RESET OSC1 LCDENB
line frame line-2nd line
OSC1
line 240th line frame-1st line frame line
OSC1
240th line frame line frame
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Timing Diagram
Write Control Register "H")
Without WAIT
(IOCS)
IOCS
(LWR)
WAIT
(D-IOCS)
(D-LWR)
(IOCS-D)
(LWR-D)
<7:0>
(A-IOCS) (A-LWR)
Data input established
(IOCS-A) (LWR-A)
<4:0>
Address established
Read from Control Register (LWR "H")
Without WAIT
IOCS WAIT
(IOCS-D) (RD-D)
tdis (IOCS-D)
tdis (RD-D)
<7:0>
(A-IOCS) (A-RD)
Data output established
(IOCS-A) (RD-A)
<4:0>
Address established
Note: Writing/Reading operation control register performed during overlapping IOCS (LWR RD). Limits IOCS, prescribed input signal last change starting access, input signal first change ending access.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Write VRAM "H")
Term cycle steal access
(MCS)
(WR)
(+HWR) WAIT
(D-MCS) (D-WR) (MCS-D) (WR-D)
<7:0> <15:0>) <13:0> (+BHE)
Data input established
(A-MCS) (A-WR)
(MCS-A) (WR-A)
Address established
Read from VRAM (LWR, "H")
Term cycle steal access WAIT
(MCS-D) (RD-D)
tdis (MCS-D) tdis (RD-D)
<7:0> <15:0>)
Data output established
(A-MCS) (A-RD) (MCS-A) (RD-A)
<13:0>
Address established
Note: Writing/Reading operation VRAM during cycle steal access performed during overlapping [LWR (+HWR) RD]. Limits MCS, (+HWR) prescribed input signal last change starting access, input signal first change ending access.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Write VRAM "H")
Term cycle steal access
(CLK)
(CLK)
(CLK)
MPUCLK
(MCS)
(WR)
(+HWR) WAIT
tpHL (MCS-WAIT)
tpLH (CLK-WAIT)
(D-MCS) tpHL (WR-WAIT)
(D-WR)
(MCS-D)
(WR-D)
<7:0> <15:0>)
<13:0> (+BHE)
Data input established
(A-MCS)
(A-WR)
(MCS-A) (WR-A)
Address established
Read from VRAM (LWR, "H")
Term cycle steal access
(CLK) (CLK) (CLK)
MPUCLK
WAIT
tpHL (MCS-WAIT) tpLH (CLK-WAIT)
tpHL (RD-WAIT) (MCS-D) (RD-D) (D-WAIT)
tdis (MCS-D)
tdis (RD-D)
<7:0> <15:0>)
<13:0>
Data output established
(A-MCS)
(A-RD)
(MCS-A) (RD-A)
Address established
Notes: Reading/writing operation VRAM during cycle steal needs (Internal) best case (Internal) worst case, according condition internal cycle steal starting access requested from MPU. (Internal) Clock cycle time after setting division OSC1. Data output reading established before changing WAIT "H". Limits MCS, (+HWR) prescribed input signal last change starting access, input signal first change ending access. Always once return MCS, (+HWR) after canceling WAIT output. case latching "L", don't output next WAIT, this cause error action.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP Interface Timing with (OSCC division: set) (When OSCC division, clock internal operation OSC1 input.) Transfer display data
(OSC) (OSC) (OSC)
OSC1
(OSC-CP) (CP) (CP) (CP)
tpLH (OSC-LP) tpHL (OSC-LP)
(UD)
<3:0>
Data indefinite
control signal
OSC1
tpLH (OSC-FLM)
tpHL (OSC-FLM)
(FLM)
(OSC-M)
tpLH (OSC-LE) tpHL (OSC-LE)
LCDENB
Note: Output signal side synchronized with clock internal operation. When division 1/16 OSCC register, switching characteristics defined rising edge OSC1.
REJ03F0267-0200 Rev.2.00 2008 Page
M66271FP
Package Dimensions
JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GB-A Previous Code 80P6N-A MASS[Typ.] 1.6g
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Reference Symbol
Dimension Millimeters
Index mark
Detail
REJ03F0267-0200 Rev.2.00 2008 Page
19.8 20.0 20.2 13.8 14.0 14.2 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.35 0.45 0.13 0.15 0.65 0.95 0.10
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: This document provided reference purposes only that Renesas customers select appropriate Renesas products their use. Renesas neither makes warranties representations with respect accuracy completeness information contained this document grants license intellectual property rights other rights Renesas third party with respect information this document. Renesas shall have liability damages infringement intellectual property other rights arising information this document, including, limited product data, diagrams, charts, programs, algorithms, application circuit examples. should products technology described this document purpose military applications such development weapons mass destruction purpose other military use. When exporting products technology described herein, should follow applicable export control laws regulations, procedures required such laws regulations. information included this document such product data, diagrams, charts, programs, algorithms, application circuit examples, current date this document issued. Such information, however, subject change without prior notice. Before purchasing using Renesas products listed this document, please confirm latest product information with Renesas sales office. Also, please regular careful attention additional different information disclosed Renesas such that disclosed through website. (http://www.renesas.com Renesas used reasonable care compiling information included this document, Renesas assumes liability whatsoever damages incurred result errors omissions information included this document. When using otherwise relying information this document, should evaluate information light total system before deciding about applicability such information intended application. Renesas makes representations, warranties guaranties regarding suitability products particular application specifically disclaims liability arising application information this document Renesas products. With exception products specified Renesas suitable automobile applications, Renesas products designed, manufactured tested applications otherwise systems failure malfunction which cause direct threat human life create risk human injury which require especially high quality reliability such safety systems, equipment systems transportation traffic, healthcare, combustion control, aerospace aeronautics, nuclear power, undersea communication transmission. considering products such purposes, please contact Renesas sales office beforehand. Renesas shall have liability damages arising uses forth above. Notwithstanding preceding paragraph, should Renesas products purposes listed below: artificial life support devices systems surgical implantations healthcare intervention (e.g., excision, administration medication, etc.) other purposes that pose direct threat human life Renesas shall have liability damages arising uses forth above purchasers elect Renesas products foregoing applications shall indemnify hold harmless Renesas Technology Corp., affiliated companies their officers, directors, employees against damages arising such applications. should products described herein within range specified Renesas, especially with respect maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation other product characteristics. Renesas shall have liability malfunctions damages arising Renesas products beyond such specified ranges. Although Renesas endeavors improve quality reliability products, products have specific characteristics such occurrence failure certain rate malfunctions under certain conditions. Please sure implement safety measures guard against possibility physical injury, injury damage caused fire event failure Renesas product, such safety design hardware software including limited redundancy, fire control malfunction prevention, appropriate treatment aging degradation other applicable measures. Among others, since evaluation microcomputer software alone very difficult, please evaluate safety final products system manufactured you. case Renesas products listed this document detached from products which Renesas products attached affixed, risk accident such swallowing infants small children very high. should implement safety measures that Renesas products easily detached from your products. Renesas shall have liability damages arising such detachment. This document reproduced duplicated, form, whole part, without prior written approval from Renesas. Please contact Renesas sales office have questions regarding information contained this document, Renesas semiconductor products, have other inquiries.
RENESAS SALES OFFICES
Refer latest detailed information. Renesas Technology America, Inc. Holger Way, Jose, 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> 2715-2888, Fax: <886> 3518-3399 Renesas Technology Singapore Pte. Ltd. Harbour Front Avenue, #06-10, Keppel Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 796-3115, Fax: <82> 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Unit 906, Block Menara Amcorp, Amcorp Trade Centre, No.18, Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
2008. Renesas Technology Corp., rights reserved. Printed Japan.
Colophon .7.2

Operation Panel Controller REJ03F0267-0200 Rev.2.00 2008 M66

Top Searches for this datasheet

Other recent searches