5120 8-Bit Line Memory (FIFO) REJ03F0251-0200 Rev.2.00 2007
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M66257FP
5120 8-Bit Line Memory (FIFO)
REJ03F0251-0200 Rev.2.00 2007
M66257FP high-speed line memory with FIFO (First First Out) structure 5120-word 8-bit double configuration which uses high-performance silicon gate CMOS process technology. allows simultaneous output 1-line delay data 2-line delay data, most suitable data correction over multiple lines. separate clock, enable reset signals write read, most suitable buffer memory between devices with different data processing throughput.
Features
Memory configuration: 5120 words bits (dynamic memory) High-speed cycle: (Min) High-speed access: (Max) Output hold: (Min) Fully independent, asynchronous write read operations Output: states 1-line delay Q07: Q17: 2-line delay
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
Data output
Data output
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
Write enable input WRES Write reset input Write clock input
Read enable input
Memory array 5120-word 8-bit configuration 1-line delay data only memory/ 2-line delay data only memory
RRES
Read reset input
Read clock input
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Arrangement
M66257FP
Data output
RRES WRES
Read enable input Read reset input Read clock input Write enable input Write reset input Write clock input
Data input
(Top view) Outline: PRSP0036GA-A (36P2R-A)
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Absolute Maximum Ratings
70°C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Symbol Tstg Ratings -0.5 +7.0 -0.5 -0.5 Unit Conditions value based 25°C
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating ambient temperature Symbol Topr Unit
Electrical Characteristics
70°C, 10%, unless otherwise noted)
Item input voltage input voltage output voltage output voltage input current Symbol 0.55 Unit Test Conditions
WRES, WCK, RRES, RCK, WRES, WCK, RRES, RCK,
input current
-1.0
state output current state output current Operating mean current dissipation Input capacitance state output capacitance
IOZH IOZL
-5.0
VCC, GND, Output open tWCK, tRCK
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Function
When write enable input "L", contents data inputs written into 1-line delay data only memory synchronization with rise edge write clock input WCK. this time, write address counter 1-line delay data only memory also incremented simultaneously. write functions given below also performed synchronization with rise edge WCK. When "H", write operation 1-line delay data only memory inhibited write address counter 1-line delay data only memory stopped. When write reset input WRES "L", write address counter 1-line delay data only memory initialized. When read enable input "L", contents 1-line delay data only memory output data outputs those 2-line delay data only memory data outputs synchronization with rise read clock input RCK. this time, read address counters 1-line 2-line delay data only memories also incremented simultaneously. Moreover, data written into 2-line delay data only memory synchronization with rise edge RCK. this time, write address 2-line delay data only memory incremented. read functions given below also performed synchronization with rise edge RCK. When "H", read operation from both 1-line delay data only memory 2-line delay data only memory inhibited read address counter each memory stopped. outputs high impedance state. Moreover, write operation 2-line delay data only memory inhibited write address counter 2-line delay data only memory stopped. When read reset input RRES "L", read address counter 1-line delay data only memory, write address counter read address counter 2-line delay data only memory initialized.
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Switching Characteristics
70°C, 10%, unless otherwise noted)
Item Access time Output hold time Output enable time Output disable time Symbol tOEN tODIS Unit
Timing Conditions
70°C, 10%, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) pulse width Write clock (WCK) pulse width Read clock (RCK) cycle Read clock (RCK) pulse width Read clock (RCK) pulse width Input data setup time Input data hold time Reset setup time Reset hold time Reset nonselect setup time Reset nonselect hold time setup time hold time nonselect setup time nonselect hold time setup time hold time nonselect setup time nonselect hold time Input pulse rise/fall time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH Unit
Notes: Reset after power turned 1-line access, following should satisfied: level period 5120 tWCK WRES level period level period 5120 tRCK RRES level period
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Test Circuit
tAC, tOEN, tODIS
Input pulse level:
Input pulse rise/fall time: Decision voltage input: Decision voltage output: (However, tODIS (LZ) output amplitude tODIS (HZ) that decision)
load capacitance includes floating capacitance connection input capacitance probe.
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Closed Open Closed Open Open Closed Open Closed
tODIS/tOEN Test Condition
tODIS (HZ) tODIS (LZ) tOEN (ZL) tOEN (ZH)
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Operating Timing
Write Cycle
Cycle Cycle Cycle Disable cycle Cycle Cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WRES
Write Reset Cycle
Cycle Cycle Reset cycle Cycle Cycle Cycle
tWCK tNRESH tRESS tRESH tNRESS
WRES
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP Read Cycle
Cycle Cycle Cycle Disable cycle Cycle Cycle
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tODIS
tOEN
HIGH-Z
RRES
Read Reset Cycle
Cycle Cycle Reset cycle Cycle Cycle Cycle
tRCK tNRESH tRESS tRESH tNRESS
RRES
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP Note Stop
cycle cycle cycle Disable cycle
tWCK tNWES
Period writing data into memory
Period writing data into memory WRES
Input data cycle read rising edge after cycle. Writing operation starts period cycle ends rising edge after cycle. stop reading write data cycle, input rising edge cycle. When cycle next cycle disable cycle, input cycle required after disable cycle well.
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP Shortest Read Data Written Cycle (Cycle read side should started after cycle write side) When start cycle read side earlier than cycle write side, output cycle becomes invalid. figure shown below, read cycle invalid.
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Invalid
Longest Read Data Written Cycle 1-line Delay (Cycle <1>* read side should started when cycle <2>* write started) Output cycle <1>* read until start reading side cycle start writing side cycle <2>* overlap each other.
Cycle <1>*
Cycle <2>*
Cycle <2>*
<1>*
<1>*
<2>*
<2>*
<2>*
Cycle <0>*
Cycle <1>*
Cycle <1>*
<0>*
<0>*
<1>*
<1>*
<1>*
Note: <0>*, <1>* <2>* indicates line value.
REJ03F0251-0200 Rev.2.00 2007 Page
M66257FP
Application Example
Laplacian Filter Circuit Correction Resolution Secondary Scanning Direction
Line image data
M66257
Line image data
Adder
1-line delay
Corrected image data
Subtractor
2-line delay
Secondary scanning direction
Primary scanning direction
Line Line Line Laplacian coefficient
REJ03F0251-0200 Rev.2.00 2007 Page
Adder
Line image data
M66257FP
Package Dimensions
JEITA Package Code P-SSOP36-8.4x15-0.80 RENESAS Code PRSP0036GA-A Previous Code 36P2R-A MASS[Typ.] 0.5g
NOTE) DIMENSIONS "*1" "*2" INCLUDE MOLD FLASH. DIMENSION "*3" DOES INCLUDE TRIM OFFSET.
Index mark
Reference Symbol
Dimension Millimeters
Detail
14.8 15.0 15.2 0.05 0.35 0.13 0.15 11.63 11.93 12.23 0.65 0.95 0.15
REJ03F0251-0200 Rev.2.00 2007 Page
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