5120 8-Bit Line Memory (FIFO) REJ03F0250-0200 Rev.2.00 2007
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M66256FP
5120 8-Bit Line Memory (FIFO)
REJ03F0250-0200 Rev.2.00 2007
M66256FP high-speed line memory with FIFO (First First Out) structure 5120-word 8-bit configuration which uses high-performance silicon gate CMOS process technology. separate clock, enable reset signals write read, most suitable buffer memory between devices with different data processing throughput.
Features
Memory configuration: 5120 words bits (dynamic memory) High-speed cycle: (Min) High-speed access: (Max) Output hold: (Min) Fully independent, asynchronous write read operations Variable length delay Output: states
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
Data output
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
Write enable input WRES Write reset input Write clock input
Read enable input
Memory array 5120-word 8-bit configuration
RRES
Read reset input
Read clock input
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Arrangement
M66256FP
Data output
Read enable input Read reset input Read clock input
Data output
RRES
WRES
Data input
Write enable input Write reset input Write clock input
Data input
(Top view) Outline: 24P2U-A
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Absolute Maximum Ratings
70°C, unless otherwise noted)
Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Symbol Tstg Ratings -0.5 +7.0 -0.5 -0.5 Unit Conditions value based 25°C
Recommended Operating Conditions
Item Supply voltage Supply voltage Operating ambient temperature Symbol Topr Unit
Electrical Characteristics
70°C, 10%,
Item input voltage input voltage output voltage output voltage input current Symbol 0.55 Unit Test Conditions
WRES, WCK, RRES, RCK, WRES, WCK, RRES, RCK,
input current
-1.0
state output current state output current Operating mean current dissipation Input capacitance state output capacitance
IOZH IOZL
-5.0
VCC, GND, Output open tWCK, tRCK
Function
When write enable input "L", contents data inputs written into memory synchronization with rise edge write clock input WCK. this time, write address counter also incremented simultaneously. write function given below also performed synchronization with rise edge WCK. When "H", write operation memory inhibited write address counter stopped. When write reset input WRES "L", write address counter initialized. When read enable input "L", contents memory output data outputs synchronization with rise edge read clock input RCK. this time, read address counter also incremented simultaneously. read functions given below also performed synchronization with rise edge RCK. When "H", read operation from memory inhibited read address counter stopped. outputs high impedance state. When read reset input RRES "L", read address counter initialized.
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Switching Characteristics
70°C, 10%,
Item Access time Output hold time Output enable time Output disable time Symbol tOEN tODIS Unit
Timing Conditions
70°C, 10%, unless otherwise noted)
Item Write clock (WCK) cycle Write clock (WCK) pulse width Write clock (WCK) pulse width Read clock (RCK) cycle Read clock (RCK) pulse width Read clock (RCK) pulse width Input data setup time Input data hold time Reset setup time Reset hold time Reset nonselect setup time Reset nonselect hold time setup time hold time nonselect setup time nonselect hold time setup time hold time nonselect setup time nonselect hold time Input pulse rise/fall time Data hold time* Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH Unit
Notes: Perform reset operation after turning power supply. 1-line access, following should satisfied: level period 5120 tWCK WRES level period level period 5120 tRCK RRES level period
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Test Circuit
tAC, tOEN, tODIS
Input pulse level:
Input pulse rise/fall time: Decision voltage input: Decision voltage output: (However, tODIS (LZ) output amplitude tODIS (HZ) that decision)
load capacitance includes floating capacitance connection input capacitance probe.
Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Closed Open Closed Open Open Closed Open Closed
tODIS/tOEN Test Condition
tODIS (HZ) tODIS (LZ) tOEN (ZL) tOEN (ZH)
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Operating Timing
Write Cycle
Cycle Cycle Cycle Disable cycle Cycle Cycle
tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WRES
Write Reset Cycle
Cycle Cycle Reset cycle Cycle Cycle Cycle
tWCK tNRESH tRESS tRESH tNRESS
WRES
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP Matters that Needs Attention when Stops
cycle cycle cycle Disable cycle
tWCK tNWES
Period writing data into memory
Period writing data into memory WRES
Input data cycle read rising edge after cycle writing operation starts low-level period cycle. writing operation complete falling edge after cycle. stop reading write data cycle, enter before rising edge after cycle. When cycle next cycle disable cycle, cycle requires entered after disable cycle well.
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP Read Cycle
Cycle Cycle Cycle Disable cycle Cycle Cycle
tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tODIS
tOEN
HIGH-Z
RRES
Read Reset Cycle
Cycle Cycle Reset cycle Cycle Cycle Cycle
tRCK tNRESH tRESS tRESH tNRESS
RRES
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Variable Length Delay Bits
1-line (5120 Bits) Delay write input data written into memory second rise edge cycle, read output data output from memory first rise edge cycle, that 1-line delay made easily.
Cycle 5120 Cycle 5121 Cycle 5122 (0') (1') (2')
Cycle
Cycle
Cycle
Cycle 5118 Cycle 5119
tRESS tRESH
WRES RRES
(5117)
(5118)
(5119)
(0')
(1')
(2')
(3')
5120 cycles
N-bit Delay (Making reset cycle corresponding delay length)
Cycle Cycle Cycle (0') Cycle Cycle Cycle (1') (2') (3')
Cycle
Cycle
Cycle
tRESS tRESH
tRESS tRESH
WRES RRES
(0')
(1')
(2')
(3')
cycles
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP N-bit Delay (Sliding WRES RRES cycle corresponding delay length)
Cycle Cycle Cycle
Cycle Cycle
Cycle
Cycle Cycle Cycle
tRESS tRESH
WRES
tRESS tRESH
RRES
cycles
N-bit Delay (Disabling cycle corresponding delay length)
Cycle Cycle
Cycle
Cycle
Cycle
Cycle Cycle Cycle
tRESS tRESH
WRES RRES
tNREH tRES
cycles HIGH-Z
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP Shortest Read Data Written Cycle (Cycle read side should started after cycle write side) When start cycle read side earlier than cycle write side, output cycle becomes invalid. figure shown below, read cycle invalid.
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Invalid
Longest Read Data Written Cycle 1-line Delay (Cycle <1>* read side should started when cycle <2>* write started) Output cycle <1>* read until start reading side cycle <1>* start writing side cycle <2>* overlap each other.
Cycle <1>*
Cycle <2>*
Cycle <2>*
<1>*
Cycle <0>*
<1>*
(00) <2>*
<2>*
<2>*
Cycle <1>*
Cycle <1>*
<0>*
<0>*
<1>*
<1>*
<1>*
Note: <0>*, <1>* <2>* indicates line value.
REJ03F0250-0200 Rev.2.00 2007 Page
M66256FP
Application Example
Laplacian Filter Circuit Correction Resolution Secondary Scanning Direction
Line image data
M66256
Line image data
Adder
1-line delay
Corrected image data
Subtractor
M66256
Line image data
1-line delay
Secondary scanning direction
Primary scanning direction
Line Line Line Laplacian coefficient
REJ03F0250-0200 Rev.2.00 2007 Page
Adder
M66256FP
Package Dimensions
24P2U-A
EIAJ Package Code SSOP24-P-375-0.80
Plastic 24pin 375mil SSOP
JEDEC Code
Weight(g)
Lead Material Alloy
Recommended Mount
Symbol
Detail
Detail
Dimension Millimeters 2.65 0.35 0.45 0.23 0.25 10.2 10.3 10.4 10.0 10.3 10.6 0.75 9.53 1.27
REJ03F0250-0200 Rev.2.00 2007 Page
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