Standard Clock Generator with Frequency Synthesizer REJ03F0268-02

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Standard Clock Generator with Frequency Synthesizer REJ03F0268-02

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M66238FP
Standard Clock Generator with Frequency Synthesizer
REJ03F0268-0200 Rev.2.00 2008
M66238 that incorporates synthesizer sync clock generator synthesizer covers range minimum steps kHz. sync circuit outputs clock one-shot pulse which synchronized with external trigger signal. Setting dividing ratio allows acquisition sync clock outputs within range 0.78 MHz.
Features
Sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 Sync accuracy (jitter): Trigger input: Polarity selectable One-shot pulse output: Polarity width selectable power supply
Application
Pixel clock generator
Block Diagram
Chip select input Serial data input Serial clock input
SCLK
Serial write control circuit
Command register
Command control circuit
TCKI Test TCKO
Clock input Clock output
XOUT
Crystal oscillator circuit
15-bit counter
12-bit divider
Phase comparator
fvco Sync/divider circuit Sync clock generator CKO/ PLLO output Clock output One-shot pulse output
CKOB PULSE
Reset input RESET
Charge pump
Trigger input
CPIN
Filter connect
DOWN CPOUT
Test Filter connect
load output
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Arrangement
M66238FP
Digital Reset input Chip select input Serial data input Serial clock input Clock output Clock input
Digital
DGND RESET SCLK XOUT DGND DVCC TCKI TCKO
AGND AVCC AGND AVCC AGND CPIN AGND
Analog Analog power supply Analog load output Analog power supply Analog Filter connect Analog
Digital power supply Test
CPOUT Filter connect DGND DVCC DOWN DVCC DGND
Test Digital power supply Digital Trigger input Digital Digital power supply
output CKO/PLLO Clock output One-shot pulse output Sync output power supply Sync output
CKOB PULSE VCCO GNDO
(Top view) Outline: 32P2W-A
Name RESET SCLK XOUT CKOB CKO/PLLO PULSE CPOUT CPIN TCKI TCKO DOWN DVCC DGND VCCO GNDO AVCC AGND Name Reset input Chip select input Serial data input Serial clock input Clock input Clock output Trigger input Clock output output One-shot pulse output Filter connect Filter connect load output Test Test Test Test Digital power supply Digital Sync output power supply Sync output Analog power supply Analog Input Input Input Input Input Output Input Output Output Output Output Input Output Input Output Output Output Function Initialize M66238 internal status. Transfer serial data when "L". Synchronize 32-bit serial data from with SCK, enter. Enter sync clock writing 32-bit serial data. Used connecting crystal oscillator between XOUT. When using external clock signal, connect clock oscillator open XOUT pin. Trigger input clock sync. Output inverted signal. outputs clock synchronized with trigger signal PLLO outputs oscillator clock Output one-shot pulse synchronized with signal. Connect pass filter charge pump output. pass filter input pin. Connect load resistor circuit operation between GND. Shipping test pin. Connect when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Shipping test pin. Keep open when use. Digital power supply pin. Digital pin. Power supply sync output. sync output. Analog power supply pin. Analog pin.
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Power dissipation*1 Storage temperature Note: Symbol Tstg Ratings -0.5 +7.0 -0.5 -0.5 +150 Unit
When board mounted voltages adopt circuit base absolute values displayed maximum minimum values.
Recommended Operating Conditions
70°C)
Item Supply voltage Supply voltage Input voltage Output voltage Operating ambient temperature Note: Symbol Topr 4.75 5.25 Unit
direction current flowing into circuit defined positive sign) direction current flowing defined negative (-sign). Absolute values displayed maximum minimum values.
Electrical Characteristics
70°C,
Item High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Supply current time standstill) Supply current time operation) High-level input current Low-level input current Input capacitance Note: Symbol 0.55 Unit Test Conditions
Measurement circuit; direction current flowing circuit specified positive sign).
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Timing Requirements
70°C,
Item width time hold time width time hold time Clock input frequency Clock input duty Trigger input pulse width Clock input rising time Clock input falling time Symbol (CS) (CS-SCK) (SCK-CS) (SCK) (SIN-SCK) (SCK-SIN) fiDUTY (TR) Unit
Switching Characteristics
70°C,
Item oscillation frequency Synchronous output frequency Synchronous accuracy (jitter) Synchronous clock output start Synchronous clock reversible output start One-shot pulse output start Synchronous clock output stop Synchronous clock reversible output stop One-shot pulse output width Synchronous clock output duty Synchronous clock reversible output duty Note: Symbol fvco fout (CKO) (CKOB) (PULSE) (CKO) (CKOB) (PULSE) foDUTY (CKO) foDUT (CKOB) Unit
fout, (100 fvcoduty) value one-shot pulse output width register.
Measurement Circuit
Input Output
Tested element
Notes:
Waveform switching test Input pulse level XIN: Vcc, Input pulse rising time: Input pulse falling time: Decision voltage Input voltage Output voltage XIN: Vcc/2, outputs: Vcc/2
Electrostatic capacitance: includes floating capacitance connection probe input capacitance.
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
List Register Setting Commands
Setting Setting CKO/PLLO dividing ratio, synthesizer 15-bit generation dividing ratio reference clock generation 12-bit dividing ratio. Setting one-shot pulse polarity width, setting trigger edge, HALT entire M66238, HALT charge pump VCO, phase comparator output UP/DOWN, CKO/PLLO switching. Dummy trigger generation command
Serial Data Write Timing
SCLK
Address
Data
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Register Configuration
Clock frequency setting command Reference clock generation 12-bit division ratio, synthesizer 15-bit division ratio CKO/PLLO division ratio address (A1,
Data Description 12-bit reference clock dividing ratio set. correspond LSB, respectively.
Default
Reference clock dividing ratio
15-bit synthesizer dividing ratio set. correspond LSB, respectively.
2n-12)
synthesizer dividing ratio
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Data Description Setting CKO/PLLO dividing ratios Dividing Ratio 1/16 1/32 PLLO/CKO Oscillator Frequency 12.5 6.25 12.5 3.125 6.25 1.563 3.125 0.781 1.563 Default
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP Operating mode setting commands Address (A1, allows setting one-shot pulse polarity width, trigger edge, M66238 entire halt, charge pump halt, phase comparator UP/DOWN output, cutoff, CKO/PLLO switching, switching charge pump switching.
Data Description Setting trigger edge Synchronizes with Synchronizes with Synchronizes with Synchronizes with Description stopped when stopped when output when output when Default
When trigger occurs: spike sync clock eliminated. When trigger occurs: spike sync clock eliminated (disabled when Polarity one-shot pulse: Negative pulse Polarity one-shot pulse: Positive pulse Setting one-shot pulse width Description 2-cycle width 4-cycle width 8-cycle width 16-cycle width
CKO/PLLO pin: output CKO/PLLO pin: PLLO output Entire M66238: Operating state Entire M66238: Halt state VCO: Operating state VCO: Halt state Charge pump: Charge pump: pass filter: Operating state pass filter: Separated Normal use: output outside Phase comparator UP/DOWN output enable Normal test circuit Normal Charge pump test circuit Normal 15-bit counter test clock enable Normal Sync clock generator test clock enable Normal Sync clock generator test input enable Normal 12-bit counter test output enable Normal 15-bit counter test output enable Normal Sync clock generator trigger test output enable Normal Sync clock generator test output enable normal use:
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP Dummy trigger generating command internal status sync clock generator becomes unstable stable sync clock output (CKO) obtained after power turned after reset cleared after internal oscillator frequency set. obtain stable sync clock output, enter trigger signal from input after oscillator becomes stable, enter dummy trigger generating command from MCU. synthesizer oscillator frequency after cancellation reset depends default (See register configuration). command address (A1,
Data Description command must stored times continuously when dummy trigger generated. first time, dummy trigger generating command with second time, dummy trigger generating command with second setting becomes sync edge clock begins output from CKO. After first setting, halt state. normal use: Default
Operating Timing
Sync Clock Spike Non-removal Mode upon Occurrence Trigger Setting Trigger Edge when One-shot pulse start timing: One-shot pulse polarity: One-shot pulse width: output dividing ratio: leading edge after fall Negative pulse cycles division
example condition address (A1, data (D6, shown below. clock output synchronized PULSE one-shot pulse synchronized with rise CKO.
fvco Internal oscillator clock (TR)
(CKO) (CKO) SPIKE PULSE (PULSE) fout
(PULSE)
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP Setting Trigger Edge when One-shot pulse start timing: One-shot pulse polarity: One-shot pulse width: output dividing ratio: leading edge after rise (except rise spike which occurs when stopped). Negative pulse cycles division
example condition address (A1, data (D6, shown below. clock output synchronized PULSE one-shot pulse synchronized with rise CKO.
fvco Internal oscillator clock (TR)
(CKO) (CKO) SPIKE PULSE fout
(PULSE)
Sync Clock Spike Removal Mode upon Occurrence Trigger When address (A1, data (D6, with first rise after occurrence trigger output then stops. However, this mode available when trigger edge setting. wide that sync edge entered more after stops.
(TR)
more required (CKO) (CKOB) PULSE (PULSE)
CKOB
(PULSE)
Notes: more required (CKO, CKOB, PULSE) defined input clock width addition, value denotes internal delay, values definite unless temperature, Vcc, etc. changed, variations that time defined (sync accuracy: jitter).
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
CKO/PLLO Output Frequency Range
M66238 requires internal oscillator frequency MHz. Settings dividing ratio 12-bit divider dividing ratio 15-bit counter required order determine internal oscillator frequency. relation between settings internal oscillator frequency shown below.
Oscillator frequency fVCO
(MHz)
2n-12)
Note: Setting recommended consideration frequency accuracy characteristics output. Therefore, division ratio 12-bit divider division ratio 15-bit counter meet following conditions: fvco addition, PLLO CKO, setting division ratios sync/division circuit (synchronous clock generating area) 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow frequencies 0.78 accommodated.
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Input Timing
Register Setting
(CS-SCK) (SCK) (SIN-SCK) (SCK-SIN) (SCK) (SCK-CS) (CS)
Clock from Trigger Input One-shot Pulse Output
CKOB PULSE
Stop Clock from Trigger Input
CKOB
Trigger Input Width
(TR)
One-shot Pulse Width
PULSE (PULSE)
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Application Circuit Example
Digital power supply Programmable Interface 0.015 Analog Programmable Interface Analog power supply
M66238FP
Crystal oscillator
Digital
REJ03F0268-0200 Rev.2.00 2008 Page
M66238FP
Package Dimensions
32P2W-A
EIAJ Package Code SOP32-P-450-1.27 JEDEC Code Weight(g) 0.67 Lead Material Alloy
Plastic 32pin 450mil
Recommended Mount
Symbol
Detail
Detail
Dimension Millimeters 0.05 0.35 0.13 0.15 19.8 20.0 20.2 1.27 11.63 11.93 12.23 1.765 0.475 0.625 0.25 0.15 0.76 11.43 1.27
REJ03F0268-0200 Rev.2.00 2008 Page
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Standard Clock Generator with Frequency Synthesizer REJ03F0268-02

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