IDT7200L IDT7201LA IDT7202LA First-In/First-Out dual-port memory
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CMOS ASYNCHRONOUS FIFO 1,024
IDT7200L IDT7201LA IDT7202LA
First-In/First-Out dual-port memory organization (IDT7200) organization (IDT7201) 1,024 organization (IDT7202) power consumption Active: 770mW (max.) -Power-down: 2.75mW (max.) Ultra high speed-12ns access time Asynchronous simultaneous read write Fully expandable both word depth and/or width functionally compatible with 720X family Status Flags: Empty, Half-Full, Full Auto-retransmit capability High-performance CEMOStechnology Military product compliant MIL-STD-883, Class Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 5962-89536 listed this function Industrial temperature range (-40°C +85°C) available (plastic packages only)
DESCRIPTION:
IDT7200/7201/7202 dual-port memories that load empty data first-in/first-out basis. devices Full Empty flags prevent data overflow underflow expansion logic allow unlimited expansion capability both word size depth. reads writes internally sequential through ring pointers, with address information required load unload data. Data toggled devices through Write Read pins. devices utilize 9-bit wide data array allow control parity bits user's option. This feature especially useful data communications applications where necessary parity transmission/reception error checking. also features Retransmit (RT) capability that allows reset read pointer initial position when pulsed allow retransmission from beginning data. Half-Full Flag available single device mode width expansion modes. These FIFOs fabricated using IDT's high-speed CMOS technology. They designed those applications requiring asynchronous simultaneous read/writes multiprocessing rate buffer applications. Military grade product manufactured compliance with latest revision MILSTD-883, Class
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
WRITE CONTROL
WRITE POINTER
ARRAY 1,024
READ POINTER
READ CONTROL
THREESTATE BUFFERS DATA OUTPUTS
RESET LOGIC
FLAG LOGIC
XO/HF
FL/RT
logo trademark
EXPANSION LOGIC
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MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
SEPTEMBER 1997
DSC-2679/7
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
FL/RT
FL/RT XO/HF
INDEX
CONFIGURATIONS
XO/HF
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PLASTIC DIP(1) PLASTIC THIN CERDIP(1) THIN CERDIP SOIC CERPAK(1)
Reference Identifier P28-1 P28-2 D28-1 D28-3 SO28-3 E28-2
Order Code
LCC(1) PLCC
Reference Identifier L32- J32-1 VIEW
Order Code
VIEW
NOTE: 600-mil-wide (P28-1 D28-1), CERPACK available 7200.
ABSOLUTE MAXIMUM RATINGS
Symbol Rating VTERM Terminal Voltage with Respect TSTG Storage Temperature IOUT Output Current Com'l Ind'l -0.5 +7.0 Mil. Unit -0.5 +7.0
RECOMMENDED OPERATING CONDITIONS
Symbol VCCM VCCC
Parameter Military Supply Voltage Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input High Voltage Military Input Voltage Commercial Military Operating Temperature Commercial Operating Temperature Industrial Operating Temperature Military
Min.
Typ.
Max. Unit
+125
+155
NOTE: 2679 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliabilty.
VIH(1) VIL(2)
CAPACITANCE +25°C, MHz)
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Condition VOUT Max. Unit
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NOTE: This parameter sampled 100% tested.
NOTES: 2.6V input (commercial). 2.8V input (military). 1.5V undershoots allowed 10ns once cycle.
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS
(Commercial: 10%, +70°C; Industrial: 10%, -40°C +85°C; Military: 10%, -55°C +125°C)
IDT7200L IDT7201LA IDT7202LA Com'l Ind'l(1) Symbol
IDT7200L IDT7201LA IDT7202LA Military Min. Typ. Max. Unit
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Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic Voltage -2mA Output Logic Voltage Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current
Min.
Typ.
Max.
ILO(3) ICC1(4,5,6) ICC2(4,6,7) ICC3(L)
(4,6,7)
IDT7200L IDT7201LA IDT7202LA Commercial Symbol ILI(2) ILO(3) ICC1(4,5,6) ICC2(4,6,7) ICC3(L)(4,6,7) Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic Voltage -2mA Output Logic Voltage Active Power Supply Current Standby Current (R=W=RS=FL/RT=VIH) Power Down Current Min. Typ. Max.
IDT7200L IDT7201LA IDT7202LA Military Min. Typ. Max. Unit
NOTES: 2679 Industrial temperature range product speed grade available standard device. other speed grades available special order. Measurements with VCC. VIH, VOUT VCC. Tested with outputs open (IOUT RCLK WCLK toggle data inputs switch MHz. measurements made with outputs open. Inputs 0.2V 0.2V, except RCLK WCLK, which toggle MHz.
TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V 1.5V 1.5V Figure
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS(1)
(Commercial: 10%, +70°C; Industrial: 10%, -40°C +85°C; Military: 10%, -55°C +125°C)
Commercial 7200L12 7200L15 7201LA12 7201LA15 7202LA12 7202LA15 Symbol tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR tEFL tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXIR tXIS Parameter Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width(3) Read Pulse Data Z(4) Write Pulse High Data Z(4,5) Data Valid from Read Pulse High Read Pulse High Data High Write Cycle Time Write Pulse Width Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(3) Reset Set-up Time(4) Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width
Com'l Mil. Com'l Ind'l(2) 7200L20 7201LA20 7202LA20 33.3 7200L25 7201LA25 7202LA25 Min. 28.5
Military
Com'l
7200L30 7200L35 7201LA30 7201LA35 7202LA30 7202LA35 22.2
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Min. Max. Min. Max. Min. Max.
Max. Min. Max. Min. Max. Unit
Write Recovery Time
Retransmit Set-up Time(4) Retransmit Recovery Time Reset Empty Flag Retransmit Flags Valid Read Empty Flag Read High Full Flag High Read Pulse Width after High Write High Empty Flag High Write Full Flag Write Half-Full Flag Read High Half-Full Flag High Write Pulse Width after High Read/Write Read/Write High
tHFH,FFH Reset Half-Full Full Flag High
Pulse Width Recovery Time Set-up Time
NOTES: Timings referenced Test Conditions. Industrial temperature range available special order speed grades faster than 25ns.
Pulse widths less than minimum value allowed. Values guaranteed design, currently tested. Only applies read data flow-through mode.
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: 10%, +70°C; Industrial: 10%, -40°C +85°C; Military: 10%, -55°C +125°C)
Military 7200 7201LA40 7202LA40 Symbol tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR tEFL tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXIR tXIS Parameter Shift Frequency Read Cycle Time Access Time Read Recovery Time Read Pulse Width
Com'l Mil. 7200L50 7201LA50 7202LA50 Max. 7200L65 7201LA65 7202LA65 Min. Max. 12.5
Military(2) 7200L80 7201LA80 7202LA80 Min. Max. 7200L120 7201LA120 7202LA120 Min. Max. Unit
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Min.
Max. Min.
Read Pulse Data Data Valid from Read Pulse High
Write Pulse High Data Z(4, Read Pulse High Data High Write Cycle Time Write Pulse Width Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(3) Reset Set-up Time
Write Recovery Time
Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width
Retransmit Set-up Time(4) Retransmit Recovery Time Reset Empty Flag Retransmit Flags Valid Read Empty Flag Read High Full Flag High Read Pulse Width after High Write High Empty Flag High Write Full Flag Write Half-Full Flag Read High Half-Full Flag High Write Pulse Width after High Read/Write Read/Write High
tHFH,FFH Reset Half-Full Full Flag High
Pulse Width Recovery Time Set-up Time
NOTES: Timings referenced Test Conditions Speed grades available CERPACK Pulse widths less than minimum value allowed.
Values guaranteed design, currently tested. Only applies read data flow-through mode.
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
1.1K OUTPUT
30pF*
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equivalent circuit Figure Output Load Includes scope capacitances.
ongoing write operations. After Read Enable goes high, Data Outputs will return high impedance condition until next Read operation. When data been read from FIFO, Empty Flag (EF) will low, allowing "final" read cycle inhibiting further read operations with data outputs remaining high impedance state. Once valid write operation been accomplished, Empty Flag (EF) will high after tWEF valid Read then begin. When FIFO empty, internal read pointer blocked from external changes will affect FIFO when empty. FIRST LOAD/RETRANSMIT (FL/RT) This dual-purpose input. Depth Expansion Mode, this grounded indicate that first loaded (see Operating Modes). Single Device Mode, this acts restransmit input. Single Device Mode initiated grounding Expansion (XI). IDT7200/7201A/7202A made retransmit data when Retransmit Enable control (RT) input pulsed low. retransmit operation will internal read pointer first location will affect write pointer. Read Enable Write Enable must high state during retransmit. This feature useful when less than 256/ 512/1,024 writes performed between resets. retransmit feature compatible with Depth Expansion Mode will affect Half-Full Flag (HF), depending relative locations read write pointers. EXPANSION (XI) This input dual-purpose pin. Expansion (XI) grounded indicate operation single device mode. Expansion (XI) connected Expansion (XO) previous device Depth Expansion Daisy Chain Mode.
SIGNAL DESCRIPTIONS INPUTS:
DATA Data inputs 9-bit wide data.
Reset accomplished whenever Reset (RS) input taken state. During reset, both internal read write pointers first location. reset required after power before write operation take place. Both Read Enable Write Enable inputs must high state during window shown Figure (i.e., tRSS before rising edge should change until tRSR after rising edge Half-Full Flag (HF) will reset high after Reset (RS). WRITE ENABLE write cycle initiated falling edge this input Full Flag (FF) set. Data set-up hold times must adhered with respect rising edge Write Enable (W). Data stored array sequentially independently on-going read operation. After half memory filled falling edge next write operation, Half-Full Flag (HF) will will remain until difference between write pointer read pointer less than equal half total memory device. Half-Full Flag (HF) then reset rising edge read operation. prevent data overflow, Full Flag (FF) will low, inhibiting further write operations. Upon completion valid read operation, Full Flag (FF) will high after tRFF, allowing valid write begin. When FIFO full, internal write pointer blocked from external changes will affect FIFO when full. READ ENABLE read cycle initiated falling edge Read Enable provided Empty Flag (EF) set. data accessed First-In/First-Out basis, independent
CONTROLS: RESET (RS)
OUTPUTS:
FULL FLAG (FF) Full Flag (FF) will low, inhibiting further write operation, when write pointer location less than read pointer, indicating that device full. read pointer moved after Reset (RS), Full-Flag (FF) will after writes IDT7200, writes IDT7201A 1,024 writes IDT7202A. EMPTY FLAG (EF) Empty Flag (EF) will low, inhibiting further read operations, when read pointer equal write pointer, indicating that device empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This dual-purpose output. single device mode, when Expansion (XI) grounded, this output acts indication half-full memory. After half memory filled falling edge next write operation, Half-Full Flag (HF) will will remain until difference between write
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
pointer read pointer less than equal half total memory device. Half-Full Flag (HF) then reset using rising edge read operation. Depth Expansion Mode, Expansion (XI) connected Expansion (XO) previous device. This output acts signal next device Daisy Chain
providing pulse next device when previous device reaches last location memory. DATA OUTPUTS Data outputs 9-bit wide data. This data high impedance condition whenever Read high state.
NOTES: change status during Reset, flags will valid tRSC. around rising edge Figure Reset
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DATA VALID
DATA VALID
DATA VALID
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DATA VALID
Figure Asynchronous Write Read Operation
LAST WRITE
IGNORED WRITE
FIRST READ
ADDITIONAL READS
FIRST WRITE
Figure Full Flag From Last Write First Read
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
LAST READ
IGNORED READ
FIRST WRITE
ADDITIONAL WRITES
FIRST READ
DATA VALID
Figure Empty Flag From Last Read First Write
VALID
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Figure Retransmit
FLAG VALID
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Figure Minimum Timing Empty Flag Coincident Read Pulse
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Figure Minimum Timing Full Flag Coincident Write Pulse
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
HALF-FULL LESS MORE THAN HALF-FULL
Figure Half-Full Flag Timing
HALF-FULL LESS
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WRITE LAST PHYSICAL LOCATION
READ FROM LAST PHYSICAL LOCATION
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Figure Expansion
WRITE FIRST PHYSICAL LOCATION READ FROM FIRST PHYSICAL LOCATION
Figure Expansion
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OPERATING MODES:
Care must taken assure that appropriate flag monitored each system (i.e. monitored device where used; monitored device where used). additional information, refer Tech Note Operating FIFOs Full Empty Boundary Conditions Tech Note Designing with FIFOs. Single Device Mode single IDT7200/7201A/7202A used when application requirements 256/512/1,024 words less. These devices Single Device Configuration when Expansion (XI) control input grounded (see Figure 12). Depth Expansion IDT7200/7201A/7202A easily adapted applications when requirements greater than 256/512/ 1,024 words. Figure demonstrates Depth Expansion using three IDT7200/7201A/7202As. depth attained
adding additional IDT7200/7201A/7202As. These FIFOs operate Depth Expansion mode when following conditions met: first device must designated grounding First Load (FL) control input. other devices must have high state. Expansion (XO) each device must tied Expansion (XI) next device. Figure External logic needed generate composite Full Flag (FF) Empty Flag (EF). This requires ORing ORing (i.e. must generate correct composite EF). Figure Retransmit (RT) function Half-Full Flag (HF) available Depth Expansion Mode. additional information, refer Tech Note Cascading FIFOs FIFO Modules.
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
USAGE MODES:
Width Expansion Word width increased simply connecting corresponding input control signals multiple devices. Status flags (EF, detected from device. Figure demonstrates 18-bit word width using IDT7200/7201A/7202As. word width attained adding additional IDT7200/7201A/7202As (Figure 13). Bidirectional Operation Applications which require data buffering between systems (each system capable Read Write operations) achieved pairing IDT7200/7201A/7202As shown Figure Both Depth Expansion Width Expansion used this mode. Data Flow-Through types flow-through modes permitted, read flow-through write flow-through mode. read flowthrough mode (Figure 17), FIFO permits reading
single word after writing word data into empty FIFO. data enabled (tWEF after rising edge called first write edge, remains until line raised from low-to-high, after which would into three-state mode after tRHZ line would have pulse showing temporary deassertion then would asserted. write flow-through mode (Figure 18), FIFO permits writing single word data immediately after reading word data from full FIFO. line causes deasserted line being causes asserted again anticipation data word. rising edge word loaded FIFO. line must toggled when asserted write data FIFO increment write pointer. Compound Expansion expansion techniques described above applied together straightforward manner achieve large FIFO arrays (see Figure 15).
(HALF-FULL FLAG) WRITE DATA FULL FLAG (FF) RESET (RS)
(HF) READ 7200/ 7201A/ 7202A DATA EMPTY FLAG (EF) RETRANSMIT (RT)
EXPANSION (XI)
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Figure Block Diagram Single 1,024 FIFO
DATA WRITE FULL FLAG (FF) RESET (RS) 7200/ 7201A/ 7202A
7200/ 7201A/ 7202A
READ EMPTY FLAG (EF) RETRANSMIT (RT)
DATA
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Figure Block Diagram 1,024 FIFO Memory Used Width Expansion Mode
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
TABLE I-RESET RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs Mode Reset Retransmit Read/Write
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Unchanged Increment(1) Increment(1)
Outputs
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NOTE: Pointer will increment flag High.
TABLE II-RESET FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs Mode Reset First Device Reset Other Devices Read/Write
Internal Status Read Pointer Write Pointer Location Zero Location Zero Location Zero Location Zero
Outputs
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NOTE: connected previous device. Figure Expansion Input, Half-Full Flag Output
Reset Input, FL/RT First Load/Retransmit, Empty Flag Output, Flag Full Output,
7200/ 7201A/ 7202A
FULL
7200/ 7201A/ 7202A
EMPTY
7200/ 7201A/ 7202A
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Figure Block Diagram 1,536 3,072 FIFO Memory (Depth Expansion)
IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK
NOTES: depth expsansion block section Depth Expansion Figure Flag detection section Width Expansion Figure
IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK (N-8)
(N-8) (N-8) IDT7200/ IDT7201A/ IDT7202A DEPTH EXPANSION BLOCK (N-8)
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Figure Compound FIFO Expansion
7200/ 7201A/ 7201A 7202A
SYSTEM
SYSTEM
7200/ 7201A/ 7202A
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Figure Bidirectional FIFO Mode
DATA
DATA
Figure Read Data Flow-Through Mode
DATA
VALID
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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO 1,024
MILITARY, INDUSTRIAL COMMERCIAL TEMPERATURE RANGES
DATA DATA
DATA
VALID
DATA
VALID
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Figure Write Data Flow-Through Mode
ORDERING INFORMATION
XXXX Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C +70°C) Industrial (-40°C +85°C) Military (-55°C +125°C) Compliant MIL-STD-883, Class Plastic Plastic Thin CERDIP Thin CERDIP Plastic Leaded Chip Carrier PLCC SOIC Leadless Chip Carrier CERPACK P28-1 P28-2 D28-1 D28-3 J32-1 SO28-3 L32-1 E28-2 (7201 7202 Only) (7201 7202 Only)
(7201 7202 Only) (7201 7202 Only)
Commercial Only Commercial Only Commercial Industrial Military Only Commercial Only Military Only Military only-except package Power
Access Time Speed Nanoseconds
7200 7201 7202
9-Bit FIFO 9-Bit FIFO 1,024 9-Bit FIFO
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NOTES: Industrial temperature range available plastic packages special order speed grades faster than included 7201 7202 ordering part number.
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