0.18 Series with Embedded DPRAM ATU18 Description ATU18 seri

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0.18 Series with Embedded DPRAM ATU18 Description ATU18 seri

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High Performance Family Suitable Latest CPLDs FPGAs conversion Very effective associated Physical synthesis/optimization Flow From Gates 1000K Gates Supported From 55Kbit 847Kbit DPRAM Compatible with Xilinx Altera Latest FPGA's Pin-count: Over pins 1.8V 0.15V core; 1.8V, 2.5V, 3.3V Periphery Pin-out Matched Full Range Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, Available Commercial, Industrial Military Grades 0.18 Drawn CMOS, Metal Layers Library Optimised best Synthesis, Place route Testability Generation (ATPG) High system clock Skew Control 250Mhz system clock, 400Mhz local clock Power Reset, PLL, Multiplier Standard I/Os LVCMOS, LVTTL, GTL, HSTL, LVPECL, LVDS Interfaces High Noise Immunity Thick Oxide periphery Allowing Interface with 2.5V 3.3V Environments
0.18 Series with Embedded DPRAM ATU18
Description
ATU18 series ULCs fully suited conversion latest CPLDs FPGAs. supports within 55Kbits 847Kbits DPRAM 45Kgates 1000 Kgates. Typically, size smaller than equivalent FPGA. Metal level customisation allows DPRAM blocks compatibility with Xilinx® Altera® blocks. Devices implemented high-performance 0.18 CMOS technology improve design frequency reach 250Mhz typical application local clock 400Mhz. architecture ATU18 series dedicated efficient conversion latest CPLD FPGA device types with higher count. compact cell large number available gates allow implementation memories compatible with FPGA RAM, well JTAG boundary-scan scan-path testing. Conversion ATU18 series provides significant reduction operating power when compared original FPGA. ATU18 series very standby consumption, less than 0.145 nA/gate typically commercial temperature. Operating consumption strict function clock frequency, which typically results significant power reduction depending device being compared. NAND2 cell dynamic power consumption 0.124uW/MHz 1.8V.
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ATU18 series provide several options output buffers, including variety drive levels 24mA. Schmitt trigger inputs also available. number techniques used improve noise immunity reduce emissions, including several independent power supply buses internal decoupling isolation. ATU18 series designed allow conversion high performance 1.8V devices. Support mixed supply conversions also possible, allowing optimal trade-offs between speed power consumption.
Array Organization
Table Matrices
Part Number ATU18_680 ATU18_600 ATU18_484 ATU18_432 ATU18_352 ATU18_304 ATU18_256 ATU18_160 Pads Gates 1000K 720K 486K 330K 276K 171K 111K DPRAM bits 847K 700K 460K 350K 221K 183K 147K
Architecture
ATMEL 0.18um matrices allow conversions designs being developed Altera/ApexApexTMII Stratix® Cycloneor Xilinx/VirtexTM, Spartanand CoolRunnerfamilies. Each matrix contains configurable memory DPRAM blocks, PLLs (from Power-on-Reset. also integrate 1.8V regulator from 3.3V supply available 1.8V board. associated Physical synthesis/optimization flow contributes achieve high speed designs, even improving drastically application frequency power consumption.
ATU18
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ATU18
Figure Atmel 0.18um matrix supply rings configurable DPRAMs core logic area PLLs configurable pads
DPRAM Description
flexibility, embedded DPRAMs blocks, using ATMEL memory configuration tool, configured customization Metal levels, order match behaviour format Xilinx Altera memories.
Figure ATMEL Memory Configuration Tool
test production, bist systematically inserted, without degrading performances. memories will then automatically tested provide high reliability.
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Table Dual Port Mode Configurations
Memory area 576k bits Port Port 64kx9 64kx9 64kx9 32kx18 64kx9 16kx36 64kx9 8Kx72 16kx1 16kx1 16kx1 8kx2 Memory Area bits 16kx1 4kx4 16kx1 2kx9 16kx1 1kx8 16kx1 512x36
Port Port
32kx18 32kx18
32kx18 16kx36
32kx18 8kx72
8kx2 8kx2
8kx2 4kx4
8kx2 2kx9
8kx2 1kx18
8kx2 512x36
Port Port
16kx36 16kx36
16kx36 8kx72
4kx4 4kx4
4kx4 2kx9
4kx4 1kx18
4kx4 512x36
Port Port
8kx72 8kx72
2kx9 2kx9
2kx9 1kx18
2kx9 512x36
Port Port
4Kx144 4Kx144
1kx18 1kx18
1kx18 512x36
Port Port
512x36 512x36
ATU18
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ATU18
Buffer Interfacing
Flexibility buffers periphery configured input, output, bi-directional oscillator. power rings modified allow clusterization (i.e. cluster 1.8V cluster 3.3V). When core supply differs from periphery supply, level shifters available buffers, example following conditions: 3.3V 1.8V core, 2.5V I/O->1.8V core.
Each LVTTL, LVCMOS, Schmitt Trigger input programmed with without pull pull down resistor keeper. Standard supported given table Fast Output Buffer able drive 24mA 3.3V according chosen option. (higher drive achievable using adjacent pads). Table Standard Supported
Standard LVTTL LVCMOS PCI33 PCI66 GTL+ HSTL III, SSTL2 SSTL3 LVPECL LVDS Comment 3.3V 1.8V/2.5V/3.3V 3.3V 3.3V 3.3V 3.3V input only input only input only input only 3.3V
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Description
ATMEL available large range frequencies. internal filter external component necessary. Programming customization level allows choose between four ranges frequency shown table below:
FreqSelect1 FreqSlect0 Frequency 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
Different outputs also available, ensure wide variety use. drawing below shows PLL.
VccPLL
FREQIN DIVOUT ENPLL FREQSELECT(1:0) ICP(1:0) SYNC VCOIN ENVCOIN
OUT0 OUT90 OUT180 OUT270
OUTX0 OUTX180
OUT1 OUT2
VssPLL
Table Description
Name FREQIN DIVOUT FREQSELECT(1:0) SC2,SC1 ICP(1:0) TYPE digital digital digital digital digital Function Reference input frequency Feedback input frequency frequency range select internal filter value select Charge pump current select
ATU18
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ATU18
Table Description
Name SR1, SYNC VCOIN ENVCOIN OUT0 OUT90 OUT180 TYPE digital digital analog digital digital digital digital Function internal filter value select synchronization mode select external input external input select degree phase shift freq divided degree phase shift freq divided degree phase shift freq divided degree phase shift freq divided degree phase shift freq divided degree phase shift freq divided output delayed output from OUT1 lock output 1.8V
OUT270 OUTX0 OUTX180 OUT1 OUT2 VCCPLL VSSPLL
digital digital digital digital digital digital power power
FREQUENCY 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
OUT1,OUT2 66-90Mhz 90-160Mhz 155-300Mhz 280-500Mhz
OUTX0, OUTX180 33-45Mhz 45-80Mhz 77.5-150Mhz 140-250Mhz
OUT[0,90,180,270] 16.5-22.5Mhz 22.5-40Mhz 38-75Mhz 70-125Mhz
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Applications
ATMEL configurable support applications Clock tree delay reduction Zero delay buffer Phase shift Frequency synthesis
Clock Tree Delay Reduction
Typically, clock tree synthesis able build very performant clock tree (for example: 0.15ns skew clock tree connected 25000 Flipflops). that, however, clock tree latency increased during clock tree insertion. satisfy propagation delay, used reduce even remove clock tree delay.
Frequency Synthesis
adding dividers input clock feedback clock, used multiply input frequency factor determined user, illustrated below: Figure Frequency Synthesis CLKin
freqin Phase divout comp
Charge Pump
outx0
CLKout
example, with 32Mhz input clock, generate frequency clock output outx0, necessary input clock divider feed-back clock divider
ATU18
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ATU18
Atmel Flow
With 0.18um technology, ATMEL introduced Physical synthesis optimize design speed. Physical synthesis takes into account placement routing cells, optimization incremental mode done full design only partially. result that ATMEL faster chips, using same code. Less iterations necessary timings target quickly reached.
Customer Pinout
Customer Code SYNTHESIS Timing Power ATMEL NETLIST SCAN, JTAG, BIST NETLIST Layout
Customer Timing constraints
ATMEL Bonding diagram
Formal Proof
PHYSICAL SYNTHESIS
Placement
Clock Tree synthesis
Route
Post layout Simulations, Timing power Analysis
TAPE
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ATU18 Packages
following packages supported:
ATU18_680 TQFP TQFP PQFP PQFP PQFP PQFP PQFP FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA FLBGA 1020 FLBGA 1156 FLBGA 1508 FLBGA SBGA SBGA SBGA ATU18_600 ATU18_484 ATU18_432 ATU18_352 ATU18_304 ATU18_256 ATU18_160
gray cells supported package configuration Remark: Other package package/matrix configurations supported upon request
ATU18
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ATU18
Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature Commercial.0° 70°C Industrial.-40° 85°C Military.-55° 125°C Supply Core Voltage (VDD).1.95 Supply Periphery Voltage (VCC).3.6V 3.3V Tolerant/Compliant.Vcc +0.3V pullup resistor.100Kohms pulldown resistor.100Kohms Output buffer drive range.3 leakage current Temp=25C.0.145nA/gate NAND2 dynamic power consumption.0.124uW/MHz 1.8V Storage Temperature.-65° 150°C *NOTICE: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability. This value based maximum allowable temperature thermal resistance package.
Specifications
Operating Modes Clock tree reduction Zero delay buffer Phase shift Frequency synthesis
range .66Mhz 500Mhz OUT1, OUT2 output range.66Mhz OUTX0, OUTX180 ouput range.33Mhz OUT0,90,180,270 output range.16.5Mhz 125Mhz VDDPLL supply .1.8V
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0.18 Series with Embedded DPRAM ATU18 Description ATU18 seri

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