CMOS SRAM (Common I/O) Features compatible with AS7C256 Industria

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CMOS SRAM (Common I/O) Features compatible with AS7C256 Industria

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AS7C256A
CMOS SRAM (Common I/O) Features
compatible with AS7C256 Industrial commercial temperature options Organization: 32,768 words bits High speed 10/12/15/20 address access time output enable access time Very power consumption: ACTIVE 412.5 Very power consumption: STANDBY CMOS Easy memory expansion with inputs TTL-compatible, three-state 28-pin JEDEC standard packages 13.4 TSOP protection 2000 volts Latch-up current 2.0V Data retention
Logic block diagram
Input buffer
arrangement
28-pin TSOP 28-pin (300 mil)
I/O7 decoder Sense Array (262,144)
I/O0
AS7C256A
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Column decoder
Control circuit
I/O0 I/O1 I/O2
I/O7 I/O6 I/O5 I/O4 I/O3
Selection guide
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current Unit
9/24/04; v.1.2
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS7C256A
AS7C256A
Functional description
AS7C256A 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized 32,768 words bits. designed memory applications requiring fast data access voltage, including PentiumTM, PowerPCTM, portable computing. Alliance's advanced circuit design process techniques permit 5.0V operation without sacrificing performance operating margins. device enters standby mode when high. CMOS standby mode consumes Normal operation offers power reduction after initial access, resulting significant power savings during idle, suspend, stretch mode. Equal address access cycle times (tAA, tRC, tWC) 10/12/15/20 with output enable access times (tOE) ideal high-performance applications. chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. write cycle accomplished asserting chip enable (CE) write enable (WE) LOW. Data input pins I/O0-I/O7 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting chip enable (CE) output enable (OE) LOW, with write enable (WE) high. chip drives pins with data word referenced input address. When chip enable output enable high, write enable low, output drivers stay high-impedance mode. chip inputs outputs TTL-compatible. Operation from single ±0.5V supply. AS7C256A packaged high volume industry standard packages.
Absolute maximum ratings
Parameter Voltage relative Voltage relative Power dissipation Storage temperature (plastic) Ambient temperature with applied current into outputs (low) Symbol Tstg Tbias IOUT -0.5 -0.5 +7.0 +150 +125 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
High High DOUT Data Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: Don't care, Low, High
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Recommended operating conditions
Parameter Supply voltage Input voltage Ambient operating temperature commercial industrial Symbol VIH** VIL* -0.5 Typical VCC+0.5 Unit
-1.0V pulse width less than 5ns. 2.0V pulse width less than 5ns.
operating characteristics (over operating range)1
Parameter Input leakage current |ILI| Test conditions Max, Unit Notes
Output leakage Max, |ILO| current VOUT Operating power supply current Standby power supply current Max, fMax, IOUT Max, fMax
Max, VCC-0.2V ISB1 0.2V VCC-0.2V,
Output voltage
Capacitance 1MHz, room temperature, NOMINAL)4
Parameter Input capacitance capacitance Symbol CI/O Signals Test conditions Vout Unit
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Read cycle (over operating range)2,8
Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change output HIGH output high output HIGH output high Power time Power down time Symbol tACE tCLZ tCHZ tOLZ tOHZ Unit Notes
switching waveforms
Rising input Falling input Undefined output/don't care
Read waveform (address controlled)2,5,6,8
Address Dout Data valid
Read waveform controlled)2,5,7,8
tRC1 tOLZ Dout tCLZ Supply current tACE Data valid tOHZ tCHZ
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Write cycle (over operating range)9
Parameter Write cycle time Chip enable write Address setup write Address setup time Write pulse width Write recovery time Address hold from write Data valid write Data hold time Write enable output high Output active from write Symbol Unit Notes
Write waveform controlled)9
Address Dout Data valid
Write waveform controlled)9
Address Data valid
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
test conditions
Output load: Figure Input pulse level: Figure Input rise fall times: Figure Input output timing reference levels: 1.5V.
+5.0V Dout Dout Thevenin equivalent
+1.72V
Figure Input pulse
Figure Output load
Notes
During power-up, pull-up resistor required meet specification. test conditions, Test Conditions, Figures These parameters specified with 5pF, Figures Transition measured ±500mV from steady-state voltage. This parameter guaranteed, tested. High read cycle. read cycle. Address valid prior coincident with transition Low. read cycle timings referenced from last valid address first transitioning address. write cycle timings referenced from last valid address first transitioning address. C=30pF, except High parameters, where C=5pF.
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Package diagrams 28-pin
28-pin inches
0.128 0.148 0.026 0.095 0.105 0.026 0.032 0.016 0.020 0.007 0.010 0.720 0.730 0.255 0.275 0.295 0.305 0.330 0.340 0.050
Seating Plane
28-pin TSOP1
28-pin TSOP1
1.00 1.20 0.05 0.15 0.91 1.05 0.17 0.27 0.10 0.20 11.70 11.90 0.55 nominal 7.90 8.10 13.20 13.60 0.50 0.70
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Ordering information
Package Access time Plastic SOJ, TSOP 8x13.4mm
Temperature Commercial Industrial Commercial Industrial
AS7C256A-10JC AS7C256A-10JI AS7C256A-10TC AS7C256A-10TI
AS7C256A-12JC AS7C256A-12JI AS7C256A-12TC AS7C256A-12TI
AS7C256A-15JC AS7C256A-15JI AS7C256A-15TC AS7C256A-15TI
AS7C256A-20JC AS7C256A-20JI AS7C256A-20TC AS7C256A-20TI
Note: suffix `N'to above part number lead free parts. (Ex. AS7C256A-10JIN)
Part numbering system
AS7C 256A
Packages: SRAM prefix Device number Access time TSOP 8x13.4mm
Temperature range:
Lead Free Part
-40C
9/24/04; v.1.2
Alliance Semiconductor
AS7C256A
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, 95054 Tel: 4900 Fax: 4999 www.alsc.com
Copyright Alliance Semiconductor Rights Reserved Part Number: AS7C256A Document Version: v.1.2
Copyright 2003 Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights; mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such lifesupporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

CMOS SRAM (Common I/O) Features compatible with AS7C256 Industria

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