State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Diss
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs 32-mA IOH, 64-mA Package Options Include Plastic Small-Outline (DW) Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs
SN54ABT533 PACKAGE SN74ABT533 PACKAGE (TOP VIEW)
description
ABT533 8-bit transparent D-type latches with 3-state outputs designed specifically driving highly capacitive relatively lowimpedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. When latch-enable (LE) input high, outputs follow complements data inputs. When taken low, outputs latched inverse levels inputs. ABT533 provides inverted data outputs.
SN54ABT533 PACKAGE (TOP VIEW)
buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. Previously stored data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN74ABT533 available TI's shrink small-outline package (DB), which provides same count functionality standard small-outline packages less than half printed-circuit-board area. SN54ABT533 characterized operation over full military temperature range 55°C 125°C. SN74ABT533 characterized operation from 40°C 85°C.
EPIC-B trademark Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 1994, Texas Instruments Incorporated
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic symbol
logic diagram (positive logic)
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Voltage range applied output high state power-off state, Current into output state, SN54ABT533 SN74ABT533 Input clamp current, Output clamp current, Maximum power dissipation 55°C still air) (see Note package package package Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero. more information, refer Package Thermal Considerations application note 1994 Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note
SN54ABT533 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate SN74ABT533 UNIT
Operating free-air temperature NOTE Unused floating inputs must held high low.
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high input Other inputs Outputs Outputs disabled Outputs enabled Outputs disabled Control inputs Outputs high -140 0.55 0.55* ±150 -180 -180 0.55 0.55 ±150 -180 25°C -1.2 SN54ABT533 -1.2 SN74ABT533 -1.2 UNIT
products compliant MIL-STD-883, Class this parameter does apply. typical values This data sheet limit vary among suppliers. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure1)
25°C Pulse duration, high Setup time, data before Hold time, data after High High SN54ABT533 SN74ABT533 UNIT
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABT533 SN74ABT533 UNIT
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SN54ABT533, SN74ABT533 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT OUTPUTS Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP HOLD TIMES Data Input
Input (see Note tPLH Output
tPHL tPHL tPLH
Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH
tPLZ tPHZ
Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device 5962-9584301Q2A 5962-9584301QRA 5962-9584301QSA SN74ABT533DBLE SN74ABT533DW SN74ABT533DWR SN74ABT533N SNJ54ABT533FK SNJ54ABT533J SNJ54ABT533W
Status ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE
Package Type LCCC CDIP SSOP SOIC SOIC PDIP LCCC CDIP
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call Call Call Call Call Call Call
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Call Call Call Call Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MLCC006B OCTOBER 1996
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
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MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
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