SiI151 uses PanelLink Digital technology support displays ranging from

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PanelLink® Digital Receiver
SiI151 uses PanelLink Digital technology support displays ranging from SXGA (25-112 MHz) which ideal desktop specialty applications. SiI151 receiver supports true color panels bit/pixel, 16.7M colors) pixels/clock mode, also features inter-pair skew tolerance full input clock cycle. addition, receiver data output time staggered reduce ground bounce which affects EMI. Since PanelLink products designed scaleable CMOS architecture support future performance requirements while maintaining same logical interface, system designers assured that interface will fixed through number technology performance generations. PanelLink Digital technology simplifies design resolving many system level issues associated with high-speed digital design, providing system designer with digital interface solution that quicker market lower cost.
Features
Scaleable Bandwidth: 25-112 (VGA SXGA) Power: 3.3V core operation power-down mode High Skew Tolerance: full input clock cycle (9ns MHz) Time staggered data output reduced ground bounce Sync Detect: Plug Display "Hot Plugging" Cable Distance Support: over with twisted-pair, fiber-optics ready Compliant with (DVI backwards compatible with VESA® DFP)
SiI151 Diagram
OUTPUT CLOCK
Functional Block Diagram
CONTROLS HSYNC VSYNC OGND
OVCC CTL3 CTL2 CTL1 QE23
EVEN 8-bits OGND OVCC QE22 QE21 QE20 QE19 QE18 QE17 QE16 QE15 QE14
PIXS OCK_INV EXT_RES Termination Control DATA RX2+ RX2RX1+ RX1RX0+ RX0RXC+ Data Recovery Data Recovery Data Recovery SYNC2 SYNC2 CTL3 CTL2 Channel SYNC SYNC1 DATA Decoder CTL1 DATA VSYNC SYNC0 SYNC0 HSYNC Panel Interface Logic QE[23:0] QO[23:0] ODCK HSYNC VSYNC SCDT CTL1 CTL2 CTL3
ODCK
8-bits BLUE
OVCC OGND QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO21 QO22
QE13 QE12 QE11 QE10 OGND OVCC SCDT
EVEN 8-bits GREEN
SYNC1
8-bits GREEN
EVEN 8-bits BLUE
RXCPDO STAG_OUT
SiI151
100-Pin TQFP
(Top View)
STAG_OUT PIXS
8-bits
DIFFERNTIAL SIGNAL
RESERVED
OCK_INV
EXT_RES
CONFIG. PINS
AGND
AGND
AGND
AGND
AGND
OGND
OVCC
AVCC
AVCC
AVCC
AVCC
PGND
RXC+
RXC-
RX2-
RX1-
RX0-
PVCC
RX2+
RX1+
RX0+
QO23
MANAGEMENT
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Absolute Maximum Conditions
SiI151
SiI/DS-0007-E
Note: Permanent device damage occur absolute maximum conditions exceeded. Functional operation should restricted conditions described under Normal Operating Conditions. Symbol Parameter Units Supply Voltage 3.3V -0.3 Input Voltage -0.3 VCC+ Output Voltage -0.3 VCC+ Ambient Temperature (with power applied) TSTG Storage Temperature Package Power Dissipation
Normal Operating Conditions
Symbol Parameter Supply Voltage VCCN Supply Voltage Noise Ambient Temperature (with power applied) Note: Guaranteed design. 3.00 Units mVP-P
Digital Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage VCINL Input Clamp Voltage -18mA VCIPL Input Clamp Voltage 18mA VCONL Output Clamp Voltage -18mA VCOPL Output Clamp Voltage 18mA Output Leakage Current High Impedance Note: Guaranteed design. -0.8 IVCC -0.8 OVCC Units
Specifications
Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions IOHD Output High Drive VOUT VOH; Data Controls IOLD Output Drive VOUT VOL; Data Controls IOHC ODCK High Drive VOUT VOH; IOLC ODCK Drive VOUT VOL; Differential Input Voltage Single Ended Amplitude Power-down Current ICCR Receiver Supply Current CLOAD= 10pF DCLK=112MHz, 1-pixel/clock mode REXT_SWING Typical Pattern CLOAD 10pF REXT_SWING Worse Case Pattern 10.4 2.75 1000 Units
DCLK=112MHz, 1-pixel/clock mode Note:
Guaranteed design. transmitter must power-down mode, powered off, disconnected current under this maximum. Typical Pattern contains gray scale area, checkerboard area, text. Black white checkerboard pattern, each checker pixel wide.
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Specifications
SiI151
SiI/DS-0007-E
Under normal operating conditions unless otherwise specified. drive strength values, when ST=0, given below. Symbol Parameter Conditions Units TDPS Intra-Pair Differential Input Skew Pixel Clock TCCS Channel Channel Differential Input Skew Pixel Clock TIJIT Worst Case Differential Input Clock Jitter tolerance MHz, Pixel Clock MHz, Pixel Clock DLHT Low-to-High Transition Time 10pF; Data Controls 5pF; ODCK 10pF; 2.75 5pF; DHLT High-to-Low Transition Time 10pF; Data Controls 5pF; ODCK 10pF; 5pF; TSOF Data/Control Setup Time ODCK falling edge (OCK_INV 10pF; 65MHz, 1-pixel/clock, PIXS 5pF; 56MHz, 2-pixel/clock, PIXS 10pF; 5pF; THOF Data/Control Hold Time ODCK falling edge (OCK_INV 10pF; 65MHz, 1-pixel/clock, PIXS 5pF; 56MHz, 2-pixel/clock, PIXS 10pF; 5pF; RCIP ODCK Cycle Time (1-pixels/clock) FCIP ODCK Frequency (1-pixel/clock) RCIP ODCK Cycle Time (2-pixels/clock) 17.8 FCIP ODCK Frequency (2-pixel/clock) RCIH ODCK High Time 65MHz, 1-pixel/clock, PIXS 10pF; 5pF; 56MHz, 1-pixel/clock, PIXS 10pF; 5pF; RCIL ODCK Time 65MHz, 1-pixel/clock, PIXS 10pF; 5pF; 56MHz, 1-pixel/clock, PIXS 10pF; 5pF; TPDL Delay from high impedance outputs THSC Link disabled inactive) SCDT Link disabled power down) SCDT TFSC Link enabled active) SCDT high edges ODCK high even data output 0.25 RCIP Notes: Guaranteed design. Jitter defined Specification, Section Jitter Specification. Jitter measured with Clock Recovery Unit Specification, Section Electrical Measurement Procedures. setup hold timing data controls relative ODCK rising edge (OCK_INV=1) design same falling edge timing. Output clock duty cycle independent differential input clock duty cycle IDCK duty cycle. Measured when transmitter powered down (see SiI/AN-0005 "PanelLink Basic Design/Application Guide," Section 2.4).
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Timing Diagrams
SiI151
SiI/DS-0007-E
SiI151 10pF DLHT
DHLT
Figure Digital Output Transition Times
RCIP RCIH
RCIL
Figure Receiver Clock Cycle/High/Low Times
VDIFF=0V TCCS
Figure Channel-to-Channel Skew Timing
VDIFF=0V
Output Timing
ODCK TSOF QE[23:0]/QO[23:0], HSYNC, VSYNC, CTL[3:1] THOF
Figure Output Data, Control Signals Setup/Hold Times ODCK Falling Edge
QE[23:0]/QO[23:0], VSYNC,HSYNC, CTL[3:1],PLLCK
TPDL
Figure Output Signals Disabled Timing from Active
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Output Timing (continued)
SiI151
SiI/DS-0007-E
THSC
SCDT
TFSC
SCDT
Figure SCDT Timing from Inactive/Active
Internal ODCK
ODCK
QE[23:0]
FIRST DATA
THIRD DATA
QO[23:0]
SECOND DATA
FOURTH DATA
Figure 2-Pixels/Clock Staggered Output Timing Diagram
Output Description
Name QE23QE0 SiI151 Diagram Type Description Output Even Data[23:0] corresponds 24-bit pixel data 1-pixel/clock input mode first 24-bit pixel data 2-pixels/clock mode. Output data synchronized with output data clock (ODCK). Refer DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0008-A) which tabulates relationship between input data transmitter output data from receiver. level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. Output Data[23:0] corresponds second 24-bit pixel data 2-pixels/clock mode. During 1-pixel/clock mode, these outputs driven low. Output data synchronized with output data clock (ODCK). Refer DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0008-A) which tabulates relationship between input data transmitter output data from receiver. level will output drivers into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. Output Data Clock. level will output driver into high impedance (tri-state) mode. weak internal pull-down device brings output ground. Output Data Enable. This signal qualifies active data area. level will output driver into high impedance (tri-state) mode. weak internal pull-down device brings output ground. Horizontal Sync input control signal. Vertical Sync input control signal. General output control signal This output powered down PDO. General output control signal General output control signal level will output drivers (except CTL1 PDO) into high impedance (tri-state) mode. weak internal pull-down device brings each output ground.
QO23QO0
SiI151 Diagram
ODCK HSYNC VSYNC CTL1 CTL2 CTL3
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Configuration Description
Name OCK_INV Type
SiI151
SiI/DS-0007-E
PIXS
STAG_OUT
Description ODCK Polarity. level selects normal ODCK output. high level (3.3V) selects inverted ODCK output. other outputs signals affected this pin. They will maintain same timing matter setting OCK_INV pin. Pixel Select. level indicates pixel 24-bits) clock mode using QE[23:0]. high level (3.3V) indicates pixels 48-bits) clock mode using QE[23:0] first pixel QO[23:0] second pixel. Output Data Format. This controls clock output format. level indicates that ODCK runs continuously panel support. high level indicates that ODCK stopped (LOW) when DSTN panel support. Refer and/or DSTN Signal Mapping application notes (SiI/AN-0007-A SiI/AN-0008-A) table DSTN panel support. high level selects normal simultaneous outputs even data lines. level selects staggered output drive. This function only available 2-pixels clock mode. Output Drive. high level selects HIGH output drive strength. level selects output drive strength.
Power Management Description
Name SCDT Type Description Sync Detect. high level outputted when actively toggling indicating that link alive. level outputted when inactive, indicating link down. connected power down outputs when detected. SCDT output itself, however, remains active mode times. Output Driver Power Down (active low). high level indicates normal operation. level puts output drivers only (except SCDT CTL1) into high impedance (tri-state) mode. weak internal pull-down device brings each output ground. sub-set description. chip power-down mode with this pin. There internal pull-up resistor that defaults chip normal operation left unconnected. SCDT CTL1 tri-stated this pin. Power Down (active low). high level (3.3V) indicates normal operation level indicates power down mode. During power down mode, output buffers disabled brought low, analog logic powered down, inputs disabled.
Differential Signal Data Description
Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCEXT_RES Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Voltage Differential Signal input data pairs.
TMDS Voltage Differential Signal input data pairs. Impedance Matching Control. Resistor value should times characteristic impedance cable. common case transmission line, external resistor must connected between AVCC this pin.
Reserved Description
Name RESERVED Type Description Must tied high normal operation.
Power Ground Description
Name OVCC OGND AVCC AGND PVCC PGND 6,38,67 5,39,68 18,29,43,57,78 19,28,45,58,76 82,84,88,95 79,83,87,89,92 Type Power Ground Power Ground Power Ground Power Ground Description Digital Core VCC, must 3.3V. Digital Core GND. Output VCC, must 3.3V. Output GND. Analog must 3.3V. Analog GND. Analog must 3.3V. Analog GND.
Application Information
obtain most updated Application Notes other useful information your design application, please visit Silicon Image site www.siimage.com, contact your local Silicon Image sales office.
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Package Dimensions
100-pin TQFP Package Dimensions
Lead Length 1.00mm
SiI151
SiI/DS-0007-E
Lead Width 0.20mm
100-pin Plastic TQFP
Lead Pitch 0.50mm
Body Size 14.00mm
Device Date Code Rev.
SiINNN LNNNNN.NLLL XXYY X.XX
Package Height 1.20mm max.
Clearance 0.15mm max. 12.00mm Body Size 14.00mm Footprint 16.00mm
Body Thickness 1.05 max.
Copyright Notice
This manual copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc.
Trademark Acknowledgment
PanelLink PanelLink Digital Image Logo registered trademarks Silicon Image, Inc. Silicon Image, Silicon Image Logo, TMDS trademarks Silicon Image, Inc. VESA registered trademark Video Electronics Standards Association. other trademarks property their respective holders.
Disclaimer
This document provides technical information user. Silicon Image, Inc. reserves right modify information this document necessary. customer should make sure that they have most recent data sheet version. Silicon Image, Inc. holds responsibility errors that appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights.
Ordering Information
Part Number: SiI151CT100 1999 Silicon Image, Inc. 7/99 /DS-0007-E
Silicon Image, Inc. 10131 Bubb Road Cupertino, 95014
Tel: 408-873-3111 Fax: 408-873-0446 E-Mail: salessupport@siimage.com Web: www.siimage.com www.panellink.com
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Footprint 16.00mm
12.00mm

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