Flextronics Semiconductor's 0.13µ Standard Cell product suite offer de
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0.13µ Standard Cell
Flextronics Semiconductor's 0.13µ Standard Cell product suite offer designers best high-volume solution 3.3V performance, power, system cost. Applications benefiting from these features telecom, networking, portable datacom, consumer applications. product suite well equipped design teams intend migrate from advanced FPGA full system chip ASIC well system architects need prototype with ASIC. Production "all about results" utilizing Flextronics manufacturing supply chain muscle execute cycle-time cost performance.
Description
Deep sub-micron CMOS silicon utilizing 0.09µ effective gate length capable operation logic gates. power volt core operation with 0.01 µW/gate/MHz power dissipation. Dense, fast SRAM, Multi-port Register File compilers instance options 1Mbit. High Density fully diffused compiler 1Mbit. noise library designed minimum size performance utilizing staggered, in-line, flip-chip configurations. Complete sets tested 4000 volts latchup. Features Standard Cells High Performance Logic Cells Functions Application Specific 550+ cell engineered optimum synthesis high routability. 400+ high speed cells optimized performance applications. 400+ CMOS/TTL functions with multiple drive strengths with built level shifters. PCI, PCI-X, SSTL, SSTL_2, HSTL, USB, LVDS Clock driver, crystal oscillator, analog input, power, ground, spacer cells compatibility. Single port SRAM compiler high density, high performance solution embedded applications. transistor borderless cells achieve reduced area while maintaining tooling (mask) cost. compilier maintains multi-bank architecture with capacity Mbit. High density dual port SRAM compiler offers high performance solution with highest density embedded memory applications. Eight transistor bordered cells achieve minimum area while maintaining tooling (mask) cost. compiler maintains multi-bank architecture with capacity Kbit. FSC13_021202 Core Voltage Voltage Poly/Metal Density Power Dissipation
Process operation 1P8M (220K gates/mm2 0.01 µW/gate/MHz
SRAM
SRAM
CMOS 0.13µ Data Sheet
Features (continued) SRAM Register compiled high performance port memory solution embedded applications. Best solution register files, buffer memories, fall-through FIFO, palette RAM, RAM. Capacity compile very wide words bits address matching virtual address. overhead decode-logic sense amplifiers minimize required area. Read Only Memory compiler high density, fully diffused solution targeted embedded applications that require program store. cells optimized offer very high density power. Configurations Mbit available. Metal programmable versions also available custom basis. Compiler based technology that allows system designers choose center frequency, duty cycle, create customized PLL. Fully modular embedded ring with area overhead core eliminates manual wiring analog power supply additional band-gaps external components. Sophisticated frequency synthesizer targeted applications such pixel (dot clock) generation video master non-integer clock multiplication high-speed networking application. Cascaded architecture precision phase jitter stability. Fully modular embedded ring with area overhead core eliminates manual wiring analog power supply additional band-gaps external components.
Frequency Synthesizer
Design Support views Verilog views with best case worse case timing power data VHDL views with best case worse case timing power data Synopsys views with best case worse case timing power data
design kits include broad selection embedded semiconductor intellectual property components including standard cell logic, standard I/O, specialty interfaces, memory, options. Please contact regarding your specific requirements.
CMOS 0.13µ Data Sheet
FSC13_021202
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CMOS 0.13µ Data Sheet
FSC13_021202
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